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GET /api/patches/135486/?format=api
{ "id": 135486, "url": "https://patches.dpdk.org/api/patches/135486/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-12-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231221180529.18687-12-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231221180529.18687-12-ajit.khaparde@broadcom.com", "date": "2023-12-21T18:05:22", "name": "[11/18] net/bnxt: add ESP and AH header based RSS support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a06cd1187ad001b41efa870b922c06308f160d18", "submitter": { "id": 501, "url": "https://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "https://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231221180529.18687-12-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 30650, "url": "https://patches.dpdk.org/api/series/30650/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30650", "date": "2023-12-21T18:05:11", "name": "bnxt patchset", "version": 1, "mbox": "https://patches.dpdk.org/series/30650/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/135486/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/135486/checks/", "tags": {}, "related": [], "headers": { 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add ESP and AH header based RSS support", "Date": "Thu, 21 Dec 2023 10:05:22 -0800", "Message-Id": "<20231221180529.18687-12-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.39.2 (Apple Git-143)", "In-Reply-To": "<20231221180529.18687-1-ajit.khaparde@broadcom.com>", "References": "<20231221180529.18687-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "multipart/signed; protocol=\"application/pkcs7-signature\";\n micalg=sha-256; boundary=\"0000000000001db02e060d08f3ac\"", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Check if the firmware can support RSS based on these types and\nprogram the hardware accodringly when requested when the\nfirmware indicates that the underlying hardware supports the\nfunctionality.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Damodharam Ammepalli <damodharam.ammepalli@broadcom.com>\n---\n drivers/net/bnxt/bnxt.h | 6 ++\n drivers/net/bnxt/bnxt_ethdev.c | 8 ++-\n drivers/net/bnxt/bnxt_hwrm.c | 104 +++++++++++++++++++++++++--------\n drivers/net/bnxt/bnxt_hwrm.h | 1 +\n drivers/net/bnxt/bnxt_vnic.c | 13 ++++-\n 5 files changed, 102 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h\nindex e7b288c849..576688bbff 100644\n--- a/drivers/net/bnxt/bnxt.h\n+++ b/drivers/net/bnxt/bnxt.h\n@@ -809,6 +809,12 @@ struct bnxt {\n #define BNXT_VNIC_CAP_XOR_MODE\t\tBIT(5)\n #define BNXT_VNIC_CAP_CHKSM_MODE\tBIT(6)\n #define BNXT_VNIC_CAP_L2_CQE_MODE\tBIT(8)\n+#define BNXT_VNIC_CAP_AH_SPI4_CAP\tBIT(9)\n+#define BNXT_VNIC_CAP_AH_SPI6_CAP\tBIT(10)\n+#define BNXT_VNIC_CAP_ESP_SPI4_CAP\tBIT(11)\n+#define BNXT_VNIC_CAP_ESP_SPI6_CAP\tBIT(12)\n+#define BNXT_VNIC_CAP_AH_SPI_CAP\t(BNXT_VNIC_CAP_AH_SPI4_CAP | BNXT_VNIC_CAP_AH_SPI6_CAP)\n+#define BNXT_VNIC_CAP_ESP_SPI_CAP\t(BNXT_VNIC_CAP_ESP_SPI4_CAP | BNXT_VNIC_CAP_ESP_SPI6_CAP)\n \n \tunsigned int\t\trx_nr_rings;\n \tunsigned int\t\trx_cp_nr_rings;\ndiff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex ef5e65ff16..5b775e7716 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -995,8 +995,12 @@ uint64_t bnxt_eth_rss_support(struct bnxt *bp)\n \t\t RTE_ETH_RSS_LEVEL_MASK;\n \n \tif (bp->vnic_cap_flags & BNXT_VNIC_CAP_CHKSM_MODE)\n-\t\tsupport |= (RTE_ETH_RSS_IPV4_CHKSUM |\n-\t\t\t RTE_ETH_RSS_L4_CHKSUM);\n+\t\tsupport |= RTE_ETH_RSS_IPV4_CHKSUM |\n+\t\t\t RTE_ETH_RSS_L4_CHKSUM;\n+\tif (bp->vnic_cap_flags & BNXT_VNIC_CAP_AH_SPI_CAP)\n+\t\tsupport |= RTE_ETH_RSS_AH;\n+\tif (bp->vnic_cap_flags & BNXT_VNIC_CAP_ESP_SPI_CAP)\n+\t\tsupport |= RTE_ETH_RSS_ESP;\n \n \treturn support;\n }\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex 587433a878..1ac3f30074 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -1031,6 +1031,21 @@ int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)\n \tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP)\n \t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_CHKSM_MODE;\n \n+\tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP)\n+\t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_L2_CQE_MODE;\n+\n+\tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP)\n+\t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_AH_SPI4_CAP;\n+\n+\tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP)\n+\t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_AH_SPI6_CAP;\n+\n+\tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP)\n+\t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_ESP_SPI4_CAP;\n+\n+\tif (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP)\n+\t\tbp->vnic_cap_flags |= BNXT_VNIC_CAP_ESP_SPI6_CAP;\n+\n \tbp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);\n \n \tHWRM_UNLOCK();\n@@ -2412,6 +2427,52 @@ int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \treturn rc;\n }\n \n+static uint32_t bnxt_sanitize_rss_type(struct bnxt *bp, uint32_t types)\n+{\n+\tuint32_t hwrm_type = types;\n+\n+\tif (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 &&\n+\t !(bp->vnic_cap_flags & BNXT_VNIC_CAP_ESP_SPI4_CAP))\n+\t\thwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4;\n+\tif (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 &&\n+\t !(bp->vnic_cap_flags & BNXT_VNIC_CAP_ESP_SPI6_CAP))\n+\t\thwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6;\n+\n+\tif (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 &&\n+\t !(bp->vnic_cap_flags & BNXT_VNIC_CAP_AH_SPI4_CAP))\n+\t\thwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4;\n+\n+\tif (types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 &&\n+\t !(bp->vnic_cap_flags & BNXT_VNIC_CAP_AH_SPI6_CAP))\n+\t\thwrm_type &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6;\n+\n+\treturn hwrm_type;\n+}\n+\n+#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG\n+static int\n+bnxt_hwrm_vnic_rss_qcfg_p5(struct bnxt *bp)\n+{\n+\tstruct hwrm_vnic_rss_qcfg_output *resp = bp->hwrm_cmd_resp_addr;\n+\tstruct hwrm_vnic_rss_qcfg_input req = {0};\n+\tint rc;\n+\n+\tHWRM_PREP(&req, HWRM_VNIC_RSS_QCFG, BNXT_USE_CHIMP_MB);\n+\t/* vnic_id and rss_ctx_idx must be set to INVALID to read the\n+\t * global hash mode.\n+\t */\n+\treq.vnic_id = rte_cpu_to_le_16(BNXT_DFLT_VNIC_ID_INVALID);\n+\treq.rss_ctx_idx = rte_cpu_to_le_16(BNXT_RSS_CTX_IDX_INVALID);\n+\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req),\n+\t\t\t\t BNXT_USE_CHIMP_MB);\n+\tHWRM_CHECK_RESULT();\n+\tHWRM_UNLOCK();\n+\tPMD_DRV_LOG(DEBUG, \"RSS QCFG: Hash level %d\\n\", resp->hash_mode_flags);\n+\n+\treturn rc;\n+}\n+#endif\n+\n static int\n bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n {\n@@ -2425,7 +2486,10 @@ bnxt_hwrm_vnic_rss_cfg_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \t\tHWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n \t\treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n-\t\treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n+\t\treq.hash_type = rte_cpu_to_le_32(bnxt_sanitize_rss_type(bp, vnic->hash_type));\n+\t\t/* Update req with vnic ring_select_mode for P7 */\n+\t\tif (BNXT_CHIP_P7(bp))\n+\t\t\treq.ring_select_mode = vnic->ring_select_mode;\n \t\t/* When the vnic_id in the request field is a valid\n \t\t * one, the hash_mode_flags in the request field must\n \t\t * be set to DEFAULT. And any request to change the\n@@ -2524,7 +2588,7 @@ bnxt_hwrm_vnic_rss_cfg_non_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \n \tHWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n-\treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n+\treq.hash_type = rte_cpu_to_le_32(bnxt_sanitize_rss_type(bp, vnic->hash_type));\n \treq.hash_mode_flags = vnic->hash_mode;\n \n \treq.ring_grp_tbl_addr =\n@@ -2550,29 +2614,18 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,\n \tif (!vnic->rss_table)\n \t\treturn 0;\n \n-\tif (BNXT_CHIP_P5(bp)) {\n-\t\trc = bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t\t/* Configuring the hash mode has to be done in a\n-\t\t * different VNIC_RSS_CFG HWRM command by setting\n-\t\t * vnic_id & rss_ctx_id to INVALID. The only\n-\t\t * exception to this is if the USER doesn't want\n-\t\t * to change the default behavior. So, ideally\n-\t\t * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 should be\n-\t\t * called when user is explicitly changing the hash\n-\t\t * mode. However, this logic will unconditionally\n-\t\t * call bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 to\n-\t\t * simplify the logic as there is no harm in calling\n-\t\t * bnxt_hwrm_vnic_rss_cfg_hash_mode_p5 even when\n-\t\t * user is not setting it explicitly. Because, this\n-\t\t * routine will convert the default value to inner\n-\t\t * which is our adapter's default behavior.\n-\t\t */\n+\t/* Handle all the non-thor skus rss here */\n+\tif (!BNXT_CHIP_P5_P7(bp))\n+\t\treturn bnxt_hwrm_vnic_rss_cfg_non_p5(bp, vnic);\n+\n+\t/* Handle Thor2 and Thor skus rss here */\n+\trc = bnxt_hwrm_vnic_rss_cfg_p5(bp, vnic);\n+\n+\t/* configure hash mode for Thor/Thor2 */\n+\tif (!rc)\n \t\treturn bnxt_hwrm_vnic_rss_cfg_hash_mode_p5(bp, vnic);\n-\t}\n \n-\treturn bnxt_hwrm_vnic_rss_cfg_non_p5(bp, vnic);\n+\treturn rc;\n }\n \n int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,\n@@ -5343,7 +5396,7 @@ int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,\n \treturn 0;\n }\n \n-static int\n+int\n bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n {\n \tstruct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n@@ -5363,8 +5416,9 @@ bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \t\tHWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n \t\treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n-\t\treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n+\t\treq.hash_type = rte_cpu_to_le_32(bnxt_sanitize_rss_type(bp, vnic->hash_type));\n \t\treq.hash_mode_flags = vnic->hash_mode;\n+\t\treq.ring_select_mode = vnic->ring_select_mode;\n \n \t\treq.ring_grp_tbl_addr =\n \t\t rte_cpu_to_le_64(vnic->rss_table_dma_addr +\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex 3d5194257b..56b232d7de 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -357,6 +357,7 @@ void bnxt_free_hwrm_tx_ring(struct bnxt *bp, int queue_index);\n int bnxt_alloc_hwrm_tx_ring(struct bnxt *bp, int queue_index);\n int bnxt_hwrm_config_host_mtu(struct bnxt *bp);\n int bnxt_vnic_rss_clear_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n+int bnxt_vnic_rss_configure_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n int bnxt_hwrm_func_backing_store_qcaps_v2(struct bnxt *bp);\n int bnxt_hwrm_func_backing_store_cfg_v2(struct bnxt *bp,\n \t\t\t\t\tstruct bnxt_ctx_mem *ctxm);\ndiff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c\nindex bf1f0ea09f..5ea34f7cb6 100644\n--- a/drivers/net/bnxt/bnxt_vnic.c\n+++ b/drivers/net/bnxt/bnxt_vnic.c\n@@ -268,6 +268,8 @@ uint32_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type)\n \tif ((rte_type & RTE_ETH_RSS_IPV4) ||\n \t (rte_type & RTE_ETH_RSS_ECPRI))\n \t\thwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;\n+\tif (rte_type & RTE_ETH_RSS_ECPRI)\n+\t\thwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;\n \tif (rte_type & RTE_ETH_RSS_NONFRAG_IPV4_TCP)\n \t\thwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;\n \tif (rte_type & RTE_ETH_RSS_NONFRAG_IPV4_UDP)\n@@ -278,9 +280,12 @@ uint32_t bnxt_rte_to_hwrm_hash_types(uint64_t rte_type)\n \t\thwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;\n \tif (rte_type & RTE_ETH_RSS_NONFRAG_IPV6_UDP)\n \t\thwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;\n-\tif (rte_type & RTE_ETH_RSS_IPV4_CHKSUM)\n-\t\thwrm_type |=\n-\t\t\tHWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM;\n+\tif (rte_type & RTE_ETH_RSS_ESP)\n+\t\thwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 |\n+\t\t\t HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6;\n+\tif (rte_type & RTE_ETH_RSS_AH)\n+\t\thwrm_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 |\n+\t\t\t HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6;\n \n \treturn hwrm_type;\n }\n@@ -1327,7 +1332,9 @@ int bnxt_rte_flow_to_hwrm_ring_select_mode(enum rte_eth_hash_function hash_f,\n \t\t\t/* Checksum mode cannot with hash func makes no sense */\n \t\t\tvnic->ring_select_mode =\n \t\t\t\tHWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM;\n+\t\t\tvnic->hash_f_local = RTE_ETH_HASH_FUNCTION_TOEPLITZ;\n \t\t\t/* shadow copy types as !hash_f is always true with default func */\n+\t\t\tvnic->rss_types_local = types;\n \t\t\treturn 0;\n \t\t}\n \t\tPMD_DRV_LOG(ERR, \"Hash function not supported with checksun type\\n\");\n", "prefixes": [ "11/18" ] }