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GET /api/patches/134958/?format=api
{ "id": 134958, "url": "https://patches.dpdk.org/api/patches/134958/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231208082835.2817601-2-amitprakashs@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231208082835.2817601-2-amitprakashs@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231208082835.2817601-2-amitprakashs@marvell.com", "date": "2023-12-08T08:28:34", "name": "[2/3] dma/cnxk: support for DMA event enqueue dequeue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dce01db27c8d911253e7ba4a71fae7ee0aa42568", "submitter": { "id": 2699, "url": "https://patches.dpdk.org/api/people/2699/?format=api", "name": "Amit Prakash Shukla", "email": "amitprakashs@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231208082835.2817601-2-amitprakashs@marvell.com/mbox/", "series": [ { "id": 30491, "url": "https://patches.dpdk.org/api/series/30491/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30491", "date": "2023-12-08T08:28:33", "name": "[1/3] common/cnxk: dma result to an offset of the event", "version": 1, "mbox": "https://patches.dpdk.org/series/30491/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/134958/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/134958/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AC61A436A6;\n\tFri, 8 Dec 2023 09:29:27 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9BE2C42FD7;\n\tFri, 8 Dec 2023 09:29:27 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id AC27342F04\n for <dev@dpdk.org>; Fri, 8 Dec 2023 09:29:26 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3B81KRCj028755 for <dev@dpdk.org>; Fri, 8 Dec 2023 00:29:26 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3uubddc94q-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 08 Dec 2023 00:29:21 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Fri, 8 Dec 2023 00:29:10 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Fri, 8 Dec 2023 00:29:09 -0800", "from localhost.localdomain (unknown [10.28.36.157])\n by maili.marvell.com (Postfix) with ESMTP id 7DFE43F7088;\n Fri, 8 Dec 2023 00:29:07 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Fqpfr3vDpfW+iK2FlyrYI/Z3s+9SnLSO0rkPKpklJ4g=;\n b=UT9y4ccgFCuRDIjgqRvAMfB6h9Itv8SxC6ZQZgxpcB3sVC6y9n0CfeCGLon9KoOj/CXq\n HL1BclDOzwjxjFo/6p08eAuzWj7ecnACphR2iEHdEQ/8oYI5U+vu7o4iQAuN7vdnY2+6\n 9lif8MlSFQJ8/7ek/M/relnJq8Kv1QmVy13a2hlF51ILyYft1bCVLDUT1IFRT80ZmR2U\n 42zg6OFMNCcwcG1RTTDonut4AWNVyzZS/MOjV2q4Y/Q6rsNkzKwOcfL7qxPp01jLpdtb\n durxbCmMfmUPaZE0aOmmJ1fFjUQt7Q0TWTRef53pCsxhmTLo8hQxTQqODZBTGkwI1NKJ 5g==", "From": "Amit Prakash Shukla <amitprakashs@marvell.com>", "To": "Pavan Nikhilesh <pbhagavatula@marvell.com>, Shijith Thotton\n <sthotton@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>", "CC": "<dev@dpdk.org>, <jerinj@marvell.com>, <ndabilpuram@marvell.com>, \"Amit\n Prakash Shukla\" <amitprakashs@marvell.com>", "Subject": "[PATCH 2/3] dma/cnxk: support for DMA event enqueue dequeue", "Date": "Fri, 8 Dec 2023 13:58:34 +0530", "Message-ID": "<20231208082835.2817601-2-amitprakashs@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231208082835.2817601-1-amitprakashs@marvell.com>", "References": "<20231208082835.2817601-1-amitprakashs@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "R5wqBrPI7cDFp69YkUpAQT5RbQpEvf_j", "X-Proofpoint-GUID": "R5wqBrPI7cDFp69YkUpAQT5RbQpEvf_j", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-12-08_04,2023-12-07_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added cnxk driver support for dma event enqueue and dequeue.\nAlso added changes for work queue entry completion status.\n\nSigned-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 5 +\n drivers/dma/cnxk/cnxk_dma_event_dp.h | 21 +++\n drivers/dma/cnxk/cnxk_dmadev.c | 2 +-\n drivers/dma/cnxk/cnxk_dmadev.h | 18 ++-\n drivers/dma/cnxk/cnxk_dmadev_fp.c | 212 +++++++++++++++++++++++++++\n drivers/dma/cnxk/meson.build | 9 +-\n drivers/dma/cnxk/version.map | 9 ++\n 7 files changed, 273 insertions(+), 3 deletions(-)\n create mode 100644 drivers/dma/cnxk/cnxk_dma_event_dp.h\n create mode 100644 drivers/dma/cnxk/version.map", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex cccb8a0304..9ff1052c53 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -227,3 +227,8 @@ ethernet devices connected to event device to override this applications can\n use `force_rx_bp=1` device arguments.\n Using unique mempool per each ethernet device is recommended when they are\n connected to event device.\n+\n+DMA adapter new mode support\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+DMA driver does not support DMA adapter configured in new mode.\ndiff --git a/drivers/dma/cnxk/cnxk_dma_event_dp.h b/drivers/dma/cnxk/cnxk_dma_event_dp.h\nnew file mode 100644\nindex 0000000000..a526d25665\n--- /dev/null\n+++ b/drivers/dma/cnxk/cnxk_dma_event_dp.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2023 Marvell.\n+ */\n+\n+#ifndef _CNXK_DMA_EVENT_DP_H_\n+#define _CNXK_DMA_EVENT_DP_H_\n+\n+#include <stdint.h>\n+\n+#include <rte_common.h>\n+#include <rte_eventdev.h>\n+\n+__rte_internal\n+uint16_t cn10k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events);\n+\n+__rte_internal\n+uint16_t cn9k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events);\n+\n+__rte_internal\n+uintptr_t cnxk_dma_adapter_dequeue(uintptr_t get_work1);\n+#endif /* _CNXK_DMA_EVENT_DP_H_ */\ndiff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c\nindex 1e7f49792c..a748331da1 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev.c\n@@ -592,7 +592,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_de\n \trdpi = &dpivf->rdpi;\n \n \trdpi->pci_dev = pci_dev;\n-\trc = roc_dpi_dev_init(rdpi);\n+\trc = roc_dpi_dev_init(rdpi, offsetof(struct cnxk_dpi_compl_s, wqecs));\n \tif (rc < 0)\n \t\tgoto err_out_free;\n \ndiff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h\nindex 350ae73b5c..332325d6b6 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.h\n+++ b/drivers/dma/cnxk/cnxk_dmadev.h\n@@ -19,6 +19,8 @@\n \n #include <roc_api.h>\n \n+#include \"cnxk_dma_event_dp.h\"\n+\n #define CNXK_DPI_MAX_POINTER\t\t 15\n #define CNXK_DPI_STRM_INC(s, var)\t ((s).var = ((s).var + 1) & (s).max_cnt)\n #define CNXK_DPI_STRM_DEC(s, var)\t ((s).var = ((s).var - 1) == -1 ? (s).max_cnt :\t\\\n@@ -40,6 +42,11 @@\n */\n #define CNXK_DPI_REQ_CDATA 0xFF\n \n+/* Set Completion data to 0xDEADBEEF when request submitted for SSO.\n+ * This helps differentiate if the dequeue is called after cnxk enueue.\n+ */\n+#define CNXK_DPI_REQ_SSO_CDATA 0xDEADBEEF\n+\n union cnxk_dpi_instr_cmd {\n \tuint64_t u;\n \tstruct cn9k_dpi_instr_cmd {\n@@ -85,7 +92,10 @@ union cnxk_dpi_instr_cmd {\n \n struct cnxk_dpi_compl_s {\n \tuint64_t cdata;\n-\tvoid *cb_data;\n+\tvoid *op;\n+\tuint16_t dev_id;\n+\tuint16_t vchan;\n+\tuint32_t wqecs;\n };\n \n struct cnxk_dpi_cdesc_data_s {\n@@ -95,6 +105,11 @@ struct cnxk_dpi_cdesc_data_s {\n \tuint16_t tail;\n };\n \n+struct cnxk_dma_adapter_info {\n+\tbool enabled; /* Set if vchan queue is added to dma adapter. */\n+\tstruct rte_mempool *req_mp; /* DMA inflight request mempool. */\n+};\n+\n struct cnxk_dpi_conf {\n \tunion cnxk_dpi_instr_cmd cmd;\n \tstruct cnxk_dpi_cdesc_data_s c_desc;\n@@ -103,6 +118,7 @@ struct cnxk_dpi_conf {\n \tuint16_t desc_idx;\n \tstruct rte_dma_stats stats;\n \tuint64_t completed_offset;\n+\tstruct cnxk_dma_adapter_info adapter_info;\n };\n \n struct cnxk_dpi_vf_s {\ndiff --git a/drivers/dma/cnxk/cnxk_dmadev_fp.c b/drivers/dma/cnxk/cnxk_dmadev_fp.c\nindex 95df19a2db..85a8e1310e 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev_fp.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev_fp.c\n@@ -5,6 +5,13 @@\n #include <rte_vect.h>\n \n #include \"cnxk_dmadev.h\"\n+#include <rte_event_dma_adapter.h>\n+\n+#include <cn10k_eventdev.h>\n+#include <cnxk_eventdev.h>\n+#include <rte_mcslock.h>\n+\n+rte_mcslock_t *dpi_ml;\n \n static __plt_always_inline void\n __dpi_cpy_scalar(uint64_t *src, uint64_t *dst, uint8_t n)\n@@ -434,3 +441,208 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n \n \treturn dpi_conf->desc_idx++;\n }\n+\n+static inline uint64_t\n+cnxk_dma_adapter_format_event(uint64_t event)\n+{\n+\tuint64_t w0;\n+\tw0 = (event & 0xFFC000000000) >> 6 |\n+\t (event & 0xFFFFFFF) | RTE_EVENT_TYPE_DMADEV << 28;\n+\n+\treturn w0;\n+}\n+\n+uint16_t\n+cn10k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tconst struct rte_dma_sge *src, *dst;\n+\tstruct rte_event_dma_adapter_op *op;\n+\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tstruct cnxk_dpi_conf *dpi_conf;\n+\tstruct cnxk_dpi_vf_s *dpivf;\n+\tstruct rte_event *rsp_info;\n+\tstruct cn10k_sso_hws *work;\n+\tuint16_t nb_src, nb_dst;\n+\trte_mcslock_t ml_me;\n+\tuint64_t hdr[4];\n+\tuint16_t count;\n+\tint rc;\n+\n+\twork = (struct cn10k_sso_hws *)ws;\n+\n+\tfor (count = 0; count < nb_events; count++) {\n+\t\top = ev[count].event_ptr;\n+\t\trsp_info = (struct rte_event *)((uint8_t *)op +\n+\t\t\t sizeof(struct rte_event_dma_adapter_op));\n+\t\tdpivf =\trte_dma_fp_objs[op->dma_dev_id].dev_private;\n+\t\tdpi_conf = &dpivf->conf[op->vchan];\n+\n+\t\tif (unlikely(rte_mempool_get(dpi_conf->adapter_info.req_mp, (void **)&comp_ptr)))\n+\t\t\treturn count;\n+\n+\t\tcomp_ptr->op = op;\n+\t\tcomp_ptr->dev_id = op->dma_dev_id;\n+\t\tcomp_ptr->vchan = op->vchan;\n+\t\tcomp_ptr->cdata = CNXK_DPI_REQ_SSO_CDATA;\n+\n+\t\tnb_src = op->nb_src & CNXK_DPI_MAX_POINTER;\n+\t\tnb_dst = op->nb_dst & CNXK_DPI_MAX_POINTER;\n+\n+\t\thdr[0] = dpi_conf->cmd.u | ((uint64_t)DPI_HDR_PT_WQP << 54);\n+\t\thdr[0] |= (nb_dst << 6) | nb_src;\n+\t\thdr[1] = ((uint64_t)comp_ptr);\n+\t\thdr[2] = cnxk_dma_adapter_format_event(rsp_info->event);\n+\n+\t\tsrc = &op->src_seg[0];\n+\t\tdst = &op->dst_seg[0];\n+\n+\t\tif (CNXK_TAG_IS_HEAD(work->gw_rdata) ||\n+\t\t ((CNXK_TT_FROM_TAG(work->gw_rdata) == SSO_TT_ORDERED) &&\n+\t\t (rsp_info->sched_type & DPI_HDR_TT_MASK) ==\n+\t\t\t RTE_SCHED_TYPE_ORDERED))\n+\t\t\troc_sso_hws_head_wait(work->base);\n+\n+\t\trte_mcslock_lock(&dpi_ml, &ml_me);\n+\t\trc = __dpi_queue_write_sg(dpivf, hdr, src, dst, nb_src, nb_dst);\n+\t\tif (unlikely(rc)) {\n+\t\t\trte_mcslock_unlock(&dpi_ml, &ml_me);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tif (op->flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\t\trte_wmb();\n+\t\t\tplt_write64(dpi_conf->pnum_words + CNXK_DPI_CMD_LEN(nb_src, nb_dst),\n+\t\t\t\t dpivf->rdpi.rbase + DPI_VDMA_DBELL);\n+\t\t\tdpi_conf->stats.submitted += dpi_conf->pending + 1;\n+\t\t\tdpi_conf->pnum_words = 0;\n+\t\t\tdpi_conf->pending = 0;\n+\t\t} else {\n+\t\t\tdpi_conf->pnum_words += CNXK_DPI_CMD_LEN(nb_src, nb_dst);\n+\t\t\tdpi_conf->pending++;\n+\t\t}\n+\t\trte_mcslock_unlock(&dpi_ml, &ml_me);\n+\t}\n+\n+\treturn count;\n+}\n+\n+uint16_t\n+cn9k_dma_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tconst struct rte_dma_sge *fptr, *lptr;\n+\tstruct rte_event_dma_adapter_op *op;\n+\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tstruct cnxk_dpi_conf *dpi_conf;\n+\tstruct cnxk_dpi_vf_s *dpivf;\n+\tstruct rte_event *rsp_info;\n+\tstruct cn9k_sso_hws *work;\n+\tuint16_t nb_src, nb_dst;\n+\trte_mcslock_t ml_me;\n+\tuint64_t hdr[4];\n+\tuint16_t count;\n+\tint rc;\n+\n+\twork = (struct cn9k_sso_hws *)ws;\n+\n+\tfor (count = 0; count < nb_events; count++) {\n+\t\top = ev[count].event_ptr;\n+\t\trsp_info = (struct rte_event *)((uint8_t *)op +\n+\t\t\t sizeof(struct rte_event_dma_adapter_op));\n+\t\tdpivf =\trte_dma_fp_objs[op->dma_dev_id].dev_private;\n+\t\tdpi_conf = &dpivf->conf[op->vchan];\n+\n+\t\tif (unlikely(rte_mempool_get(dpi_conf->adapter_info.req_mp, (void **)&comp_ptr)))\n+\t\t\treturn count;\n+\n+\t\tcomp_ptr->op = op;\n+\t\tcomp_ptr->dev_id = op->dma_dev_id;\n+\t\tcomp_ptr->vchan = op->vchan;\n+\t\tcomp_ptr->cdata = CNXK_DPI_REQ_SSO_CDATA;\n+\n+\t\thdr[1] = dpi_conf->cmd.u | ((uint64_t)DPI_HDR_PT_WQP << 36);\n+\t\thdr[2] = (uint64_t)comp_ptr;\n+\n+\t\tnb_src = op->nb_src & CNXK_DPI_MAX_POINTER;\n+\t\tnb_dst = op->nb_dst & CNXK_DPI_MAX_POINTER;\n+\t\t/*\n+\t\t * For inbound case, src pointers are last pointers.\n+\t\t * For all other cases, src pointers are first pointers.\n+\t\t */\n+\t\tif (((dpi_conf->cmd.u >> 48) & DPI_HDR_XTYPE_MASK) == DPI_XTYPE_INBOUND) {\n+\t\t\tfptr = &op->dst_seg[0];\n+\t\t\tlptr = &op->src_seg[0];\n+\t\t\tRTE_SWAP(nb_src, nb_dst);\n+\t\t} else {\n+\t\t\tfptr = &op->src_seg[0];\n+\t\t\tlptr = &op->dst_seg[0];\n+\t\t}\n+\n+\t\thdr[0] = ((uint64_t)nb_dst << 54) | (uint64_t)nb_src << 48;\n+\t\thdr[0] |= cnxk_dma_adapter_format_event(rsp_info->event);\n+\n+\t\tif ((rsp_info->sched_type & DPI_HDR_TT_MASK) == RTE_SCHED_TYPE_ORDERED)\n+\t\t\troc_sso_hws_head_wait(work->base);\n+\n+\t\trte_mcslock_lock(&dpi_ml, &ml_me);\n+\t\trc = __dpi_queue_write_sg(dpivf, hdr, fptr, lptr, nb_src, nb_dst);\n+\t\tif (unlikely(rc)) {\n+\t\t\trte_mcslock_unlock(&dpi_ml, &ml_me);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tif (op->flags & RTE_DMA_OP_FLAG_SUBMIT) {\n+\t\t\trte_wmb();\n+\t\t\tplt_write64(dpi_conf->pnum_words + CNXK_DPI_CMD_LEN(nb_src, nb_dst),\n+\t\t\t\t dpivf->rdpi.rbase + DPI_VDMA_DBELL);\n+\t\t\tdpi_conf->stats.submitted += dpi_conf->pending + 1;\n+\t\t\tdpi_conf->pnum_words = 0;\n+\t\t\tdpi_conf->pending = 0;\n+\t\t} else {\n+\t\t\tdpi_conf->pnum_words += CNXK_DPI_CMD_LEN(nb_src, nb_dst);\n+\t\t\tdpi_conf->pending++;\n+\t\t}\n+\t\trte_mcslock_unlock(&dpi_ml, &ml_me);\n+\t}\n+\n+\treturn count;\n+}\n+\n+uintptr_t\n+cnxk_dma_adapter_dequeue(uintptr_t get_work1)\n+{\n+\tstruct rte_event_dma_adapter_op *op;\n+\tstruct cnxk_dpi_compl_s *comp_ptr;\n+\tstruct cnxk_dpi_conf *dpi_conf;\n+\tstruct cnxk_dpi_vf_s *dpivf;\n+\trte_mcslock_t ml_me;\n+\tuint8_t *wqecs;\n+\n+\tcomp_ptr = (struct cnxk_dpi_compl_s *)get_work1;\n+\n+\t/* Dequeue can be called without calling cnx_enqueue in case of\n+\t * dma_adapter. When its called from adapter, dma op will not be\n+\t * embedded in completion pointer. In those cases return op.\n+\t */\n+\tif (comp_ptr->cdata != CNXK_DPI_REQ_SSO_CDATA)\n+\t\treturn (uintptr_t)comp_ptr;\n+\n+\tdpivf =\trte_dma_fp_objs[comp_ptr->dev_id].dev_private;\n+\tdpi_conf = &dpivf->conf[comp_ptr->vchan];\n+\n+\trte_mcslock_lock(&dpi_ml, &ml_me);\n+\twqecs = (uint8_t *)&comp_ptr->wqecs;\n+\tif (__atomic_load_n(wqecs, __ATOMIC_RELAXED) != 0)\n+\t\tdpi_conf->stats.errors++;\n+\n+\t/* Take into account errors also. This is similar to\n+\t * cnxk_dmadev_completed_status().\n+\t */\n+\tdpi_conf->stats.completed++;\n+\trte_mcslock_unlock(&dpi_ml, &ml_me);\n+\n+\top = (struct rte_event_dma_adapter_op *)comp_ptr->op;\n+\n+\trte_mempool_put(dpi_conf->adapter_info.req_mp, comp_ptr);\n+\n+\treturn (uintptr_t)op;\n+}\ndiff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build\nindex e557349368..8ccc1c2cb7 100644\n--- a/drivers/dma/cnxk/meson.build\n+++ b/drivers/dma/cnxk/meson.build\n@@ -8,6 +8,13 @@ foreach flag: error_cflags\n endif\n endforeach\n \n-deps += ['bus_pci', 'common_cnxk', 'dmadev']\n+driver_sdk_headers = files(\n+ 'cnxk_dma_event_dp.h',\n+)\n+\n+deps += ['bus_pci', 'common_cnxk', 'dmadev', 'eventdev']\n+\n+includes += include_directories('../../event/cnxk')\n+\n sources = files('cnxk_dmadev.c', 'cnxk_dmadev_fp.c')\n require_iova_in_mbuf = false\ndiff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map\nnew file mode 100644\nindex 0000000000..6cc1c6aaa5\n--- /dev/null\n+++ b/drivers/dma/cnxk/version.map\n@@ -0,0 +1,9 @@\n+INTERNAL {\n+\tglobal:\n+\n+\tcn10k_dma_adapter_enqueue;\n+\tcn9k_dma_adapter_enqueue;\n+\tcnxk_dma_adapter_dequeue;\n+\n+\tlocal: *;\n+};\n", "prefixes": [ "2/3" ] }