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GET /api/patches/134884/?format=api
{ "id": 134884, "url": "https://patches.dpdk.org/api/patches/134884/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231206030025.2334584-1-junfeng.guo@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231206030025.2334584-1-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231206030025.2334584-1-junfeng.guo@intel.com", "date": "2023-12-06T03:00:25", "name": "raw/ntb: refactor to support NTB on 5th Gen Intel Xeon", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f5af7316b6359c06af6f58f0998336b6cf2f0d65", "submitter": { "id": 1785, "url": "https://patches.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231206030025.2334584-1-junfeng.guo@intel.com/mbox/", "series": [ { "id": 30460, "url": "https://patches.dpdk.org/api/series/30460/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30460", "date": "2023-12-06T03:00:25", "name": "raw/ntb: refactor to support NTB on 5th Gen Intel Xeon", "version": 1, "mbox": "https://patches.dpdk.org/series/30460/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/134884/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/134884/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 858C943685;\n\tWed, 6 Dec 2023 04:01:22 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0D9A540EE5;\n\tWed, 6 Dec 2023 04:01:22 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.9])\n by mails.dpdk.org (Postfix) with ESMTP id 9DE6240ED1\n for <dev@dpdk.org>; Wed, 6 Dec 2023 04:01:20 +0100 (CET)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 Dec 2023 19:01:20 -0800", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.110.217])\n by orsmga007.jf.intel.com with ESMTP; 05 Dec 2023 19:01:14 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1701831681; x=1733367681;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=wHaTC6UqZgMRPnqg/vWRi2xFcart3hWEB4B23jCxX/Y=;\n b=K+42+6bwwth2uoP7W9bf/84zUMN7LpcaUWgg8DbcSG3ZOxJHdV06MgMB\n yiza/jia55wQJBXstmwneH6sxB5pciAs01WoNI9mJP8CjNAyd2SKNnRJ5\n BzPNx302WIBkwW5RlQ/ShNB6Fy6rCvP4b9hKcSF0IKVVw+5Ayv49UlpFe\n hqUSxlldTHgA9woe0n4fna08jkMw79VDy1NbGZVobnA9nYIgCV6cOci5j\n W7oeHw2lAfTlW32Go0ckiBxWPm4hNo7gA6JVTz8o5Ysdr4SynmI560MKG\n qJhWcvR/NIiGCw9BervtvUBTxchgHCZhM9O2ltcfADfI6KXCAMKRUxSkl A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10915\"; a=\"12712654\"", "E=Sophos;i=\"6.04,254,1695711600\"; d=\"scan'208\";a=\"12712654\"", "E=McAfee;i=\"6600,9927,10915\"; a=\"764554041\"", "E=Sophos;i=\"6.04,254,1695711600\"; d=\"scan'208\";a=\"764554041\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, omkar.maslekar@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>", "Subject": "[PATCH] raw/ntb: refactor to support NTB on 5th Gen Intel Xeon", "Date": "Wed, 6 Dec 2023 11:00:25 +0800", "Message-Id": "<20231206030025.2334584-1-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Refactor to support for 5th Gen Intel Xeon Scalable processors. Note that\nNTB devices within the 3rd, 4th and 5th Gen Intel Xeon Scalable processors\nshare the same device id, and compliant to PCIe 4.0 spec.\nIt is more reasonable to distinguish NTB devices by their PCIe generation.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n doc/guides/rawdevs/ntb.rst | 7 +-\n doc/guides/rel_notes/release_24_03.rst | 4 +\n drivers/raw/ntb/ntb.c | 8 +-\n drivers/raw/ntb/ntb.h | 5 +-\n drivers/raw/ntb/ntb_hw_intel.c | 182 +++++++++++--------------\n drivers/raw/ntb/ntb_hw_intel.h | 90 ++++++------\n usertools/dpdk-devbind.py | 8 +-\n 7 files changed, 149 insertions(+), 155 deletions(-)", "diff": "diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst\nindex f8befc6594..ee452af4fd 100644\n--- a/doc/guides/rawdevs/ntb.rst\n+++ b/doc/guides/rawdevs/ntb.rst\n@@ -153,6 +153,7 @@ Limitation\n \n This PMD is only supported on Intel Xeon Platforms:\n \n-- 4th Generation Intel® Xeon® Scalable Processors.\n-- 3rd Generation Intel® Xeon® Scalable Processors.\n-- 2nd Generation Intel® Xeon® Scalable Processors.\n+- 5th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E)\n+- 4th Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E)\n+- 3rd Generation Intel® Xeon® Scalable Processors. (NTB GEN4 device id: 0x347E)\n+- 2nd Generation Intel® Xeon® Scalable Processors. (NTB GEN3 device id: 0x201C)\ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex bd84875d4f..a43f64b199 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -55,6 +55,10 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added support for Intel NTB with 5th Gen Intel Xeon Scalable processors..**\n+\n+Added NTB device (4th generation) support for the 5th Gen Intel Xeon Platforms.\n+\n * **Improved support of RSS hash algorithm.**\n \n * Added new function ``rte_eth_find_rss_algo`` to get RSS hash\ndiff --git a/drivers/raw/ntb/ntb.c b/drivers/raw/ntb/ntb.c\nindex 0ed4c14592..2a163eff60 100644\n--- a/drivers/raw/ntb/ntb.c\n+++ b/drivers/raw/ntb/ntb.c\n@@ -24,8 +24,8 @@\n #include \"ntb.h\"\n \n static const struct rte_pci_id pci_id_ntb_map[] = {\n-\t{ RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_SKX) },\n-\t{ RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_ICX) },\n+\t{ RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_GEN3) },\n+\t{ RTE_PCI_DEVICE(NTB_INTEL_VENDOR_ID, NTB_INTEL_DEV_ID_B2B_GEN4) },\n \t{ .vendor_id = 0, /* sentinel */ },\n };\n \n@@ -1378,8 +1378,8 @@ ntb_init_hw(struct rte_rawdev *dev, struct rte_pci_device *pci_dev)\n \thw->link_width = NTB_WIDTH_NONE;\n \n \tswitch (pci_dev->id.device_id) {\n-\tcase NTB_INTEL_DEV_ID_B2B_SKX:\n-\tcase NTB_INTEL_DEV_ID_B2B_ICX:\n+\tcase NTB_INTEL_DEV_ID_B2B_GEN3:\n+\tcase NTB_INTEL_DEV_ID_B2B_GEN4:\n \t\thw->ntb_ops = &intel_ntb_ops;\n \t\tbreak;\n \tdefault:\ndiff --git a/drivers/raw/ntb/ntb.h b/drivers/raw/ntb/ntb.h\nindex a30a6b60c9..d2e6d566ed 100644\n--- a/drivers/raw/ntb/ntb.h\n+++ b/drivers/raw/ntb/ntb.h\n@@ -17,9 +17,8 @@ extern int ntb_logtype;\n #define NTB_INTEL_VENDOR_ID 0x8086\n \n /* Device IDs */\n-#define NTB_INTEL_DEV_ID_B2B_SKX 0x201C\n-#define NTB_INTEL_DEV_ID_B2B_ICX 0x347E\n-#define NTB_INTEL_DEV_ID_B2B_SPR 0x347E\n+#define NTB_INTEL_DEV_ID_B2B_GEN3 0x201C\n+#define NTB_INTEL_DEV_ID_B2B_GEN4 0x347E\n \n /* Reserved to app to use. */\n #define NTB_SPAD_USER \"spad_user_\"\ndiff --git a/drivers/raw/ntb/ntb_hw_intel.c b/drivers/raw/ntb/ntb_hw_intel.c\nindex 9b4465176a..3e2094437f 100644\n--- a/drivers/raw/ntb/ntb_hw_intel.c\n+++ b/drivers/raw/ntb/ntb_hw_intel.c\n@@ -25,25 +25,6 @@ static enum xeon_ntb_bar intel_ntb_bar[] = {\n \tXEON_NTB_BAR45,\n };\n \n-static inline int\n-is_gen3_ntb(const struct ntb_hw *hw)\n-{\n-\tif (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_SKX)\n-\t\treturn 1;\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-is_gen4_ntb(const struct ntb_hw *hw)\n-{\n-\tif (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_ICX ||\n-\t hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_SPR)\n-\t\treturn 1;\n-\n-\treturn 0;\n-}\n-\n static int\n intel_ntb3_check_ppd(struct ntb_hw *hw)\n {\n@@ -51,35 +32,36 @@ intel_ntb3_check_ppd(struct ntb_hw *hw)\n \tint ret;\n \n \tret = rte_pci_read_config(hw->pci_dev, ®_val,\n-\t\t\t\t sizeof(reg_val), XEON_PPD_OFFSET);\n+\t\t\t\t sizeof(reg_val), XEON_NTB3_PPD_OFFSET);\n \tif (ret < 0) {\n \t\tNTB_LOG(ERR, \"Cannot get NTB PPD (PCIe port definition).\");\n \t\treturn -EIO;\n \t}\n \n \t/* Check connection topo type. Only support B2B. */\n-\tswitch (reg_val & XEON_PPD_CONN_MASK) {\n-\tcase XEON_PPD_CONN_B2B:\n+\tswitch (reg_val & XEON_NTB3_PPD_CONN_MASK) {\n+\tcase XEON_NTB3_PPD_CONN_B2B:\n \t\tNTB_LOG(INFO, \"Topo B2B (back to back) is using.\");\n \t\tbreak;\n-\tcase XEON_PPD_CONN_TRANSPARENT:\n-\tcase XEON_PPD_CONN_RP:\n \tdefault:\n \t\tNTB_LOG(ERR, \"Not supported conn topo. Please use B2B.\");\n \t\treturn -EINVAL;\n \t}\n \n-\t/* Check device type. */\n-\tif (reg_val & XEON_PPD_DEV_DSD) {\n+\t/* Check device config status. */\n+\tswitch (reg_val & XEON_NTB3_PPD_DEV_MASK) {\n+\tcase XEON_NTB3_PPD_DEV_DSD:\n \t\tNTB_LOG(INFO, \"DSD, Downstream Device.\");\n \t\thw->topo = NTB_TOPO_B2B_DSD;\n-\t} else {\n+\t\tbreak;\n+\tcase XEON_NTB3_PPD_DEV_USD:\n \t\tNTB_LOG(INFO, \"USD, Upstream device.\");\n \t\thw->topo = NTB_TOPO_B2B_USD;\n+\t\tbreak;\n \t}\n \n \t/* Check if bar4 is split. Do not support split bar. */\n-\tif (reg_val & XEON_PPD_SPLIT_BAR_MASK) {\n+\tif (reg_val & XEON_NTB3_PPD_SPLIT_BAR_MASK) {\n \t\tNTB_LOG(ERR, \"Do not support split bar.\");\n \t\treturn -EINVAL;\n \t}\n@@ -91,8 +73,8 @@ static int\n intel_ntb4_check_ppd_for_ICX(struct ntb_hw *hw, uint32_t reg_val)\n {\n \t/* Check connection topo type. Only support B2B. */\n-\tswitch (reg_val & XEON_GEN4_PPD_CONN_MASK) {\n-\tcase XEON_GEN4_PPD_CONN_B2B:\n+\tswitch (reg_val & XEON_GEN3_NTB4_PPD_CONN_MASK) {\n+\tcase XEON_GEN3_NTB4_PPD_CONN_B2B:\n \t\tNTB_LOG(INFO, \"Topo B2B (back to back) is using.\");\n \t\tbreak;\n \tdefault:\n@@ -100,38 +82,16 @@ intel_ntb4_check_ppd_for_ICX(struct ntb_hw *hw, uint32_t reg_val)\n \t\treturn -EINVAL;\n \t}\n \n-\t/* Check device type. */\n-\tif (reg_val & XEON_GEN4_PPD_DEV_DSD) {\n+\t/* Check device config status. */\n+\tswitch (reg_val & XEON_GEN3_NTB4_PPD_DEV_MASK) {\n+\tcase XEON_GEN3_NTB4_PPD_DEV_DSD:\n \t\tNTB_LOG(INFO, \"DSD, Downstream Device.\");\n \t\thw->topo = NTB_TOPO_B2B_DSD;\n-\t} else {\n-\t\tNTB_LOG(INFO, \"USD, Upstream device.\");\n-\t\thw->topo = NTB_TOPO_B2B_USD;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-intel_ntb4_check_ppd_for_SPR(struct ntb_hw *hw, uint32_t reg_val)\n-{\n-\t/* Check connection topo type. Only support B2B. */\n-\tswitch (reg_val & XEON_SPR_PPD_CONN_MASK) {\n-\tcase XEON_SPR_PPD_CONN_B2B:\n-\t\tNTB_LOG(INFO, \"Topo B2B (back to back) is using.\");\n \t\tbreak;\n-\tdefault:\n-\t\tNTB_LOG(ERR, \"Not supported conn topo. Please use B2B.\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Check device type. */\n-\tif (reg_val & XEON_SPR_PPD_DEV_DSD) {\n-\t\tNTB_LOG(INFO, \"DSD, Downstream Device.\");\n-\t\thw->topo = NTB_TOPO_B2B_DSD;\n-\t} else {\n+\tcase XEON_GEN3_NTB4_PPD_DEV_USD:\n \t\tNTB_LOG(INFO, \"USD, Upstream device.\");\n \t\thw->topo = NTB_TOPO_B2B_USD;\n+\t\tbreak;\n \t}\n \n \treturn 0;\n@@ -152,19 +112,36 @@ intel_ntb4_check_ppd(struct ntb_hw *hw)\n \t\treturn -EIO;\n \t}\n \n-\treg_val = rte_read32(hw->hw_addr + XEON_GEN4_PPD1_OFFSET);\n+\treg_val = rte_read32(hw->hw_addr + XEON_NTB4_PPD1_OFFSET);\n \n-\t/* Distinguish HW platform (ICX/SPR) via PCI Revision ID */\n-\tif (revision_id > NTB_PCI_DEV_REVISION_ICX_MAX)\n-\t\tret = intel_ntb4_check_ppd_for_SPR(hw, reg_val);\n-\telse if (revision_id >= NTB_PCI_DEV_REVISION_ICX_MIN)\n-\t\tret = intel_ntb4_check_ppd_for_ICX(hw, reg_val);\n-\telse {\n-\t\tNTB_LOG(ERR, \"Invalid NTB PCI Device Revision ID.\");\n-\t\treturn -EIO;\n+\t/* Distinguish HW platform (3rd Gen Xeon) via PCI Revision ID */\n+\tif (revision_id <= NTB_PCI_DEV_REVISION_ICX_MAX &&\n+\t is_gen4_ntb(hw->pci_dev))\n+\t\treturn intel_ntb4_check_ppd_for_ICX(hw, reg_val);\n+\n+\t/* Check connection topo type. Only support B2B. */\n+\tswitch (reg_val & XEON_NTB4_PPD_CONN_MASK) {\n+\tcase XEON_NTB4_PPD_CONN_B2B:\n+\t\tNTB_LOG(INFO, \"Topo B2B (back to back) is using.\");\n+\t\tbreak;\n+\tdefault:\n+\t\tNTB_LOG(ERR, \"Not supported conn topo. Please use B2B.\");\n+\t\treturn -EINVAL;\n \t}\n \n-\treturn ret;\n+\t/* Check device config status. */\n+\tswitch (reg_val & XEON_NTB4_PPD_DEV_MASK) {\n+\tcase XEON_NTB4_PPD_DEV_DSD:\n+\t\tNTB_LOG(INFO, \"DSD, Downstream Device.\");\n+\t\thw->topo = NTB_TOPO_B2B_DSD;\n+\t\tbreak;\n+\tcase XEON_NTB4_PPD_DEV_USD:\n+\t\tNTB_LOG(INFO, \"USD, Upstream device.\");\n+\t\thw->topo = NTB_TOPO_B2B_USD;\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n }\n \n static int\n@@ -181,10 +158,11 @@ intel_ntb_dev_init(const struct rte_rawdev *dev)\n \n \thw->hw_addr = (char *)hw->pci_dev->mem_resource[0].addr;\n \n-\tif (is_gen3_ntb(hw))\n+\tif (is_gen3_ntb(hw->pci_dev))\n+\t\t/* PPD is in config space for NTB Gen3 */\n \t\tret = intel_ntb3_check_ppd(hw);\n-\telse if (is_gen4_ntb(hw))\n-\t\t/* PPD is in MMIO but not config space for NTB Gen4 */\n+\telse if (is_gen4_ntb(hw->pci_dev))\n+\t\t/* PPD is in MMIO for NTB Gen4 */\n \t\tret = intel_ntb4_check_ppd(hw);\n \telse {\n \t\tNTB_LOG(ERR, \"Cannot init device for unsupported device.\");\n@@ -275,7 +253,7 @@ intel_ntb_mw_set_trans(const struct rte_rawdev *dev, int mw_idx,\n \trte_write64(base, xlat_addr);\n \trte_write64(limit, limit_addr);\n \n-\tif (is_gen3_ntb(hw)) {\n+\tif (is_gen3_ntb(hw->pci_dev)) {\n \t\t/* Setup the external point so that remote can access. */\n \t\txlat_off = XEON_EMBAR1_OFFSET + 8 * mw_idx;\n \t\txlat_addr = hw->hw_addr + xlat_off;\n@@ -286,10 +264,10 @@ intel_ntb_mw_set_trans(const struct rte_rawdev *dev, int mw_idx,\n \t\tbase &= ~0xf;\n \t\tlimit = base + size;\n \t\trte_write64(limit, limit_addr);\n-\t} else if (is_gen4_ntb(hw)) {\n+\t} else if (is_gen4_ntb(hw->pci_dev)) {\n \t\t/* Set translate base address index register */\n-\t\txlat_off = XEON_GEN4_IM1XBASEIDX_OFFSET +\n-\t\t\t mw_idx * XEON_GEN4_XBASEIDX_INTERVAL;\n+\t\txlat_off = XEON_NTB4_IM1XBASEIDX_OFFSET +\n+\t\t\t mw_idx * XEON_XBASEIDX_INTERVAL;\n \t\txlat_addr = hw->hw_addr + xlat_off;\n \t\trte_write16(rte_log2_u64(size), xlat_addr);\n \t} else {\n@@ -335,16 +313,16 @@ intel_ntb_get_link_status(const struct rte_rawdev *dev)\n \t\treturn -EINVAL;\n \t}\n \n-\tif (is_gen3_ntb(hw)) {\n-\t\treg_off = XEON_GEN3_LINK_STATUS_OFFSET;\n+\tif (is_gen3_ntb(hw->pci_dev)) {\n+\t\treg_off = XEON_NTB3_LINK_STATUS_OFFSET;\n \t\tret = rte_pci_read_config(hw->pci_dev, ®_val,\n \t\t\t\t\t sizeof(reg_val), reg_off);\n \t\tif (ret < 0) {\n \t\t\tNTB_LOG(ERR, \"Unable to get link status.\");\n \t\t\treturn -EIO;\n \t\t}\n-\t} else if (is_gen4_ntb(hw)) {\n-\t\treg_off = XEON_GEN4_LINK_STATUS_OFFSET;\n+\t} else if (is_gen4_ntb(hw->pci_dev)) {\n+\t\treg_off = XEON_NTB4_LINK_STATUS_OFFSET;\n \t\treg_val = rte_read16(hw->hw_addr + reg_off);\n \t} else {\n \t\tNTB_LOG(ERR, \"Cannot get link status for unsupported device.\");\n@@ -402,20 +380,20 @@ intel_ntb_gen4_set_link(const struct ntb_hw *hw, bool up)\n \t\tntb_ctrl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;\n \t\trte_write32(ntb_ctrl, reg_addr);\n \n-\t\treg_addr = hw->hw_addr + XEON_GEN4_LINK_CTRL_OFFSET;\n+\t\treg_addr = hw->hw_addr + XEON_NTB4_LINK_CTRL_OFFSET;\n \t\tlink_ctrl = rte_read16(reg_addr);\n-\t\tlink_ctrl &= ~XEON_GEN4_LINK_CTRL_LINK_DIS;\n+\t\tlink_ctrl &= ~XEON_NTB4_LINK_CTRL_LINK_DIS;\n \t\trte_write16(link_ctrl, reg_addr);\n \n \t\t/* start link training */\n-\t\treg_addr = hw->hw_addr + XEON_GEN4_PPD0_OFFSET;\n+\t\treg_addr = hw->hw_addr + XEON_NTB4_PPD0_OFFSET;\n \t\tppd0 = rte_read32(reg_addr);\n-\t\tppd0 |= XEON_GEN4_PPD_LINKTRN;\n+\t\tppd0 |= XEON_NTB4_PPD_LINKTRN;\n \t\trte_write32(ppd0, reg_addr);\n \n \t\t/* make sure link training has started */\n \t\tppd0 = rte_read32(reg_addr);\n-\t\tif (!(ppd0 & XEON_GEN4_PPD_LINKTRN)) {\n+\t\tif (!(ppd0 & XEON_NTB4_PPD_LINKTRN)) {\n \t\t\tNTB_LOG(ERR, \"Link is not training.\");\n \t\t\treturn -EINVAL;\n \t\t}\n@@ -426,9 +404,9 @@ intel_ntb_gen4_set_link(const struct ntb_hw *hw, bool up)\n \t\tntb_ctrl &= ~(NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP);\n \t\trte_write32(ntb_ctrl, reg_addr);\n \n-\t\treg_addr = hw->hw_addr + XEON_GEN4_LINK_CTRL_OFFSET;\n+\t\treg_addr = hw->hw_addr + XEON_NTB4_LINK_CTRL_OFFSET;\n \t\tlink_ctrl = rte_read16(reg_addr);\n-\t\tlink_ctrl |= XEON_GEN4_LINK_CTRL_LINK_DIS;\n+\t\tlink_ctrl |= XEON_NTB4_LINK_CTRL_LINK_DIS;\n \t\trte_write16(link_ctrl, reg_addr);\n \t}\n \n@@ -441,9 +419,9 @@ intel_ntb_set_link(const struct rte_rawdev *dev, bool up)\n \tstruct ntb_hw *hw = dev->dev_private;\n \tint ret = 0;\n \n-\tif (is_gen3_ntb(hw))\n+\tif (is_gen3_ntb(hw->pci_dev))\n \t\tret = intel_ntb_gen3_set_link(hw, up);\n-\telse if (is_gen4_ntb(hw))\n+\telse if (is_gen4_ntb(hw->pci_dev))\n \t\tret = intel_ntb_gen4_set_link(hw, up);\n \telse {\n \t\tNTB_LOG(ERR, \"Cannot set link for unsupported device.\");\n@@ -466,11 +444,11 @@ intel_ntb_spad_read(const struct rte_rawdev *dev, int spad, bool peer)\n \t}\n \n \t/* When peer is true, read peer spad reg */\n-\tif (is_gen3_ntb(hw))\n-\t\treg_off = peer ? XEON_GEN3_B2B_SPAD_OFFSET :\n+\tif (is_gen3_ntb(hw->pci_dev))\n+\t\treg_off = peer ? XEON_NTB3_B2B_SPAD_OFFSET :\n \t\t\t\tXEON_IM_SPAD_OFFSET;\n-\telse if (is_gen4_ntb(hw))\n-\t\treg_off = peer ? XEON_GEN4_B2B_SPAD_OFFSET :\n+\telse if (is_gen4_ntb(hw->pci_dev))\n+\t\treg_off = peer ? XEON_NTB4_B2B_SPAD_OFFSET :\n \t\t\t\tXEON_IM_SPAD_OFFSET;\n \telse {\n \t\tNTB_LOG(ERR, \"Cannot read spad for unsupported device.\");\n@@ -496,11 +474,11 @@ intel_ntb_spad_write(const struct rte_rawdev *dev, int spad,\n \t}\n \n \t/* When peer is true, write peer spad reg */\n-\tif (is_gen3_ntb(hw))\n-\t\treg_off = peer ? XEON_GEN3_B2B_SPAD_OFFSET :\n+\tif (is_gen3_ntb(hw->pci_dev))\n+\t\treg_off = peer ? XEON_NTB3_B2B_SPAD_OFFSET :\n \t\t\t\tXEON_IM_SPAD_OFFSET;\n-\telse if (is_gen4_ntb(hw))\n-\t\treg_off = peer ? XEON_GEN4_B2B_SPAD_OFFSET :\n+\telse if (is_gen4_ntb(hw->pci_dev))\n+\t\treg_off = peer ? XEON_NTB4_B2B_SPAD_OFFSET :\n \t\t\t\tXEON_IM_SPAD_OFFSET;\n \telse {\n \t\tNTB_LOG(ERR, \"Cannot write spad for unsupported device.\");\n@@ -538,9 +516,9 @@ intel_ntb_db_clear(const struct rte_rawdev *dev, uint64_t db_bits)\n \tdb_off = XEON_IM_INT_STATUS_OFFSET;\n \tdb_addr = hw->hw_addr + db_off;\n \n-\tif (is_gen4_ntb(hw))\n-\t\trte_write16(XEON_GEN4_SLOTSTS_DLLSCS,\n-\t\t\t hw->hw_addr + XEON_GEN4_SLOTSTS);\n+\tif (is_gen4_ntb(hw->pci_dev))\n+\t\trte_write16(XEON_NTB4_SLOTSTS_DLLSCS,\n+\t\t\t hw->hw_addr + XEON_NTB4_SLOTSTS);\n \trte_write64(db_bits, db_addr);\n \n \treturn 0;\n@@ -598,10 +576,10 @@ intel_ntb_vector_bind(const struct rte_rawdev *dev, uint8_t intr, uint8_t msix)\n \t}\n \n \t/* Bind intr source to msix vector */\n-\tif (is_gen3_ntb(hw))\n-\t\treg_off = XEON_GEN3_INTVEC_OFFSET;\n-\telse if (is_gen4_ntb(hw))\n-\t\treg_off = XEON_GEN4_INTVEC_OFFSET;\n+\tif (is_gen3_ntb(hw->pci_dev))\n+\t\treg_off = XEON_NTB3_INTVEC_OFFSET;\n+\telse if (is_gen4_ntb(hw->pci_dev))\n+\t\treg_off = XEON_NTB4_INTVEC_OFFSET;\n \telse {\n \t\tNTB_LOG(ERR, \"Cannot bind vectors for unsupported device.\");\n \t\treturn -ENOTSUP;\ndiff --git a/drivers/raw/ntb/ntb_hw_intel.h b/drivers/raw/ntb/ntb_hw_intel.h\nindex 9587104f80..5a45785b57 100644\n--- a/drivers/raw/ntb/ntb_hw_intel.h\n+++ b/drivers/raw/ntb/ntb_hw_intel.h\n@@ -5,6 +5,8 @@\n #ifndef _NTB_HW_INTEL_H_\n #define _NTB_HW_INTEL_H_\n \n+#include \"ntb.h\"\n+\n /* Supported PCI device revision ID range for ICX */\n #define NTB_PCI_DEV_REVISION_ICX_MIN\t0x02\n #define NTB_PCI_DEV_REVISION_ICX_MAX\t0x0F\n@@ -38,13 +40,14 @@\n #define XEON_DEVSTS_OFFSET\t\t0x009a\n #define XEON_UNCERRSTS_OFFSET\t\t0x014c\n #define XEON_CORERRSTS_OFFSET\t\t0x0158\n-#define XEON_GEN3_LINK_STATUS_OFFSET\t0x01a2\n-/* Link status and PPD are in MMIO but not config space for Gen4 NTB */\n-#define XEON_GEN4_PPD0_OFFSET\t\t0xb0d4\n-#define XEON_GEN4_PPD1_OFFSET\t\t0xb4c0\n-#define XEON_GEN4_LINK_CTRL_OFFSET\t0xb050\n-#define XEON_GEN4_LINK_STATUS_OFFSET\t0xb052\n-#define XEON_GEN4_LINK_CTRL_LINK_DIS\t0x0010\n+#define XEON_NTB3_LINK_STATUS_OFFSET\t0x01a2\n+/* Link status and PPD are in MMIO but not config space for Gen4/5 NTB */\n+#define XEON_NTB4_PPD0_OFFSET\t\t0xb0d4\n+#define XEON_NTB4_PPD1_OFFSET\t\t0xb4c0\n+#define XEON_NTB4_LINK_CTRL_OFFSET\t0xb050\n+#define XEON_NTB4_LINK_STATUS_OFFSET\t0xb052\n+#define XEON_NTB4_LINK_CTRL_LINK_DIS\t0x0010\n+\n \n #define XEON_NTBCNTL_OFFSET\t\t0x0000\n #define XEON_BAR_INTERVAL_OFFSET\t0x0010\n@@ -52,17 +55,17 @@\n #define XEON_IMBAR1XLMT_OFFSET\t\t0x0018\t\t/* SBAR2LMT */\n #define XEON_IMBAR2XBASE_OFFSET\t\t0x0020\t\t/* SBAR4XLAT */\n #define XEON_IMBAR2XLMT_OFFSET\t\t0x0028\t\t/* SBAR4LMT */\n-#define XEON_GEN4_XBASEIDX_INTERVAL\t0x0002\n-#define XEON_GEN4_IM1XBASEIDX_OFFSET\t0x0074\n-#define XEON_GEN4_IM2XBASEIDX_OFFSET\t0x0076\n+#define XEON_XBASEIDX_INTERVAL\t\t0x0002\n+#define XEON_NTB4_IM1XBASEIDX_OFFSET\t0x0074\n+#define XEON_NTB4_IM2XBASEIDX_OFFSET\t0x0076\n #define XEON_IM_INT_STATUS_OFFSET\t0x0040\n #define XEON_IM_INT_DISABLE_OFFSET\t0x0048\n #define XEON_IM_SPAD_OFFSET\t\t0x0080\t\t/* SPAD */\n-#define XEON_GEN3_B2B_SPAD_OFFSET\t0x0180\t\t/* GEN3 B2B SPAD */\n-#define XEON_GEN4_B2B_SPAD_OFFSET\t0x8080\t\t/* GEN4 B2B SPAD */\n+#define XEON_NTB3_B2B_SPAD_OFFSET\t0x0180\t\t/* NTB GEN3 B2B SPAD */\n+#define XEON_NTB4_B2B_SPAD_OFFSET\t0x8080\t\t/* NTB GEN4/5 B2B SPAD */\n #define XEON_USMEMMISS_OFFSET\t\t0x0070\n-#define XEON_GEN3_INTVEC_OFFSET\t\t0x00d0\n-#define XEON_GEN4_INTVEC_OFFSET\t\t0x0050\n+#define XEON_NTB3_INTVEC_OFFSET\t\t0x00d0\n+#define XEON_NTB4_INTVEC_OFFSET\t\t0x0050\n #define XEON_IM_DOORBELL_OFFSET\t\t0x0100\t\t/* SDOORBELL0 */\n #define XEON_EMBAR0XBASE_OFFSET\t\t0x4008\t\t/* B2B_XLAT */\n #define XEON_EMBAR1XBASE_OFFSET\t\t0x4010\t\t/* PBAR2XLAT */\n@@ -78,30 +81,29 @@\n #define XEON_EMBAR1_OFFSET\t\t0x4518\t\t/* SBAR23BASE */\n #define XEON_EMBAR2_OFFSET\t\t0x4520\t\t/* SBAR45BASE */\n \n-#define XEON_PPD_OFFSET\t\t\t0x00d4\n-#define XEON_PPD_CONN_MASK\t\t0x03\n-#define XEON_PPD_CONN_TRANSPARENT\t0x00\n-#define XEON_PPD_CONN_B2B\t\t0x01\n-#define XEON_PPD_CONN_RP\t\t0x02\n-#define XEON_PPD_DEV_MASK\t\t0x10\n-#define XEON_PPD_DEV_USD\t\t0x00\n-#define XEON_PPD_DEV_DSD\t\t0x10\n-#define XEON_PPD_SPLIT_BAR_MASK\t\t0x40\n-\n-#define XEON_GEN4_PPD_CONN_MASK\t\t0x0300\n-#define XEON_GEN4_PPD_CONN_B2B\t\t0x0200\n-#define XEON_GEN4_PPD_DEV_MASK\t\t0x1000\n-#define XEON_GEN4_PPD_DEV_DSD\t\t0x1000\n-#define XEON_GEN4_PPD_DEV_USD\t\t0x0000\n-#define XEON_GEN4_PPD_LINKTRN\t\t0x0008\n-#define XEON_GEN4_SLOTSTS\t\t0xb05a\n-#define XEON_GEN4_SLOTSTS_DLLSCS\t0x100\n-\n-#define XEON_SPR_PPD_CONN_MASK\t\t0x0700\n-#define XEON_SPR_PPD_CONN_B2B\t\t0x0200\n-#define XEON_SPR_PPD_DEV_MASK\t\t0x4000\n-#define XEON_SPR_PPD_DEV_DSD\t\t0x4000\n-#define XEON_SPR_PPD_DEV_USD\t\t0x0000\n+#define XEON_NTB3_PPD_OFFSET\t\t0x00d4\n+#define XEON_NTB3_PPD_CONN_MASK\t\t0x03\n+#define XEON_NTB3_PPD_CONN_B2B\t\t0x01\n+#define XEON_NTB3_PPD_DEV_MASK\t\t0x10\n+#define XEON_NTB3_PPD_DEV_USD\t\t0x00\n+#define XEON_NTB3_PPD_DEV_DSD\t\t0x10\n+#define XEON_NTB3_PPD_SPLIT_BAR_MASK\t0x40\n+\n+#define XEON_GEN3_NTB4_PPD_CONN_MASK\t0x0300\n+#define XEON_GEN3_NTB4_PPD_CONN_B2B\t0x0200\n+#define XEON_GEN3_NTB4_PPD_DEV_MASK\t0x1000\n+#define XEON_GEN3_NTB4_PPD_DEV_DSD\t0x1000\n+#define XEON_GEN3_NTB4_PPD_DEV_USD\t0x0000\n+\n+#define XEON_NTB4_PPD_CONN_MASK\t\t0x0700\n+#define XEON_NTB4_PPD_CONN_B2B\t\t0x0200\n+#define XEON_NTB4_PPD_DEV_MASK\t\t0x4000\n+#define XEON_NTB4_PPD_DEV_DSD\t\t0x4000\n+#define XEON_NTB4_PPD_DEV_USD\t\t0x0000\n+\n+#define XEON_NTB4_PPD_LINKTRN\t\t0x0008\n+#define XEON_NTB4_SLOTSTS\t\t0xb05a\n+#define XEON_NTB4_SLOTSTS_DLLSCS\t0x100\n \n #define XEON_MW_COUNT\t\t\t2\n \n@@ -115,4 +117,16 @@\n \n extern const struct ntb_dev_ops intel_ntb_ops;\n \n+static inline bool\n+is_gen3_ntb(const struct rte_pci_device *pci_dev)\n+{\n+\treturn pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_GEN3;\n+}\n+\n+static inline bool\n+is_gen4_ntb(const struct rte_pci_device *pci_dev)\n+{\n+\treturn pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_GEN4;\n+}\n+\n #endif /* _NTB_HW_INTEL_H_ */\ndiff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py\nindex a278f5e7f3..230c81c5f3 100755\n--- a/usertools/dpdk-devbind.py\n+++ b/usertools/dpdk-devbind.py\n@@ -60,10 +60,8 @@\n 'SVendor': None, 'SDevice': None}\n intel_idxd_spr = {'Class': '08', 'Vendor': '8086', 'Device': '0b25',\n 'SVendor': None, 'SDevice': None}\n-intel_ntb_skx = {'Class': '06', 'Vendor': '8086', 'Device': '201c',\n- 'SVendor': None, 'SDevice': None}\n-intel_ntb_icx = {'Class': '06', 'Vendor': '8086', 'Device': '347e',\n- 'SVendor': None, 'SDevice': None}\n+intel_ntb = {'Class': '06', 'Vendor': '8086', 'Device': '201c,347e',\n+ 'SVendor': None, 'SDevice': None}\n \n cnxk_sso = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f9,a0fa',\n 'SVendor': None, 'SDevice': None}\n@@ -89,7 +87,7 @@\n regex_devices = [cn9k_ree]\n ml_devices = [cnxk_ml]\n misc_devices = [cnxk_bphy, cnxk_bphy_cgx, cnxk_inl_dev,\n- intel_ntb_skx, intel_ntb_icx,\n+ intel_ntb,\n virtio_blk]\n \n # global dict ethernet devices present. Dictionary indexed by PCI address.\n", "prefixes": [] }