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GET /api/patches/134762/?format=api
{ "id": 134762, "url": "https://patches.dpdk.org/api/patches/134762/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-18-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231203112543.844014-18-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231203112543.844014-18-michaelba@nvidia.com", "date": "2023-12-03T11:25:37", "name": "[v1,17/23] net/mlx5/hws: support GENEVE matching", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b919d1457570ecbc7cb6b39ac5f675cdbf292d98", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-18-michaelba@nvidia.com/mbox/", "series": [ { "id": 30433, "url": "https://patches.dpdk.org/api/series/30433/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30433", "date": "2023-12-03T11:25:23", "name": "net/mlx5: support Geneve and options for HWS", "version": 1, "mbox": "https://patches.dpdk.org/series/30433/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/134762/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/134762/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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Suanming Mou <suanmingm@nvidia.com>, Alex Vesker <valex@nvidia.com>", "Subject": "[PATCH v1 17/23] net/mlx5/hws: support GENEVE matching", "Date": "Sun, 3 Dec 2023 13:25:37 +0200", "Message-ID": "<20231203112543.844014-18-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231203112543.844014-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS1PEPF0001709B:EE_|SN7PR12MB8772:EE_", "X-MS-Office365-Filtering-Correlation-Id": "12b699e5-4ea5-4d41-6f3b-08dbf3f2b934", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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"X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF0001709B.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB8772", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Alex Vesker <valex@nvidia.com>\n\nAdd matching for GENEVE tunnel header.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 91 +++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 19 ++++++\n 2 files changed, 110 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex bab1869369..141941c309 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -11,6 +11,7 @@\n #define UDP_GTPU_PORT\t2152\n #define UDP_VXLAN_PORT\t4789\n #define UDP_PORT_MPLS\t6635\n+#define UDP_GENEVE_PORT 6081\n #define UDP_ROCEV2_PORT\t4791\n #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)\n \n@@ -172,6 +173,9 @@ struct mlx5dr_definer_conv_data {\n \tX(SET,\t\tsource_qp,\t\tv->queue,\t\tmlx5_rte_flow_item_sq) \\\n \tX(SET,\t\ttag,\t\t\tv->data,\t\trte_flow_item_tag) \\\n \tX(SET,\t\tmetadata,\t\tv->data,\t\trte_flow_item_meta) \\\n+\tX(SET_BE16,\tgeneve_protocol,\tv->protocol,\t\trte_flow_item_geneve) \\\n+\tX(SET,\t\tgeneve_udp_port,\tUDP_GENEVE_PORT,\trte_flow_item_geneve) \\\n+\tX(SET_BE16,\tgeneve_ctrl,\t\tv->ver_opt_len_o_c_rsvd0,\trte_flow_item_geneve) \\\n \tX(SET_BE16,\tgre_c_ver,\t\tv->c_rsvd0_ver,\t\trte_flow_item_gre) \\\n \tX(SET_BE16,\tgre_protocol_type,\tv->protocol,\t\trte_flow_item_gre) \\\n \tX(SET,\t\tipv4_protocol_gre,\tIPPROTO_GRE,\t\trte_flow_item_gre) \\\n@@ -682,6 +686,16 @@ mlx5dr_definer_mpls_label_set(struct mlx5dr_definer_fc *fc,\n \tmemcpy(tag + fc->byte_off + sizeof(v->label_tc_s), &v->ttl, sizeof(v->ttl));\n }\n \n+static void\n+mlx5dr_definer_geneve_vni_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_geneve *v = item_spec;\n+\n+\tmemcpy(tag + fc->byte_off, v->vni, sizeof(v->vni));\n+}\n+\n static void\n mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,\n \t\t\t const void *item_spec,\n@@ -2172,6 +2186,79 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_geneve(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t\tstruct rte_flow_item *item,\n+\t\t\t\tint item_idx)\n+{\n+\tconst struct rte_flow_item_geneve *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\tif (inner) {\n+\t\tDR_LOG(ERR, \"Inner GENEVE item not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\t/* In order to match on Geneve we must match on ip_protocol and l4_dport */\n+\tif (!cd->relaxed) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_udp_protocol_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type_bwc, inner);\n+\t\t}\n+\n+\t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_geneve_udp_port_set;\n+\t\t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n+\t\t}\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->rsvd1) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (m->ver_opt_len_o_c_rsvd0) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_CTRL];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_geneve_ctrl_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->bit_mask = __mlx5_mask(header_geneve, ver_opt_len_o_c_rsvd);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_geneve, ver_opt_len_o_c_rsvd);\n+\t}\n+\n+\tif (m->protocol) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_PROTO];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_geneve_protocol_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->byte_off += MLX5_BYTE_OFF(header_geneve, protocol_type);\n+\t\tfc->bit_mask = __mlx5_mask(header_geneve, protocol_type);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_geneve, protocol_type);\n+\t}\n+\n+\tif (!is_mem_zero(m->vni, 3)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_VNI];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_geneve_vni_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);\n+\t\tfc->bit_mask = __mlx5_mask(header_geneve, vni);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_geneve, vni);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt,\n \t\t\t struct mlx5dr_definer_fc *fc,\n@@ -2528,6 +2615,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\titem_flags |= MLX5_FLOW_LAYER_MPLS;\n \t\t\tcd.mpls_idx++;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GENEVE:\n+\t\t\tret = mlx5dr_definer_conv_item_geneve(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_GENEVE;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n \t\t\tret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_IB_BTH;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex e2be579303..c09c0be62e 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -91,6 +91,9 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_VPORT_REG_C_0,\n \tMLX5DR_DEFINER_FNAME_VXLAN_FLAGS,\n \tMLX5DR_DEFINER_FNAME_VXLAN_VNI,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_CTRL,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_PROTO,\n+\tMLX5DR_DEFINER_FNAME_GENEVE_VNI,\n \tMLX5DR_DEFINER_FNAME_SOURCE_QP,\n \tMLX5DR_DEFINER_FNAME_REG_0,\n \tMLX5DR_DEFINER_FNAME_REG_1,\n@@ -608,6 +611,22 @@ struct mlx5_ifc_header_gre_bits {\n \tu8 reserved_at_30[0x10];\n };\n \n+struct mlx5_ifc_header_geneve_bits {\n+\tunion {\n+\t\tu8 ver_opt_len_o_c_rsvd[0x10];\n+\t\tstruct {\n+\t\t\tu8 version[0x2];\n+\t\t\tu8 opt_len[0x6];\n+\t\t\tu8 o_flag[0x1];\n+\t\t\tu8 c_flag[0x1];\n+\t\t\tu8 reserved_at_a[0x6];\n+\t\t};\n+\t};\n+\tu8 protocol_type[0x10];\n+\tu8 vni[0x18];\n+\tu8 reserved_at_38[0x8];\n+};\n+\n struct mlx5_ifc_header_icmp_bits {\n \tunion {\n \t\tu8 icmp_dw1[0x20];\n", "prefixes": [ "v1", "17/23" ] }