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GET /api/patches/134755/?format=api
https://patches.dpdk.org/api/patches/134755/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-8-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231203112543.844014-8-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231203112543.844014-8-michaelba@nvidia.com", "date": "2023-12-03T11:25:27", "name": "[v1,07/23] common/mlx5: add GENEVE TLV option attribute structure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d699c8d5bd6058c119019609626b7f9a178a3686", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231203112543.844014-8-michaelba@nvidia.com/mbox/", "series": [ { "id": 30433, "url": "https://patches.dpdk.org/api/series/30433/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30433", "date": "2023-12-03T11:25:23", "name": "net/mlx5: support Geneve and options for HWS", "version": 1, "mbox": "https://patches.dpdk.org/series/30433/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/134755/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/134755/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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b=e0ZKZ0lqrUKALK8J0p6PsBBsRs+JapAba1pFt9XGNsjtbZbzIS5FNoc5ULJwIi8PXYJRWzJw1HEhMS2CvpZEMWrz4amkoYxwwWjcnlWIImehm3Q4xHVXjcBA8eBphY9kEJrWHotZwGTL3oDd8JE6CKEJE0Um+XnQlkiSclTYbsCCMGAd5jM6PT/mTJyYx3FLLZZJ40G9nzLpim1vQwRGZwOhDw7aZyd+OLmv/d5kOEKglUTAsm2gyJV647TYJXQNeahG0ujkBOSte1oP6Jv/nB4hGH8xGxDe4yng+wY+ikd3Pwp6f7k2HLZ8Kya7GCbrjHwdJEMJsiV96a4MC34sEQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v1 07/23] common/mlx5: add GENEVE TLV option attribute\n structure", "Date": "Sun, 3 Dec 2023 13:25:27 +0200", "Message-ID": "<20231203112543.844014-8-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231203112543.844014-1-michaelba@nvidia.com>", "References": "<20231203112543.844014-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000042AC:EE_|PH7PR12MB8105:EE_", "X-MS-Office365-Filtering-Correlation-Id": "00d16144-79be-4fe4-ed2e-08dbf3f2b051", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n xhyDe3OoE415oLOQuextY9cuzmOzELCgUPj3fOlHl+G3baHvl1TC9stZ+4S7TshAKCUAlDrQezl3mFHQ+xoCwEtyAQZZ0kwrDMVwzHMGnNMfxJqluIuc45Lzx9zcPQPcEIHlfhbyhYtYsBEPHYaSzL/emn9DC7sYl2lcoyBoqmFp0u/STT0bPCVCjnCx/8B8oPFoeSeVkxWbpznnwQ/ys0D6tswN5nZOBcsze2XGhXuRnNXnf0odcwtBwAf2F8Ob4U3kXHfROjqUQHFzhALULKeySX7X/5K5XDaqh7Kz1vPXh2WVS5jswVFbj+ug8tHpDM2H2GqwW7wcUfpm9Xlx65Ca66AHGqH/0rgUnRuum7x2Jo5WCGrHArZ5bieFGyF3shLUoiHbB1rGKHSC95pwP77z70Pt3HY8aRpmPMcP1vu+pziWITTY7ID6zLgn2U6HgLl49z10a/DSJrN5VX5caMSwe32lC6jIs8FkUiuFW1/yZe7gu7M+D2zsMVUN0PW4+lnOapRGISH/oSNPsZaoBfAA0Amkdkf2VJTsoH8iudluqxuPCeE/MIc8qiIzYnxTwE3copE1J5nSk1Gk+mpOGrUCUb8Nv+d33O8lqxkKtnJXINkS8AokkiuzC0SO7VOwyOO7ifp7xzp8tLI6F4Q1aIqK3i+SPTqUsO6bul3OghEcZuZPSH2mj/YeTJBBFA2t+zflFek6k4A3qHycKOBOkZcouFEW0TRr5pyVUtbAKreOxVPL7CqrLUX4CyZKmSAP", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(39860400002)(396003)(376002)(136003)(230922051799003)(186009)(451199024)(64100799003)(1800799012)(82310400011)(46966006)(36840700001)(40470700004)(55016003)(40480700001)(40460700003)(36860700001)(47076005)(7636003)(356005)(2906002)(5660300002)(82740400003)(83380400001)(6666004)(336012)(426003)(26005)(107886003)(7696005)(1076003)(2616005)(6286002)(478600001)(70586007)(70206006)(36756003)(41300700001)(54906003)(6916009)(4326008)(8676002)(86362001)(316002)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Dec 2023 11:26:26.7288 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 00d16144-79be-4fe4-ed2e-08dbf3f2b051", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000042AC.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB8105", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add a new structure \"mlx5_devx_geneve_tlv_option_attr\" to use in GENEVE\nTLV option creation.\nLater this structure will be used by GENEVE TLV option query operation\nas well.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 28 +++++++++++++---------------\n drivers/common/mlx5/mlx5_devx_cmds.h | 11 ++++++++++-\n drivers/net/mlx5/mlx5_flow_dv.c | 10 +++++++---\n 3 files changed, 30 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 74609e7cb2..9855a97bf4 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -2855,19 +2855,15 @@ mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,\n *\n * @param[in] ctx\n * Context returned from mlx5 open_device() glue function.\n- * @param [in] class\n- * TLV option variable value of class\n- * @param [in] type\n- * TLV option variable value of type\n- * @param [in] len\n- * TLV option variable value of len\n+ * @param[in] attr\n+ * Pointer to GENEVE TLV option attributes structure.\n *\n * @return\n * The DevX object created, NULL otherwise and rte_errno is set.\n */\n struct mlx5_devx_obj *\n mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\n-\t\tuint16_t class, uint8_t type, uint8_t len)\n+\t\t\t\t struct mlx5_devx_geneve_tlv_option_attr *attr)\n {\n \tuint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};\n \tuint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};\n@@ -2876,25 +2872,27 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\n \t\t\t\t\t\t 0, SOCKET_ID_ANY);\n \n \tif (!geneve_tlv_opt_obj) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate geneve tlv option object.\");\n+\t\tDRV_LOG(ERR, \"Failed to allocate GENEVE TLV option object.\");\n \t\trte_errno = ENOMEM;\n \t\treturn NULL;\n \t}\n \tvoid *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);\n \tvoid *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,\n-\t\t\tgeneve_tlv_opt);\n+\t\t\t\t geneve_tlv_opt);\n \tMLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,\n-\t\t\tMLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n+\t\t MLX5_CMD_OP_CREATE_GENERAL_OBJECT);\n \tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n \t\t MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);\n \tMLX5_SET(geneve_tlv_option, opt, option_class,\n-\t\t\trte_be_to_cpu_16(class));\n-\tMLX5_SET(geneve_tlv_option, opt, option_type, type);\n-\tMLX5_SET(geneve_tlv_option, opt, option_data_length, len);\n+\t\t rte_be_to_cpu_16(attr->option_class));\n+\tMLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type);\n+\tMLX5_SET(geneve_tlv_option, opt, option_data_length,\n+\t\t attr->option_data_len);\n \tgeneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,\n-\t\t\t\t\tsizeof(in), out, sizeof(out));\n+\t\t\t\t\t\t\t sizeof(in), out,\n+\t\t\t\t\t\t\t sizeof(out));\n \tif (!geneve_tlv_opt_obj->obj) {\n-\t\tDEVX_DRV_LOG(ERR, out, \"create GENEVE TLV\", NULL, 0);\n+\t\tDEVX_DRV_LOG(ERR, out, \"create GENEVE TLV option\", NULL, 0);\n \t\tmlx5_free(geneve_tlv_opt_obj);\n \t\treturn NULL;\n \t}\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 56ed911c2a..78337dff17 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -667,6 +667,15 @@ struct mlx5_devx_crypto_login_attr {\n \tuint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE];\n };\n \n+/*\n+ * GENEVE TLV option attributes structure, used by GENEVE TLV option create.\n+ */\n+struct mlx5_devx_geneve_tlv_option_attr {\n+\tuint32_t option_class:16;\n+\tuint32_t option_type:8;\n+\tuint32_t option_data_len:5;\n+};\n+\n /* mlx5_devx_cmds.c */\n \n __rte_internal\n@@ -777,7 +786,7 @@ int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id,\n __rte_internal\n struct mlx5_devx_obj *\n mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,\n-\t\tuint16_t class, uint8_t type, uint8_t len);\n+\t\t\t\t struct mlx5_devx_geneve_tlv_option_attr *attr);\n \n /**\n * Create virtio queue counters object DevX API.\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex f8e364dfdb..8894f51f4c 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -9928,11 +9928,15 @@ flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,\n \t\t\tgoto exit;\n \t\t}\n \t} else {\n+\t\tstruct mlx5_devx_geneve_tlv_option_attr attr = {\n+\t\t\t.option_class = geneve_opt_v->option_class,\n+\t\t\t.option_type = geneve_opt_v->option_type,\n+\t\t\t.option_data_len = geneve_opt_v->option_len,\n+\t\t};\n+\n \t\t/* Create a GENEVE TLV object and resource. */\n \t\tobj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,\n-\t\t\t\tgeneve_opt_v->option_class,\n-\t\t\t\tgeneve_opt_v->option_type,\n-\t\t\t\tgeneve_opt_v->option_len);\n+\t\t\t\t\t\t\t &attr);\n \t\tif (!obj) {\n \t\t\tret = rte_flow_error_set(error, ENODATA,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n", "prefixes": [ "v1", "07/23" ] }{ "id": 134755, "url": "