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GET /api/patches/134738/?format=api
{ "id": 134738, "url": "https://patches.dpdk.org/api/patches/134738/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231130164001.666702-3-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231130164001.666702-3-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231130164001.666702-3-michaelba@nvidia.com", "date": "2023-11-30T16:40:01", "name": "[v2,2/2] net/mlx5: add random item support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0f0ee9f73cfcf063e8a7afd79984d15ff038c4e6", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231130164001.666702-3-michaelba@nvidia.com/mbox/", "series": [ { "id": 30425, "url": "https://patches.dpdk.org/api/series/30425/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30425", "date": "2023-11-30T16:39:59", "name": "net/mlx5: add random item support", "version": 2, "mbox": "https://patches.dpdk.org/series/30425/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/134738/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/134738/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v2 2/2] net/mlx5: add random item support", "Date": "Thu, 30 Nov 2023 18:40:01 +0200", "Message-ID": "<20231130164001.666702-3-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231130164001.666702-1-michaelba@nvidia.com>", "References": "<20230822103600.3247680-1-michaelba@nvidia.com>\n <20231130164001.666702-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000971E5:EE_|SA3PR12MB9132:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7221afc8-4dbc-4815-42e8-08dbf1c30fbe", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 2ENiMLPhH7jgW5HcWsb/OxEWvN8RzvN8LRZcEp7ZUpdwB2g8t3PKGtAAJ2u7OiScH9rwdXIM603Y+9RCJdb/cI312BdRLr3qV2B9gOqE9F8+e2l9PR5PeMWNiKb4vFFTZHsCv4EGP7lRmvX8mdg3034vLsPvCcFyrFm8XY/rMWLWwXsOWwCL/34bOzYUwI5+aIsTZNFvys9iVYE46W1055PY8hhZyg+2QG+722F5qWnTmfXciIg9J9JITFLjL+O3b3/YB4HIi0KlBK9ER/dPK6a9G+aBensJY21BkRdz6IvELLWK2Rwx8gFyRgWjYZD+vNMaLNeNCepVnepnbjbd6elBR9pPK0jggiN0ZSXiUTqbL4sRIRKJ7AtfDSAVCRZBDIWTTexmAaAlQLSvGpsm6pJn7j7HZcrz4F9ZLbPnVRLiIL66FBt1OGTaz8XGQ1Mojgw5YJhRcu4w67WGHRAyNPdzj3Wai1ysrcuvDijTO7fioXQeNHSSjegj70GQQWFstsoVTKA45uqBVxlTS8O9Q82BrNei0CKeOL6kZsXmWHKb6YNI5QpeSs1L3E6zBoHTt6CDJufJnK9zBCDxZ9kgjDqeWoEWEjBpbaNn/+apOwGairquBvthC/FnR/nSU/1pqWAMp2W9KcTtrMfEB9D6K3frmcgybc7aIYNFxAgP2MFFJegyC9xoDRwvQDJTVtu2ysxxllFZDnKrmOn++LDyK4Vo07xxlmC3gNRNfBN7W9FtB2Jp5Tqy6Sm5EYoly+OM", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(136003)(376002)(396003)(346002)(230922051799003)(82310400011)(64100799003)(451199024)(186009)(1800799012)(46966006)(40470700004)(36840700001)(36860700001)(40460700003)(36756003)(82740400003)(86362001)(7636003)(70206006)(478600001)(8936002)(41300700001)(316002)(54906003)(70586007)(55016003)(8676002)(7696005)(6666004)(5660300002)(2616005)(2906002)(356005)(4326008)(6916009)(26005)(40480700001)(47076005)(426003)(336012)(6286002)(1076003)(83380400001)(107886003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Nov 2023 16:40:28.7319 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7221afc8-4dbc-4815-42e8-08dbf1c30fbe", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000971E5.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA3PR12MB9132", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for random item in HWS mode.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n doc/guides/nics/features/mlx5.ini | 1 +\n doc/guides/nics/mlx5.rst | 10 +++++++++-\n doc/guides/rel_notes/release_24_03.rst | 3 +++\n drivers/net/mlx5/mlx5_flow_dv.c | 5 +++++\n drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++\n 5 files changed, 23 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini\nindex 0739fe9d63..6261b7d657 100644\n--- a/doc/guides/nics/features/mlx5.ini\n+++ b/doc/guides/nics/features/mlx5.ini\n@@ -88,6 +88,7 @@ port_id = Y\n port_representor = Y\n ptype = Y\n quota = Y\n+random = Y\n tag = Y\n tcp = Y\n udp = Y\ndiff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 6b52fb93c5..129f7d9d24 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -167,7 +167,7 @@ Features\n - Sub-Function.\n - Matching on represented port.\n - Matching on aggregated affinity.\n-\n+- Matching on random value.\n \n Limitations\n -----------\n@@ -564,6 +564,7 @@ Limitations\n - Modification of the MPLS header is supported only in HWS and only to copy from,\n the encapsulation level is always 0.\n - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported.\n+ - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported.\n - Encapsulation levels are not supported, can modify outermost header fields only.\n - Offsets cannot skip past the boundary of a field.\n - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE``\n@@ -770,6 +771,13 @@ Limitations\n - In HW steering (``dv_flow_en`` = 2):\n - not supported on guest port.\n \n+- Match on random value:\n+\n+ - Supported only with HW Steering enabled (``dv_flow_en`` = 2).\n+ - Supported only in table with ``nb_flows=1``.\n+ - NIC ingress flow in group 0 is not supported.\n+ - Supports matching only 16 bits (LSB).\n+\n - During live migration to a new process set its flow engine as standby mode,\n the user should only program flow rules in group 0 (``fdb_def_rule_en=0``).\n Live migration is only supported under SWS (``dv_flow_en=1``).\ndiff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex ab91ce2b21..164cf74f5b 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -59,6 +59,9 @@ New Features\n \n Added ``RTE_FLOW_ITEM_RANDOM`` to match random value.\n \n+* **Updated NVIDIA mlx5 net driver.**\n+\n+ * Added support for ``RTE_FLOW_ITEM_TYPE_RUNDOM`` flow item.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 115d730317..67a44095d7 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -5396,6 +5396,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifications of the MPLS header \"\n \t\t\t\t\"is not supported\");\n+\tif (dst_data->field == RTE_FLOW_FIELD_RANDOM ||\n+\t src_data->field == RTE_FLOW_FIELD_RANDOM)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"modifications of random value is not supported\");\n \tif (dst_data->field == RTE_FLOW_FIELD_MARK ||\n \t src_data->field == RTE_FLOW_FIELD_MARK)\n \t\tif (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex da873ae2e2..af4e9abd89 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -5047,6 +5047,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev,\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n \t\t\t\t\"modifying vlan_type is not supported\");\n+\tif (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM))\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n+\t\t\t\t\"modifying random value is not supported\");\n \tif (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI))\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\tRTE_FLOW_ERROR_TYPE_ACTION, action,\n@@ -6807,6 +6811,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_FLEX:\n \t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n \t\tcase RTE_FLOW_ITEM_TYPE_PTYPE:\n+\t\tcase RTE_FLOW_ITEM_TYPE_RANDOM:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\t/*\n", "prefixes": [ "v2", "2/2" ] }