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GET /api/patches/134366/?format=api
{ "id": 134366, "url": "https://patches.dpdk.org/api/patches/134366/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231114173609.3590237-1-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231114173609.3590237-1-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231114173609.3590237-1-abdullah.sevincer@intel.com", "date": "2023-11-14T17:36:09", "name": "[v2] bus/pci: revise support PASID control", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "097e2f50ff51c3a0e8f6dfe4a49a2d89b32cfdb2", "submitter": { "id": 2843, "url": "https://patches.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231114173609.3590237-1-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 30295, "url": "https://patches.dpdk.org/api/series/30295/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30295", "date": "2023-11-14T17:36:09", "name": "[v2] bus/pci: revise support PASID control", "version": 2, "mbox": "https://patches.dpdk.org/series/30295/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/134366/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/134366/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 88CEB4332D;\n\tTue, 14 Nov 2023 18:36:15 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 730D44028A;\n\tTue, 14 Nov 2023 18:36:15 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id E2CEF4027B\n for <dev@dpdk.org>; Tue, 14 Nov 2023 18:36:13 +0100 (CET)", "from orviesa001.jf.intel.com ([10.64.159.141])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Nov 2023 09:36:12 -0800", "from txanpdk02.an.intel.com ([10.123.117.76])\n by orviesa001.jf.intel.com with ESMTP; 14 Nov 2023 09:36:12 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1699983374; x=1731519374;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=wExmIDeH97IZ2kmn/5JnjIh2Hyac/jAA4U8Kyc4wFGM=;\n b=mt4eAvjlwskAu4OlPJrGYcmsHiGRQPhMcPINdH+v8vDBloDWY8EGbKX6\n x1+SDmP+lea5aEZH+udac1apgLTwh4LR1AlDnbtpG7315K9FXiw0oZuu9\n S/o+RPhopf2hgeoogcJvE4h960zQYgx/suCsPQlbqfolKDcmCjfBE3/xD\n 0zMnEEcBkVj/tZxv7NMeaSO5DJan5CiQDccNKOdNquMkKQ6WjRoAMYAqz\n e2T4Q1AfBvElGteKoCXwGkiSsYwbkb8ZNN1WxVPuLaaW0mLP2w3gwMfma\n 9mJcE9+RYuBPWqldrx6tBUf52k4CDMGf+Q9kANblRAfdq8SFwJ1INb8os A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10894\"; a=\"457200214\"", "E=Sophos;i=\"6.03,302,1694761200\"; d=\"scan'208\";a=\"457200214\"", "E=Sophos;i=\"6.03,302,1694761200\"; d=\"scan'208\";a=\"12496725\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, mike.ximing.chen@intel.com,\n bruce.richardson@intel.com,\n thomas@monjalon.net, david.marchand@redhat.com, nipun.gupta@amd.com,\n chenbox@nvidia.com, Abdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v2] bus/pci: revise support PASID control", "Date": "Tue, 14 Nov 2023 11:36:09 -0600", "Message-Id": "<20231114173609.3590237-1-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20231113172759.3529518-1-abdullah.sevincer@intel.com>", "References": "<20231113172759.3529518-1-abdullah.sevincer@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit revises PASID control function to accept PASID offset to\npasid *structure* instead of taking exact register for controlling the\nfeature.\n\nPASID control function was introduced in earlier commit.\nPlease see commit 5a6878335b81 (\"event/dlb2: disable PASID\") and\ncommit 60ea19609aec (\"bus/pci: add PASID control\").\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n drivers/bus/pci/pci_common.c | 5 ++---\n drivers/bus/pci/rte_bus_pci.h | 5 ++++-\n drivers/event/dlb2/pf/dlb2_main.c | 4 ++--\n lib/pci/rte_pci.h | 2 +-\n 4 files changed, 9 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c\nindex ba5e280d33..889a48d2af 100644\n--- a/drivers/bus/pci/pci_common.c\n+++ b/drivers/bus/pci/pci_common.c\n@@ -943,9 +943,8 @@ rte_pci_pasid_set_state(const struct rte_pci_device *dev,\n \t\toff_t offset, bool enable)\n {\n \tuint16_t pasid = enable;\n-\treturn rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0\n-\t\t? -1\n-\t\t: 0;\n+\treturn rte_pci_write_config(dev, &pasid, sizeof(pasid),\n+\t\t\toffset + RTE_PCI_PASID_CTRL) != sizeof(pasid) ? -1 : 0;\n }\n \n struct rte_pci_bus rte_pci_bus = {\ndiff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h\nindex f07bf9b588..35d07d8294 100644\n--- a/drivers/bus/pci/rte_bus_pci.h\n+++ b/drivers/bus/pci/rte_bus_pci.h\n@@ -161,9 +161,12 @@ int rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable);\n * @param dev\n * A pointer to a rte_pci_device structure.\n * @param offset\n- * Offset of the PASID external capability.\n+ * Offset of the PASID external capability structure.\n * @param enable\n * Flag to enable or disable PASID.\n+ *\n+ * @return\n+ * 0 on success, -1 on error in PCI config space read/write.\n */\n __rte_internal\n int rte_pci_pasid_set_state(const struct rte_pci_device *dev,\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex 61a7b39eef..a95d3227a4 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -518,8 +518,8 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)\n \t/* Disable PASID if it is enabled by default, which\n \t * breaks the DLB if enabled.\n \t */\n-\toff = DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL;\n-\tif (rte_pci_pasid_set_state(pdev, off, false)) {\n+\toff = DLB2_PCI_PASID_CAP_OFFSET;\n+\tif (rte_pci_pasid_set_state(pdev, off, false) < 0) {\n \t\tDLB2_LOG_ERR(\"[%s()] failed to write the pcie config space at offset %d\\n\",\n \t\t\t\t__func__, (int)off);\n \t\treturn -1;\ndiff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h\nindex 0d2d8d8fed..c26fc77209 100644\n--- a/lib/pci/rte_pci.h\n+++ b/lib/pci/rte_pci.h\n@@ -101,7 +101,7 @@ extern \"C\" {\n #define RTE_PCI_EXT_CAP_ID_ACS\t\t0x0d\t/* Access Control Services */\n #define RTE_PCI_EXT_CAP_ID_SRIOV\t0x10\t/* SR-IOV */\n #define RTE_PCI_EXT_CAP_ID_PRI\t\t0x13\t/* Page Request Interface */\n-#define RTE_PCI_EXT_CAP_ID_PASID\t0x1B /* Process Address Space ID */\n+#define RTE_PCI_EXT_CAP_ID_PASID\t0x1b /* Process Address Space ID */\n \n /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */\n #define RTE_PCI_ERR_UNCOR_STATUS\t0x04\t/* Uncorrectable Error Status */\n", "prefixes": [ "v2" ] }