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GET /api/patches/134121/?format=api
{ "id": 134121, "url": "https://patches.dpdk.org/api/patches/134121/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1db44f7d6e4b0e01329ba7a259cfa800712f143a.1699850231.git.gmuthukrishn@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1db44f7d6e4b0e01329ba7a259cfa800712f143a.1699850231.git.gmuthukrishn@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1db44f7d6e4b0e01329ba7a259cfa800712f143a.1699850231.git.gmuthukrishn@marvell.com", "date": "2023-11-13T04:41:02", "name": "[v6,2/4] app/dma-perf: add PCI device support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f8507087fd6969443dc9da16399df2d9a1b66d85", "submitter": { "id": 2301, "url": "https://patches.dpdk.org/api/people/2301/?format=api", "name": "Gowrishankar Muthukrishnan", "email": "gmuthukrishn@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1db44f7d6e4b0e01329ba7a259cfa800712f143a.1699850231.git.gmuthukrishn@marvell.com/mbox/", "series": [ { "id": 30255, "url": "https://patches.dpdk.org/api/series/30255/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30255", "date": "2023-11-13T04:41:00", "name": "PCI Dev and SG copy support", "version": 6, "mbox": "https://patches.dpdk.org/series/30255/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/134121/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/134121/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0775043315;\n\tMon, 13 Nov 2023 05:41:28 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 79562402D8;\n\tMon, 13 Nov 2023 05:41:23 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 0F49D402D6\n for <dev@dpdk.org>; Mon, 13 Nov 2023 05:41:21 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 3AD3oKuj007710; Sun, 12 Nov 2023 20:41:21 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3uaa0qusbt-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sun, 12 Nov 2023 20:41:21 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Sun, 12 Nov 2023 20:41:19 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Sun, 12 Nov 2023 20:41:19 -0800", "from BG-LT91401.marvell.com (BG-LT91401.marvell.com [10.28.168.34])\n by maili.marvell.com (Postfix) with ESMTP id 73A2B3F7073;\n Sun, 12 Nov 2023 20:41:16 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=5I0eYu6gz5WcS8Yz053JeTDkcYqYj/W/FhjWaxMoSFM=;\n b=aPAK+fR8h442qw36wJbfeX35+hpTEg/crcsEAhYImVngvg/88uTFbYk1yRc/UykuyBd8\n 6ZvEPZJf90Qld/cdyI57u1MQDYomhhgTsLOVSW7ua5X6JM5Gf56nh7EkTbsu2ISnjtWh\n 4a4nTuytgLEbCB8VWEnNLTBeOVJJ+bqL6dZB8f8Py9yPCYjA1X/Vgc4HG+D5Y7BJ58xj\n 1eJQbL3wkY0FlRls+jUxSTV6PAGHYKVf10n5MkwZ+IG06ihKkxoADrNHe7KVPBqucVJJ\n perIsP81JDd2uqMjteE/YwAW9LtGlkWVfU9YLkSukzSukwlnRwWObpYGuseJo9YBY1Lb Aw==", "From": "Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<anoobj@marvell.com>, Cheng Jiang <honest.jiang@foxmail.com>, Kevin Laatz\n <kevin.laatz@intel.com>, Bruce Richardson <bruce.richardson@intel.com>,\n \"Pavan Nikhilesh\" <pbhagavatula@marvell.com>, Amit Prakash Shukla\n <amitprakashs@marvell.com>", "Subject": "[PATCH v6 2/4] app/dma-perf: add PCI device support", "Date": "Mon, 13 Nov 2023 10:11:02 +0530", "Message-ID": "\n <1db44f7d6e4b0e01329ba7a259cfa800712f143a.1699850231.git.gmuthukrishn@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<cover.1699850231.git.gmuthukrishn@marvell.com>", "References": "<cover.1699850231.git.gmuthukrishn@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "_YPfswru6AOlicmt7IB--TDLBicKYbrT", "X-Proofpoint-GUID": "_YPfswru6AOlicmt7IB--TDLBicKYbrT", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-11-12_24,2023-11-09_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Amit Prakash Shukla <amitprakashs@marvell.com>\n\nAdd support to test performance for \"device to memory\" and\n\"memory to device\" data transfer.\n\nSigned-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>\nAcked-by: Anoob Joseph <anoobj@marvell.com>\n---\nv6:\n - fix mbuf IOVA with remote address\n---\n---\n app/test-dma-perf/benchmark.c | 108 +++++++++++++++++++++++++++++++---\n app/test-dma-perf/config.ini | 37 ++++++++++++\n app/test-dma-perf/main.c | 67 +++++++++++++++++++++\n app/test-dma-perf/main.h | 6 ++\n 4 files changed, 209 insertions(+), 9 deletions(-)", "diff": "diff --git a/app/test-dma-perf/benchmark.c b/app/test-dma-perf/benchmark.c\nindex 0601e0d171..501e21981f 100644\n--- a/app/test-dma-perf/benchmark.c\n+++ b/app/test-dma-perf/benchmark.c\n@@ -127,17 +127,54 @@ cache_flush_buf(__rte_unused struct rte_mbuf **array,\n #endif\n }\n \n+static int\n+vchan_data_populate(uint32_t dev_id, struct rte_dma_vchan_conf *qconf,\n+\t\t struct test_configure *cfg)\n+{\n+\tstruct rte_dma_info info;\n+\n+\tqconf->direction = cfg->transfer_dir;\n+\n+\trte_dma_info_get(dev_id, &info);\n+\tif (!(RTE_BIT64(qconf->direction) & info.dev_capa))\n+\t\treturn -1;\n+\n+\tqconf->nb_desc = cfg->ring_size.cur;\n+\n+\tswitch (qconf->direction) {\n+\tcase RTE_DMA_DIR_MEM_TO_DEV:\n+\t\tqconf->dst_port.pcie.vfen = 1;\n+\t\tqconf->dst_port.port_type = RTE_DMA_PORT_PCIE;\n+\t\tqconf->dst_port.pcie.coreid = cfg->dcoreid;\n+\t\tqconf->dst_port.pcie.vfid = cfg->vfid;\n+\t\tqconf->dst_port.pcie.pfid = cfg->pfid;\n+\t\tbreak;\n+\tcase RTE_DMA_DIR_DEV_TO_MEM:\n+\t\tqconf->src_port.pcie.vfen = 1;\n+\t\tqconf->src_port.port_type = RTE_DMA_PORT_PCIE;\n+\t\tqconf->src_port.pcie.coreid = cfg->scoreid;\n+\t\tqconf->src_port.pcie.vfid = cfg->vfid;\n+\t\tqconf->src_port.pcie.pfid = cfg->pfid;\n+\t\tbreak;\n+\tcase RTE_DMA_DIR_MEM_TO_MEM:\n+\tcase RTE_DMA_DIR_DEV_TO_DEV:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Configuration of device. */\n static void\n-configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size)\n+configure_dmadev_queue(uint32_t dev_id, struct test_configure *cfg)\n {\n \tuint16_t vchan = 0;\n \tstruct rte_dma_info info;\n \tstruct rte_dma_conf dev_config = { .nb_vchans = 1 };\n-\tstruct rte_dma_vchan_conf qconf = {\n-\t\t.direction = RTE_DMA_DIR_MEM_TO_MEM,\n-\t\t.nb_desc = ring_size\n-\t};\n+\tstruct rte_dma_vchan_conf qconf = { 0 };\n+\n+\tif (vchan_data_populate(dev_id, &qconf, cfg) != 0)\n+\t\trte_exit(EXIT_FAILURE, \"Error with vchan data populate.\\n\");\n \n \tif (rte_dma_configure(dev_id, &dev_config) != 0)\n \t\trte_exit(EXIT_FAILURE, \"Error with dma configure.\\n\");\n@@ -159,7 +196,6 @@ configure_dmadev_queue(uint32_t dev_id, uint32_t ring_size)\n static int\n config_dmadevs(struct test_configure *cfg)\n {\n-\tuint32_t ring_size = cfg->ring_size.cur;\n \tstruct lcore_dma_map_t *ldm = &cfg->lcore_dma_map;\n \tuint32_t nb_workers = ldm->cnt;\n \tuint32_t i;\n@@ -176,7 +212,7 @@ config_dmadevs(struct test_configure *cfg)\n \t\t}\n \n \t\tldm->dma_ids[i] = dev_id;\n-\t\tconfigure_dmadev_queue(dev_id, ring_size);\n+\t\tconfigure_dmadev_queue(dev_id, cfg);\n \t\t++nb_dmadevs;\n \t}\n \n@@ -301,13 +337,22 @@ do_cpu_mem_copy(void *p)\n \treturn 0;\n }\n \n+static void\n+dummy_free_ext_buf(void *addr, void *opaque)\n+{\n+\tRTE_SET_USED(addr);\n+\tRTE_SET_USED(opaque);\n+}\n+\n static int\n setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\t\tstruct rte_mbuf ***dsts)\n {\n+\tstatic struct rte_mbuf_ext_shared_info *ext_buf_info;\n \tunsigned int buf_size = cfg->buf_size.cur;\n \tunsigned int nr_sockets;\n \tuint32_t nr_buf = cfg->nr_buf;\n+\tuint32_t i;\n \n \tnr_sockets = rte_socket_count();\n \tif (cfg->src_numa_node >= nr_sockets ||\n@@ -360,16 +405,47 @@ setup_memory_env(struct test_configure *cfg, struct rte_mbuf ***srcs,\n \t\treturn -1;\n \t}\n \n+\tif (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM ||\n+\t cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV) {\n+\t\text_buf_info = rte_malloc(NULL, sizeof(struct rte_mbuf_ext_shared_info), 0);\n+\t\tif (ext_buf_info == NULL) {\n+\t\t\tprintf(\"Error: ext_buf_info malloc failed.\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tif (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) {\n+\t\text_buf_info->free_cb = dummy_free_ext_buf;\n+\t\text_buf_info->fcb_opaque = NULL;\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\t/* Using mbuf structure to hold remote iova address. */\n+\t\t\trte_pktmbuf_attach_extbuf((*srcs)[i], (void *)cfg->raddr,\n+\t\t\t\t\t\t (rte_iova_t)cfg->raddr, 0, ext_buf_info);\n+\t\t\trte_mbuf_ext_refcnt_update(ext_buf_info, 1);\n+\t\t}\n+\t}\n+\n+\tif (cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV) {\n+\t\text_buf_info->free_cb = dummy_free_ext_buf;\n+\t\text_buf_info->fcb_opaque = NULL;\n+\t\tfor (i = 0; i < nr_buf; i++) {\n+\t\t\t/* Using mbuf structure to hold remote iova address. */\n+\t\t\trte_pktmbuf_attach_extbuf((*dsts)[i], (void *)cfg->raddr,\n+\t\t\t\t\t\t (rte_iova_t)cfg->raddr, 0, ext_buf_info);\n+\t\t\trte_mbuf_ext_refcnt_update(ext_buf_info, 1);\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n void\n mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n {\n-\tuint16_t i;\n+\tuint32_t i;\n \tuint32_t offset;\n \tunsigned int lcore_id = 0;\n-\tstruct rte_mbuf **srcs = NULL, **dsts = NULL;\n+\tstruct rte_mbuf **srcs = NULL, **dsts = NULL, **m = NULL;\n \tstruct lcore_dma_map_t *ldm = &cfg->lcore_dma_map;\n \tunsigned int buf_size = cfg->buf_size.cur;\n \tuint16_t kick_batch = cfg->kick_batch.cur;\n@@ -475,6 +551,20 @@ mem_copy_benchmark(struct test_configure *cfg, bool is_dma)\n \t\t\tavg_cycles_total / nb_workers, bandwidth_total, mops_total);\n \n out:\n+\n+\tif (cfg->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM)\n+\t\tm = srcs;\n+\telse if (cfg->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV)\n+\t\tm = dsts;\n+\n+\tif (m) {\n+\t\tfor (i = 0; i < nr_buf; i++)\n+\t\t\trte_pktmbuf_detach_extbuf(m[i]);\n+\n+\t\tif (m[0]->shinfo && rte_mbuf_ext_refcnt_read(m[0]->shinfo) == 0)\n+\t\t\trte_free(m[0]->shinfo);\n+\t}\n+\n \t/* free mbufs used in the test */\n \tif (srcs != NULL)\n \t\trte_pktmbuf_free_bulk(srcs, nr_buf);\ndiff --git a/app/test-dma-perf/config.ini b/app/test-dma-perf/config.ini\nindex 4d59234b2a..cddcf93c6e 100644\n--- a/app/test-dma-perf/config.ini\n+++ b/app/test-dma-perf/config.ini\n@@ -38,6 +38,23 @@\n \n ; \"skip\" To skip a test-case set skip to 1.\n \n+; Parameters to be configured for data transfers from \"mem to dev\" and \"dev to mem\":\n+; ==================================================================================\n+; \"direction\" denotes the direction of data transfer. It can take 3 values:\n+; 0 - mem to mem transfer\n+; 1 - mem to dev transfer\n+; 2 - dev to mem transfer\n+; If not specified the default value is 0 (mem to mem transfer).\n+\n+; \"raddr\" remote iova address for \"mem to dev\" and \"dev to mem\" transfer.\n+\n+; \"scoreid\" denotes source PCIe core index.\n+; \"dcoreid\" denotes destination PCIe core index.\n+; \"pfid\" denotes PF-id to be used for data transfer\n+; \"vfid\" denotes VF-id of PF-id to be used for data transfer.\n+\n+; =========== End of \"mem to dev\" and \"dev to mem\" config parameters. ==============\n+\n [case1]\n type=DMA_MEM_COPY\n mem_size=10\n@@ -52,6 +69,26 @@ lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n eal_args=--in-memory --file-prefix=test\n \n [case2]\n+skip=1\n+type=DMA_MEM_COPY\n+direction=2\n+raddr=0x200000000\n+scoreid=0\n+dcoreid=0\n+pfid=0\n+vfid=0\n+mem_size=10\n+buf_size=64,4096,2,MUL\n+dma_ring_size=1024\n+kick_batch=32\n+src_numa_node=0\n+dst_numa_node=0\n+cache_flush=0\n+test_seconds=2\n+lcore_dma=lcore10@0000:00:04.2, lcore11@0000:00:04.3\n+eal_args=--in-memory --file-prefix=test\n+\n+[case3]\n type=CPU_MEM_COPY\n mem_size=10\n buf_size=64,8192,2,MUL\ndiff --git a/app/test-dma-perf/main.c b/app/test-dma-perf/main.c\nindex 61260fa072..9640356592 100644\n--- a/app/test-dma-perf/main.c\n+++ b/app/test-dma-perf/main.c\n@@ -16,6 +16,7 @@\n #include <rte_cfgfile.h>\n #include <rte_string_fns.h>\n #include <rte_lcore.h>\n+#include <rte_dmadev.h>\n \n #include \"main.h\"\n \n@@ -318,9 +319,11 @@ load_configs(const char *path)\n \tstruct test_configure *test_case;\n \tchar section_name[CFG_NAME_LEN];\n \tconst char *case_type;\n+\tconst char *transfer_dir;\n \tconst char *lcore_dma;\n \tconst char *mem_size_str, *buf_size_str, *ring_size_str, *kick_batch_str;\n \tconst char *skip;\n+\tconst char *raddr, *scoreid, *dcoreid, *vfid, *pfid;\n \tint args_nr, nb_vp;\n \tbool is_dma;\n \n@@ -358,6 +361,20 @@ load_configs(const char *path)\n \t\tif (strcmp(case_type, DMA_MEM_COPY) == 0) {\n \t\t\ttest_case->test_type = TEST_TYPE_DMA_MEM_COPY;\n \t\t\ttest_case->test_type_str = DMA_MEM_COPY;\n+\n+\t\t\ttransfer_dir = rte_cfgfile_get_entry(cfgfile, section_name, \"direction\");\n+\t\t\tif (transfer_dir == NULL) {\n+\t\t\t\tprintf(\"Transfer direction not configured.\"\n+\t\t\t\t\t\" Defaulting it to MEM to MEM transfer.\\n\");\n+\t\t\t\ttest_case->transfer_dir = RTE_DMA_DIR_MEM_TO_MEM;\n+\t\t\t} else\n+\t\t\t\ttest_case->transfer_dir = (uint8_t)atoi(transfer_dir);\n+\n+\t\t\tif (test_case->transfer_dir >= RTE_DMA_DIR_DEV_TO_DEV) {\n+\t\t\t\tprintf(\"Error: Invalid transfer direction configured.\\n\");\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n \t\t\tis_dma = true;\n \t\t} else if (strcmp(case_type, CPU_MEM_COPY) == 0) {\n \t\t\ttest_case->test_type = TEST_TYPE_CPU_MEM_COPY;\n@@ -369,6 +386,56 @@ load_configs(const char *path)\n \t\t\tcontinue;\n \t\t}\n \n+\t\tif (test_case->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV ||\n+\t\t\ttest_case->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) {\n+\t\t\tchar *endptr;\n+\n+\t\t\traddr = rte_cfgfile_get_entry(cfgfile, section_name, \"raddr\");\n+\t\t\tif (raddr == NULL) {\n+\t\t\t\tprintf(\"Error: No raddr configured for case%d.\\n\", i + 1);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\ttest_case->raddr = strtoull(raddr, &endptr, 16);\n+\n+\t\t\tvfid = rte_cfgfile_get_entry(cfgfile, section_name, \"vfid\");\n+\t\t\tif (vfid == NULL) {\n+\t\t\t\tprintf(\"Error: No vfid configured for case%d.\\n\", i + 1);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\ttest_case->vfid = (uint16_t)atoi(vfid);\n+\n+\t\t\tpfid = rte_cfgfile_get_entry(cfgfile, section_name, \"pfid\");\n+\t\t\tif (pfid == NULL) {\n+\t\t\t\tprintf(\"Error: No pfid configured for case%d.\\n\", i + 1);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\ttest_case->pfid = (uint8_t)atoi(pfid);\n+\n+\t\t}\n+\n+\t\tif (test_case->transfer_dir == RTE_DMA_DIR_DEV_TO_MEM) {\n+\t\t\tscoreid = rte_cfgfile_get_entry(cfgfile, section_name, \"scoreid\");\n+\t\t\tif (scoreid == NULL) {\n+\t\t\t\tprintf(\"Error: No scoreid configured for case%d.\\n\", i + 1);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\ttest_case->scoreid = (uint8_t)atoi(scoreid);\n+\t\t}\n+\n+\t\tif (test_case->transfer_dir == RTE_DMA_DIR_MEM_TO_DEV) {\n+\t\t\tdcoreid = rte_cfgfile_get_entry(cfgfile, section_name, \"dcoreid\");\n+\t\t\tif (dcoreid == NULL) {\n+\t\t\t\tprintf(\"Error: No dcoreid configured for case%d.\\n\", i + 1);\n+\t\t\t\ttest_case->is_valid = false;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\ttest_case->dcoreid = (uint8_t)atoi(dcoreid);\n+\t\t}\n+\n \t\ttest_case->src_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\n \t\t\t\t\t\t\t\tsection_name, \"src_numa_node\"));\n \t\ttest_case->dst_numa_node = (int)atoi(rte_cfgfile_get_entry(cfgfile,\ndiff --git a/app/test-dma-perf/main.h b/app/test-dma-perf/main.h\nindex be89cb2b65..617f62f085 100644\n--- a/app/test-dma-perf/main.h\n+++ b/app/test-dma-perf/main.h\n@@ -43,6 +43,7 @@ struct test_configure {\n \tbool is_valid;\n \tbool is_skip;\n \tuint8_t test_type;\n+\tuint8_t transfer_dir;\n \tconst char *test_type_str;\n \tuint16_t src_numa_node;\n \tuint16_t dst_numa_node;\n@@ -58,6 +59,11 @@ struct test_configure {\n \tuint16_t test_secs;\n \tconst char *eal_args;\n \tuint8_t scenario_id;\n+\tuint8_t scoreid;\n+\tuint8_t dcoreid;\n+\tuint8_t pfid;\n+\tuint16_t vfid;\n+\tuint64_t raddr;\n };\n \n void mem_copy_benchmark(struct test_configure *cfg, bool is_dma);\n", "prefixes": [ "v6", "2/4" ] }