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GET /api/patches/133655/?format=api
{ "id": 133655, "url": "https://patches.dpdk.org/api/patches/133655/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231031122512.434686-6-getelson@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231031122512.434686-6-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231031122512.434686-6-getelson@nvidia.com", "date": "2023-10-31T12:25:07", "name": "[05/10] net/mlx5/hws: support ASO first hit action", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": true, "hash": "ef8b3487d3d732ab3945e39133d1341ac7d5a7a6", "submitter": { "id": 1882, "url": "https://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231031122512.434686-6-getelson@nvidia.com/mbox/", "series": [ { "id": 30072, "url": "https://patches.dpdk.org/api/series/30072/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=30072", "date": "2023-10-31T12:25:02", "name": "net/mlx5/hws: IPSEC reparse submission", "version": 1, "mbox": "https://patches.dpdk.org/series/30072/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/133655/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/133655/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 507FB43252;\n\tTue, 31 Oct 2023 13:26:23 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DC9B940EDF;\n\tTue, 31 Oct 2023 13:26:09 +0100 (CET)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2046.outbound.protection.outlook.com [40.107.94.46])\n by mails.dpdk.org (Postfix) with ESMTP id DB58640E25\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>,\n \"Hamdan Igbaria\" <hamdani@nvidia.com>, Alex Vesker <valex@nvidia.com>, Matan\n Azrad <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori\n Kam <orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH 05/10] net/mlx5/hws: support ASO first hit action", "Date": "Tue, 31 Oct 2023 14:25:07 +0200", "Message-ID": "<20231031122512.434686-6-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231031122512.434686-1-getelson@nvidia.com>", "References": "<20231031122512.434686-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MN1PEPF0000ECDA:EE_|DS7PR12MB6095:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1dc81f5d-054d-44e2-eb2d-08dbda0c8d77", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jEBJBVTJxepV8iEGMNu5Cn4+d7N5Ud2wqNl9UKXm3xRJkZ8Dz4EETD9hmQuwqbiC0zFBsxuTVCpYECi/fudt7rvhkBOLCly9J1jIHBAjNKnpl27OCzxzCqsCvSD+kesKspDRJxC5FJXrN9aDA70gtWlz0UEb+5zDRqDlyMmaxm03PwnyF9puto0TuxAEEHvtrKD5DrE1w7fszUxtXyIisJdTYwEQ4xDrMV+jzMyVw1TNt2svh5AWnQ1n+QEZsPP5nQTPfXv4FF81exmM6ElozZxDG4/NX58+QfaabX0AzrctTotOwaYfHn2//l/we7bGQAPTMpNWaCtnfyqRBFNwsiQB8wgAaOJ16OMODBrxC521StKRjeAH/BUbGhpYTsWLnNgMquWTFiNnlY/P7Zzjqrv/kr6ivc8fRajxQys2nHazGTOQ38ueX/CzZ3gjh6XPNnLco8B5xdToGuZWzDJN8Lom3cLmSGyf3C46pitUYXUgl7i+1Pu94cFLSnHakxLwg6qWUdubD/eF0116LkGrdEFR2tzrqUIFUE8OdKZQKAveZI9+5nZHImrP+LTe7MCjMWkLHZyH/S+ayoyDTk7qqhrmXOmAm0lB0rrwMaL+B5vE7vdkJhK0rCXMR5/8G60uHcYSnUUCQUfipTPmV7fpB2jTxbamFpgmXcTnFBfow2l1R9yf84A0tqo/JBJuY0NLSoQDTXqF7cDQ3Ep1X0fnpph2edbzoaeEox/yE2OgakPhAih4Ih3iUZxtUae1zOHZ", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MN1PEPF0000ECDA.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB6095", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hamdan Igbaria <hamdani@nvidia.com>\n\nSupport ASO first hit action.\nThis action allows tracking if a rule gets hit by a packet.\n\nSigned-off-by: Hamdan Igbaria <hamdani@nvidia.com>\nReviewed-by: Alex Vesker <valex@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 5 +++++\n drivers/net/mlx5/hws/mlx5dr.h | 25 +++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_action.c | 33 ++++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_debug.c | 1 +\n 4 files changed, 64 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 793fc1a674..40e461cb82 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3541,6 +3541,7 @@ enum {\n \tMLX5_ASO_CT_NUM_PER_OBJ = 1,\n \tMLX5_ASO_METER_NUM_PER_OBJ = 2,\n \tMLX5_ASO_IPSEC_NUM_PER_OBJ = 1,\n+\tMLX5_ASO_FIRST_HIT_NUM_PER_OBJ = 512,\n };\n \n struct mlx5_ifc_stc_ste_param_execute_aso_bits {\n@@ -5371,6 +5372,10 @@ enum {\n \tMLX5_FLOW_COLOR_UNDEFINED,\n };\n \n+enum {\n+\tMLX5_ASO_FIRST_HIT_SET = 1,\n+};\n+\n /* Maximum value of srTCM & trTCM metering parameters. */\n #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))\n #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)\ndiff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h\nindex e425a8803a..e7d89ad7ec 100644\n--- a/drivers/net/mlx5/hws/mlx5dr.h\n+++ b/drivers/net/mlx5/hws/mlx5dr.h\n@@ -47,6 +47,7 @@ enum mlx5dr_action_type {\n \tMLX5DR_ACTION_TYP_ASO_METER,\n \tMLX5DR_ACTION_TYP_ASO_CT,\n \tMLX5DR_ACTION_TYP_ASO_IPSEC,\n+\tMLX5DR_ACTION_TYP_ASO_FIRST_HIT,\n \tMLX5DR_ACTION_TYP_CRYPTO_ENCRYPT,\n \tMLX5DR_ACTION_TYP_CRYPTO_DECRYPT,\n \tMLX5DR_ACTION_TYP_DEST_ROOT,\n@@ -256,6 +257,11 @@ struct mlx5dr_rule_action {\n \t\t\tuint32_t offset;\n \t\t} aso_ipsec;\n \n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tbool set;\n+\t\t} aso_first_hit;\n+\n \t\tstruct {\n \t\t\tuint32_t offset;\n \t\t} crypto;\n@@ -714,6 +720,25 @@ mlx5dr_action_create_aso_ipsec(struct mlx5dr_context *ctx,\n \t\t\t uint8_t return_reg_id,\n \t\t\t uint32_t flags);\n \n+/* Create direct rule ASO FIRST HIT action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] devx_obj\n+ *\tThe DEVX ASO object.\n+ * @param[in] return_reg_id\n+ *\tWhen a packet hits a flow connected to this object, a flag is set indicating this event,\n+ *\tcopy the original value of this flag into this reg_id.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_aso_first_hit(struct mlx5dr_context *ctx,\n+\t\t\t\t struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t\t uint8_t return_reg_id,\n+\t\t\t\t uint32_t flags);\n+\n /* Create direct rule pop vlan action.\n * @param[in] ctx\n *\tThe context in which the new action will be created.\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c\nindex f8de3d8d98..fe9c39b207 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_action.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_action.c\n@@ -7,6 +7,7 @@\n #define WIRE_PORT 0xFFFF\n \n #define MLX5DR_ACTION_METER_INIT_COLOR_OFFSET 1\n+#define MLX5DR_ACTION_ASO_FIRST_HIT_SET_OFFSET 9\n \n /* This is the maximum allowed action order for each table type:\n *\t TX: POP_VLAN, CTR, ASO, PUSH_VLAN, MODIFY, ENCAP, TRAILER, ENCRYPT,\n@@ -29,6 +30,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_METER),\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_CT),\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_IPSEC),\n+\t\tBIT(MLX5DR_ACTION_TYP_ASO_FIRST_HIT),\n \t\tBIT(MLX5DR_ACTION_TYP_PUSH_VLAN),\n \t\tBIT(MLX5DR_ACTION_TYP_PUSH_VLAN),\n \t\tBIT(MLX5DR_ACTION_TYP_MODIFY_HDR),\n@@ -49,6 +51,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_METER),\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_CT),\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_IPSEC),\n+\t\tBIT(MLX5DR_ACTION_TYP_ASO_FIRST_HIT),\n \t\tBIT(MLX5DR_ACTION_TYP_PUSH_VLAN),\n \t\tBIT(MLX5DR_ACTION_TYP_PUSH_VLAN),\n \t\tBIT(MLX5DR_ACTION_TYP_MODIFY_HDR),\n@@ -73,6 +76,7 @@ static const uint32_t action_order_arr[MLX5DR_TABLE_TYPE_MAX][MLX5DR_ACTION_TYP_\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_METER),\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_CT),\n \t\tBIT(MLX5DR_ACTION_TYP_ASO_IPSEC),\n+\t\tBIT(MLX5DR_ACTION_TYP_ASO_FIRST_HIT),\n \t\tBIT(MLX5DR_ACTION_TYP_PUSH_VLAN),\n \t\tBIT(MLX5DR_ACTION_TYP_PUSH_VLAN),\n \t\tBIT(MLX5DR_ACTION_TYP_MODIFY_HDR),\n@@ -672,6 +676,13 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action,\n \t\tattr->aso.devx_obj_id = obj->id;\n \t\tattr->aso.return_reg_id = action->aso.return_reg_id;\n \t\tbreak;\n+\tcase MLX5DR_ACTION_TYP_ASO_FIRST_HIT:\n+\t\tattr->action_offset = MLX5DR_ACTION_OFFSET_DW6;\n+\t\tattr->action_type = MLX5_IFC_STC_ACTION_TYPE_ASO;\n+\t\tattr->aso.aso_type = ASO_OPC_MOD_FLOW_HIT;\n+\t\tattr->aso.devx_obj_id = obj->id;\n+\t\tattr->aso.return_reg_id = action->aso.return_reg_id;\n+\t\tbreak;\n \tcase MLX5DR_ACTION_TYP_VPORT:\n \t\tattr->action_offset = MLX5DR_ACTION_OFFSET_HIT;\n \t\tattr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT;\n@@ -1123,6 +1134,16 @@ mlx5dr_action_create_aso_ipsec(struct mlx5dr_context *ctx,\n \t\t\t\t\tdevx_obj, return_reg_id, flags);\n }\n \n+struct mlx5dr_action *\n+mlx5dr_action_create_aso_first_hit(struct mlx5dr_context *ctx,\n+\t\t\t\t struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t\t uint8_t return_reg_id,\n+\t\t\t\t uint32_t flags)\n+{\n+\treturn mlx5dr_action_create_aso(ctx, MLX5DR_ACTION_TYP_ASO_FIRST_HIT,\n+\t\t\t\t\tdevx_obj, return_reg_id, flags);\n+}\n+\n struct mlx5dr_action *\n mlx5dr_action_create_counter(struct mlx5dr_context *ctx,\n \t\t\t struct mlx5dr_devx_obj *obj,\n@@ -2185,6 +2206,7 @@ static void mlx5dr_action_destroy_hws(struct mlx5dr_action *action)\n \tcase MLX5DR_ACTION_TYP_ASO_METER:\n \tcase MLX5DR_ACTION_TYP_ASO_CT:\n \tcase MLX5DR_ACTION_TYP_ASO_IPSEC:\n+\tcase MLX5DR_ACTION_TYP_ASO_FIRST_HIT:\n \tcase MLX5DR_ACTION_TYP_PUSH_VLAN:\n \tcase MLX5DR_ACTION_TYP_CRYPTO_ENCRYPT:\n \tcase MLX5DR_ACTION_TYP_CRYPTO_DECRYPT:\n@@ -2601,6 +2623,15 @@ mlx5dr_action_setter_aso(struct mlx5dr_actions_apply_data *apply,\n \t\toffset = rule_action->aso_ipsec.offset / MLX5_ASO_IPSEC_NUM_PER_OBJ;\n \t\texe_aso_ctrl = 0;\n \t\tbreak;\n+\tcase MLX5DR_ACTION_TYP_ASO_FIRST_HIT:\n+\t\t/* exe_aso_ctrl FIRST HIT format:\n+\t\t * [STC only and reserved bits 22b][set 1b][offset 9b]\n+\t\t */\n+\t\toffset = rule_action->aso_first_hit.offset / MLX5_ASO_FIRST_HIT_NUM_PER_OBJ;\n+\t\texe_aso_ctrl = rule_action->aso_first_hit.offset % MLX5_ASO_FIRST_HIT_NUM_PER_OBJ;\n+\t\texe_aso_ctrl |= rule_action->aso_first_hit.set <<\n+\t\t\t\tMLX5DR_ACTION_ASO_FIRST_HIT_SET_OFFSET;\n+\t\tbreak;\n \tdefault:\n \t\tDR_LOG(ERR, \"Unsupported ASO action type: %d\", rule_action->action->type);\n \t\trte_errno = ENOTSUP;\n@@ -2803,6 +2834,8 @@ int mlx5dr_action_template_process(struct mlx5dr_action_template *at)\n \t\tcase MLX5DR_ACTION_TYP_ASO_METER:\n \t\tcase MLX5DR_ACTION_TYP_ASO_CT:\n \t\tcase MLX5DR_ACTION_TYP_ASO_IPSEC:\n+\t\tcase MLX5DR_ACTION_TYP_ASO_FIRST_HIT:\n+\t\t\t/* Double ASO action */\n \t\t\tsetter = mlx5dr_action_setter_find_first(last_setter, ASF_DOUBLE);\n \t\t\tsetter->flags |= ASF_DOUBLE;\n \t\t\tsetter->set_double = &mlx5dr_action_setter_aso;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c\nindex 976a1993e3..552dba5e63 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_debug.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_debug.c\n@@ -24,6 +24,7 @@ const char *mlx5dr_debug_action_type_str[] = {\n \t[MLX5DR_ACTION_TYP_ASO_METER] = \"ASO_METER\",\n \t[MLX5DR_ACTION_TYP_ASO_CT] = \"ASO_CT\",\n \t[MLX5DR_ACTION_TYP_ASO_IPSEC] = \"ASO_IPSEC\",\n+\t[MLX5DR_ACTION_TYP_ASO_FIRST_HIT] = \"ASO_FIRST_HIT\",\n \t[MLX5DR_ACTION_TYP_DEST_ROOT] = \"DEST_ROOT\",\n \t[MLX5DR_ACTION_TYP_DEST_ARRAY] = \"DEST_ARRAY\",\n \t[MLX5DR_ACTION_TYP_CRYPTO_ENCRYPT] = \"CRYPTO_ENCRYPT\",\n", "prefixes": [ "05/10" ] }