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GET /api/patches/132803/?format=api
{ "id": 132803, "url": "https://patches.dpdk.org/api/patches/132803/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231017185356.2606580-1-amitprakashs@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231017185356.2606580-1-amitprakashs@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231017185356.2606580-1-amitprakashs@marvell.com", "date": "2023-10-17T18:53:56", "name": "[v2] dma/cnxk: offload source buffer free", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b5151e5a8baa7525c194844ce82c216dca6b81e6", "submitter": { "id": 2699, "url": "https://patches.dpdk.org/api/people/2699/?format=api", "name": "Amit Prakash Shukla", "email": "amitprakashs@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231017185356.2606580-1-amitprakashs@marvell.com/mbox/", "series": [ { "id": 29891, "url": "https://patches.dpdk.org/api/series/29891/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29891", "date": "2023-10-17T18:53:56", "name": "[v2] dma/cnxk: offload source buffer free", "version": 2, "mbox": "https://patches.dpdk.org/series/29891/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/132803/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/132803/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BB3C04318F;\n\tTue, 17 Oct 2023 20:54:14 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AC37D40A8B;\n\tTue, 17 Oct 2023 20:54:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 0835140279\n for <dev@dpdk.org>; Tue, 17 Oct 2023 20:54:12 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 39HGHr5G027265; Tue, 17 Oct 2023 11:54:12 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3tsmj533b8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 17 Oct 2023 11:54:11 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Tue, 17 Oct 2023 11:54:09 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Tue, 17 Oct 2023 11:54:09 -0700", "from localhost.localdomain (unknown [10.28.36.157])\n by maili.marvell.com (Postfix) with ESMTP id 974585B6942;\n Tue, 17 Oct 2023 11:54:05 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ScKI4MQ3y0lwSRG5b2LfyaM0IIqdCI0K/WdcsGr9Jfk=;\n b=gma7KTxyf09Zh1n9M3lGfGHQZwif3FucS0j4sVHZC6aBAF1xN3U1yI03xbGWJZ3fcXD+\n zVJNO2lfNhwgmqxGLf9XVMfQoYCdAzBOk+sUXAnbJm4IQj9NlbmwKBV9c+BmwRoPDjNo\n e4C6pbz+49iOkT+L3kAITrKElV/kqc3nSFrR7FjQVRhT+XY4CVbORqCbCYfRIJBEH/cd\n 4AwpSVb7RgZut//DIL95f6wZvU9Zsrk9ciZFG28+AkYT2XTuwZMvpCecy052p/YYpRZQ\n yzmuftA13NbT+8bbApHzk0dmWIhVTwKtN1tku+LoL+icuwtaf66KkAzL5FigNTCPGT7T 9g==", "From": "Amit Prakash Shukla <amitprakashs@marvell.com>", "To": "Vamsi Attunuru <vattunuru@marvell.com>", "CC": "<dev@dpdk.org>, <jerinj@marvell.com>, <fengchengwen@huawei.com>,\n <kevin.laatz@intel.com>, <bruce.richardson@intel.com>,\n <conor.walsh@intel.com>, <g.singh@nxp.com>,\n <sachin.saxena@oss.nxp.com>, <hemant.agrawal@nxp.com>,\n <cheng1.jiang@intel.com>, <ndabilpuram@marvell.com>,\n <anoobj@marvell.com>, <mb@smartsharesystems.com>,\n Amit Prakash Shukla <amitprakashs@marvell.com>", "Subject": "[PATCH v2] dma/cnxk: offload source buffer free", "Date": "Wed, 18 Oct 2023 00:23:56 +0530", "Message-ID": "<20231017185356.2606580-1-amitprakashs@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230907082443.1002665-1-amitprakashs@marvell.com>", "References": "<20230907082443.1002665-1-amitprakashs@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "8vrSQuZG-bTr1t6u-i-Lr0iPQz-KQqS_", "X-Proofpoint-GUID": "8vrSQuZG-bTr1t6u-i-Lr0iPQz-KQqS_", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-17_03,2023-10-17_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added support in driver, to offload source buffer free to hardware\non completion of DMA transfer.\n\nSigned-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>\n---\nv2:\n- Patch rebased.\n\nv1:\n- Driver implementation from RFC.\n\n drivers/dma/cnxk/cnxk_dmadev.c | 48 +++++++++++++++++++++++++++----\n drivers/dma/cnxk/cnxk_dmadev_fp.c | 8 +++---\n 2 files changed, 46 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c\nindex 26680edfde..1e7f49792c 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev.c\n@@ -16,7 +16,8 @@ cnxk_dmadev_info_get(const struct rte_dma_dev *dev, struct rte_dma_info *dev_inf\n \tdev_info->nb_vchans = dpivf->num_vchans;\n \tdev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM | RTE_DMA_CAPA_MEM_TO_DEV |\n \t\t\t RTE_DMA_CAPA_DEV_TO_MEM | RTE_DMA_CAPA_DEV_TO_DEV |\n-\t\t\t RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG;\n+\t\t\t RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG |\n+\t\t\t RTE_DMA_CAPA_M2D_AUTO_FREE;\n \tdev_info->max_desc = CNXK_DPI_MAX_DESC;\n \tdev_info->min_desc = CNXK_DPI_MIN_DESC;\n \tdev_info->max_sges = CNXK_DPI_MAX_POINTER;\n@@ -115,9 +116,26 @@ cnxk_dmadev_configure(struct rte_dma_dev *dev, const struct rte_dma_conf *conf,\n \treturn 0;\n }\n \n-static void\n+static int\n+dmadev_src_buf_aura_get(struct rte_mempool *sb_mp, const char *mp_ops_name)\n+{\n+\tstruct rte_mempool_ops *ops;\n+\n+\tif (sb_mp == NULL)\n+\t\treturn 0;\n+\n+\tops = rte_mempool_get_ops(sb_mp->ops_index);\n+\tif (strcmp(ops->name, mp_ops_name) != 0)\n+\t\treturn -EINVAL;\n+\n+\treturn roc_npa_aura_handle_to_aura(sb_mp->pool_id);\n+}\n+\n+static int\n cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vchan_conf *conf)\n {\n+\tint aura;\n+\n \theader->cn9k.pt = DPI_HDR_PT_ZBW_CA;\n \n \tswitch (conf->direction) {\n@@ -140,6 +158,11 @@ cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vch\n \t\t\theader->cn9k.func = conf->dst_port.pcie.pfid << 12;\n \t\t\theader->cn9k.func |= conf->dst_port.pcie.vfid;\n \t\t}\n+\t\taura = dmadev_src_buf_aura_get(conf->auto_free.m2d.pool, \"cn9k_mempool_ops\");\n+\t\tif (aura < 0)\n+\t\t\treturn aura;\n+\t\theader->cn9k.aura = aura;\n+\t\theader->cn9k.ii = 1;\n \t\tbreak;\n \tcase RTE_DMA_DIR_MEM_TO_MEM:\n \t\theader->cn9k.xtype = DPI_XTYPE_INTERNAL_ONLY;\n@@ -153,11 +176,15 @@ cn9k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vch\n \t\theader->cn9k.fport = conf->dst_port.pcie.coreid;\n \t\theader->cn9k.pvfe = 0;\n \t};\n+\n+\treturn 0;\n }\n \n-static void\n+static int\n cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vchan_conf *conf)\n {\n+\tint aura;\n+\n \theader->cn10k.pt = DPI_HDR_PT_ZBW_CA;\n \n \tswitch (conf->direction) {\n@@ -180,6 +207,10 @@ cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vc\n \t\t\theader->cn10k.func = conf->dst_port.pcie.pfid << 12;\n \t\t\theader->cn10k.func |= conf->dst_port.pcie.vfid;\n \t\t}\n+\t\taura = dmadev_src_buf_aura_get(conf->auto_free.m2d.pool, \"cn10k_mempool_ops\");\n+\t\tif (aura < 0)\n+\t\t\treturn aura;\n+\t\theader->cn10k.aura = aura;\n \t\tbreak;\n \tcase RTE_DMA_DIR_MEM_TO_MEM:\n \t\theader->cn10k.xtype = DPI_XTYPE_INTERNAL_ONLY;\n@@ -193,6 +224,8 @@ cn10k_dmadev_setup_hdr(union cnxk_dpi_instr_cmd *header, const struct rte_dma_vc\n \t\theader->cn10k.fport = conf->dst_port.pcie.coreid;\n \t\theader->cn10k.pvfe = 0;\n \t};\n+\n+\treturn 0;\n }\n \n static int\n@@ -204,16 +237,19 @@ cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,\n \tunion cnxk_dpi_instr_cmd *header;\n \tuint16_t max_desc;\n \tuint32_t size;\n-\tint i;\n+\tint i, ret;\n \n \tRTE_SET_USED(conf_sz);\n \n \theader = (union cnxk_dpi_instr_cmd *)&dpi_conf->cmd.u;\n \n \tif (dpivf->is_cn10k)\n-\t\tcn10k_dmadev_setup_hdr(header, conf);\n+\t\tret = cn10k_dmadev_setup_hdr(header, conf);\n \telse\n-\t\tcn9k_dmadev_setup_hdr(header, conf);\n+\t\tret = cn9k_dmadev_setup_hdr(header, conf);\n+\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Free up descriptor memory before allocating. */\n \tcnxk_dmadev_vchan_free(dpivf, vchan);\ndiff --git a/drivers/dma/cnxk/cnxk_dmadev_fp.c b/drivers/dma/cnxk/cnxk_dmadev_fp.c\nindex 16d7b5426b..95df19a2db 100644\n--- a/drivers/dma/cnxk/cnxk_dmadev_fp.c\n+++ b/drivers/dma/cnxk/cnxk_dmadev_fp.c\n@@ -252,7 +252,7 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t d\n \tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n \n \tcmd[0] = (1UL << 54) | (1UL << 48);\n-\tcmd[1] = dpi_conf->cmd.u;\n+\tcmd[1] = dpi_conf->cmd.u | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 37);\n \tcmd[2] = (uint64_t)comp_ptr;\n \tcmd[4] = length;\n \tcmd[6] = length;\n@@ -308,7 +308,7 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n \tcomp_ptr = dpi_conf->c_desc.compl_ptr[dpi_conf->c_desc.tail];\n \tCNXK_DPI_STRM_INC(dpi_conf->c_desc, tail);\n \n-\thdr[1] = dpi_conf->cmd.u;\n+\thdr[1] = dpi_conf->cmd.u | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 37);\n \thdr[2] = (uint64_t)comp_ptr;\n \n \t/*\n@@ -365,7 +365,7 @@ cn10k_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t\n \n \tcmd[0] = dpi_conf->cmd.u | (1U << 6) | 1U;\n \tcmd[1] = (uint64_t)comp_ptr;\n-\tcmd[2] = 0;\n+\tcmd[2] = (1UL << 47) | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 43);\n \tcmd[4] = length;\n \tcmd[5] = src;\n \tcmd[6] = length;\n@@ -412,7 +412,7 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge\n \n \thdr[0] = dpi_conf->cmd.u | (nb_dst << 6) | nb_src;\n \thdr[1] = (uint64_t)comp_ptr;\n-\thdr[2] = 0;\n+\thdr[2] = (1UL << 47) | ((flags & RTE_DMA_OP_FLAG_AUTO_FREE) << 43);\n \n \trc = __dpi_queue_write_sg(dpivf, hdr, src, dst, nb_src, nb_dst);\n \tif (unlikely(rc)) {\n", "prefixes": [ "v2" ] }