Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/132648/?format=api
{ "id": 132648, "url": "https://patches.dpdk.org/api/patches/132648/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231016184235.200427-12-getelson@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231016184235.200427-12-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231016184235.200427-12-getelson@nvidia.com", "date": "2023-10-16T18:42:31", "name": "[v2,12/16] net/mlx5: refactor HWS code", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0db997d9508f0d05110c2e415830ea0d3fd345b2", "submitter": { "id": 1882, "url": "https://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231016184235.200427-12-getelson@nvidia.com/mbox/", "series": [ { "id": 29662, "url": "https://patches.dpdk.org/api/series/29662/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29662", "date": "2023-09-27T19:10:46", "name": "net/mlx5: support indirect list actions", "version": 1, "mbox": "https://patches.dpdk.org/series/29662/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/132648/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/132648/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A377343181;\n\tMon, 16 Oct 2023 20:44:33 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EE11040F16;\n\tMon, 16 Oct 2023 20:43:45 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2083.outbound.protection.outlook.com [40.107.223.83])\n by mails.dpdk.org (Postfix) with ESMTP id 3AE5740E72\n for <dev@dpdk.org>; Mon, 16 Oct 2023 20:43:44 +0200 (CEST)", "from SN4PR0501CA0111.namprd05.prod.outlook.com\n (2603:10b6:803:42::28) by CY8PR12MB7416.namprd12.prod.outlook.com\n (2603:10b6:930:5c::10) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36; Mon, 16 Oct\n 2023 18:43:42 +0000", "from SN1PEPF0002636C.namprd02.prod.outlook.com\n (2603:10b6:803:42:cafe::1a) by SN4PR0501CA0111.outlook.office365.com\n (2603:10b6:803:42::28) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.18 via Frontend\n Transport; Mon, 16 Oct 2023 18:43:42 +0000", "from mail.nvidia.com (216.228.117.161) by\n SN1PEPF0002636C.mail.protection.outlook.com (10.167.241.137) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6838.22 via Frontend Transport; Mon, 16 Oct 2023 18:43:42 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 16 Oct\n 2023 11:43:28 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 16 Oct\n 2023 11:43:25 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=ZUJVHFTtMdwdEfaAtk5zZuxI0kpSU+tUnD/Ssky+Qss2yBMrBrBsBEro/Yjt8respD8cgN9KCju5pM+hLUcmrB+KPp3LQge+xeWe8jkHg8UEn5BLklppS9Snr1FTUWctMCeueoiIjaVkT514frBWUblYdPlg+TRgx16eGGFXhnpNKRUMB/Na59EYMCFdvXyPdtqy1H0Eeb9Q4vMfp8S/IzfFnypuheRYH4PgpydFQwXMZyeDOThqUZiyXvepMOg2flKnwhaBIZzIj6bkUbk3GLsbbYu39HaX/QCXmijmjFSmen0vHWJS92+D/eA4D73qzTpY/sG7Z25pw1jkLaNxsA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=Kfl771J46HOq757AhzPpxtaW3N3/AoH7cu1WMtEfO8c=;\n b=K71wSU4KPJprDMHREhSHlvyRDHIGlxw9hai4Owwbu+FtNJu+cXdhtyU2vRnZBT5erPB9xUVQYEFr7ya3aI3Jaw4QeqshDXvIfaW1i/HieF7Av/jBQ5tEgnsEcQWKA7Rwq9f5sO56hNZWosup7assbQyIFIixnfzIc0khhAsHyQy5PdKHfW1yCDpUI/YfVainIbZJ9OWqvp4QYgjRu46lc4mN/HaTaT0l3xy8ZGK425sIqhyJK550bfcBtkPojAewEs+ObRr5kmUs0ZljOsm+Qunx/VOfKUN7whCnubwRAZ5l40V0wXJZL3Ai1N5mhEqc7+X6k56b1LvIY+1+vFBcEQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Kfl771J46HOq757AhzPpxtaW3N3/AoH7cu1WMtEfO8c=;\n b=CcqQRMjAFU/Vz6m1Me3U7/bqh9E59eBAyqGaqZiRYs2LHP4FL7+AjNsc3rp7xWyXfiKbCOutfJDGMpiYAigF7VPLaYd03caq77378vF/m+Rd9DBQ3FDhgWYM2LCdkPduu39LwSxstLNvdWXJYIuvZCmjbFDcINZHANH0qm1W++x9Sk8cqoRxtRozNpX/iUn/SvPMIB/R2U8pF5jvQEzuX4MTUY+gljk/fUavHcLll+x+KXXDoOAswA9XXwgO2YnBbDI0IL8C3l9HwKbpoKBx8tjMLeO+M7f8in3T+mpg/tU3n3RgY/HlBBmz4fICZ6oc/neNu0Y7u0PmuJ+8utRUYA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, =?utf-8?b?wqA=?= <mkashani@nvidia.com>,\n\t=?utf-8?q?=C2=A0_=2E_=2E_/patches/upstream-pmd-indirect-actions-list/v2/v2-?=\n\t=?utf-8?q?0000-cover-letter_=2E_patch?= <rasland@nvidia.com>,\n Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>", "Subject": "[PATCH v2 12/16] net/mlx5: refactor HWS code", "Date": "Mon, 16 Oct 2023 21:42:31 +0300", "Message-ID": "<20231016184235.200427-12-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231016184235.200427-1-getelson@nvidia.com>", "References": "<20230927191046.405282-1-getelson@nvidia.com>\n <20231016184235.200427-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF0002636C:EE_|CY8PR12MB7416:EE_", "X-MS-Office365-Filtering-Correlation-Id": "bc79061b-bd40-4cdd-e654-08dbce77d210", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n nWPB28xVYcxJmSYNPM0qTgdVX9+/Hk/UpSq6UNeE1xpsSAf+btA1hJkumPQh6eDxAKm8E2fPgCdjEpmkTdhqnvy9Vu/hpGT1MsqVHt9Zmk/JLedSpW0/Xngw9oBLegGyOJ64dP5y4MlZT+ltadqlE8eQaQJfYVwkI2TO5U2nm5g2QB8PQbZrkTlLS8fpuBOmMqf77r2l5hsbV4U/1KZMhk7i62Tkd3M3f2bDsSw2y4yxUYQTZkcxPLMK8IMMjRHgCCGO33elMy7vrr8JC5X1bdueA8E8fZcsHtVezVCkxCnINh7HrngTxI2BjIF1QsINH7p8Pz6cLwU+6ZIv1guOU4LUKGBx1w04Y6f3wYlg9Rv17oNF2yXM6p/XvvrN6nM5XujAq+2nmSo/NfETmws4mgow/DMgYVC/lStCssqVoiU3yuUOHKzDDqTVHi+7r8nfWaaNptLxxqwEAyZkER7+phHAuZ8R8WSmV+zL5eJ33Y0Mqm5bahipjfc1jDLW1U20N7d3664KjzaiKDFAakN8E3rOBz3Xc8i4ia+ctsWhPKjgaFZzUGC9OvzC4kCF/JHopgAuW+lnk3MqrAsFEGGsXNB8QAh8CJJ6RIqGYhV1SahFdTB13vKIX8hxsChYUEL1iCYCGAypUcF92/SCrbFy1FBD40xkoa+DzKh528DlT4fXtIr4VUBqbboD/fh9tFAb0fi34E3WztsiVvz12+qpzoBAhKG/vddR+2cY3KrLByKM4BYGetGv8RSCLkwftO94", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(376002)(396003)(39860400002)(346002)(230922051799003)(82310400011)(451199024)(186009)(1800799009)(64100799003)(46966006)(36840700001)(40470700004)(40480700001)(40460700003)(55016003)(478600001)(6666004)(70586007)(70206006)(54906003)(6916009)(316002)(47076005)(356005)(83380400001)(36860700001)(86362001)(82740400003)(26005)(1076003)(107886003)(16526019)(6286002)(2616005)(7696005)(336012)(426003)(36756003)(41300700001)(7636003)(30864003)(5660300002)(8936002)(8676002)(4326008)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Oct 2023 18:43:42.2247 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bc79061b-bd40-4cdd-e654-08dbce77d210", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF0002636C.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY8PR12MB7416", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "1. In `rte_flow_actions_template`, rename `actions_off` into `dr_off`.\n2. Remove duplicated code in template table creation.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 2 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 117 ++++++++++++++------------------\n 2 files changed, 52 insertions(+), 67 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex f6a752475d..a31120cd78 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1331,7 +1331,7 @@ struct rte_flow_actions_template {\n \tuint64_t action_flags; /* Bit-map of all valid action in template. */\n \tuint16_t dr_actions_num; /* Amount of DR rules actions. */\n \tuint16_t actions_num; /* Amount of flow actions */\n-\tuint16_t *actions_off; /* DR action offset for given rte action offset. */\n+\tuint16_t *dr_off; /* DR action offset for given rte action offset. */\n \tuint16_t reformat_off; /* Offset of DR reformat action. */\n \tuint16_t mhdr_off; /* Offset of DR modify header action. */\n \tuint32_t refcnt; /* Reference counter. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7b060442ac..53641ae2d5 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -1506,7 +1506,7 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \tuint32_t type;\n \tbool reformat_used = false;\n \tunsigned int of_vlan_offset;\n-\tuint16_t action_pos;\n+\tuint16_t dr_pos;\n \tuint16_t jump_pos;\n \tuint32_t ct_idx;\n \tint ret, err;\n@@ -1521,9 +1521,9 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \telse\n \t\ttype = MLX5DR_TABLE_TYPE_NIC_RX;\n \tfor (; !actions_end; actions++, masks++) {\n+\t\tdr_pos = at->dr_off[actions - at->actions];\n \t\tswitch ((int)actions->type) {\n \t\tcase RTE_FLOW_ACTION_TYPE_INDIRECT_LIST:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (!attr->group) {\n \t\t\t\tDRV_LOG(ERR, \"Indirect action is not supported in root table.\");\n \t\t\t\tgoto err;\n@@ -1531,61 +1531,57 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tret = table_template_translate_indirect_list\n \t\t\t\t(dev, actions, masks, acts,\n \t\t\t\t actions - action_start,\n-\t\t\t\t action_pos);\n+\t\t\t\t dr_pos);\n \t\t\tif (ret)\n \t\t\t\tgoto err;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_INDIRECT:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (!attr->group) {\n \t\t\t\tDRV_LOG(ERR, \"Indirect action is not supported in root table.\");\n \t\t\t\tgoto err;\n \t\t\t}\n \t\t\tif (actions->conf && masks->conf) {\n \t\t\t\tif (flow_hw_shared_action_translate\n-\t\t\t\t(dev, actions, acts, actions - action_start, action_pos))\n+\t\t\t\t(dev, actions, acts, actions - action_start, dr_pos))\n \t\t\t\t\tgoto err;\n \t\t\t} else if (__flow_hw_act_data_general_append\n-\t\t\t\t\t(priv, acts, actions->type,\n-\t\t\t\t\t actions - action_start, action_pos)){\n+\t\t\t\t\t(priv, acts, RTE_FLOW_ACTION_TYPE_INDIRECT,\n+\t\t\t\t\t actions - action_start, dr_pos)){\n \t\t\t\tgoto err;\n \t\t\t}\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n-\t\t\tacts->rule_acts[action_pos].action =\n+\t\t\tacts->rule_acts[dr_pos].action =\n \t\t\t\tpriv->hw_drop[!!attr->group];\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_MARK:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tacts->mark = true;\n \t\t\tif (masks->conf &&\n \t\t\t ((const struct rte_flow_action_mark *)\n \t\t\t masks->conf)->id)\n-\t\t\t\tacts->rule_acts[action_pos].tag.value =\n+\t\t\t\tacts->rule_acts[dr_pos].tag.value =\n \t\t\t\t\tmlx5_flow_mark_set\n \t\t\t\t\t(((const struct rte_flow_action_mark *)\n \t\t\t\t\t(actions->conf))->id);\n \t\t\telse if (__flow_hw_act_data_general_append(priv, acts,\n-\t\t\t\tactions->type, actions - action_start, action_pos))\n+\t\t\t\t\t\t\t\t actions->type, actions - action_start, dr_pos))\n \t\t\t\tgoto err;\n-\t\t\tacts->rule_acts[action_pos].action =\n+\t\t\tacts->rule_acts[dr_pos].action =\n \t\t\t\tpriv->hw_tag[!!attr->group];\n \t\t\t__atomic_fetch_add(&priv->hws_mark_refcnt, 1, __ATOMIC_RELAXED);\n \t\t\tflow_hw_rxq_flag_set(dev, true);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n-\t\t\tacts->rule_acts[action_pos].action =\n+\t\t\tacts->rule_acts[dr_pos].action =\n \t\t\t\tpriv->hw_push_vlan[type];\n \t\t\tif (is_template_masked_push_vlan(masks->conf))\n-\t\t\t\tacts->rule_acts[action_pos].push_vlan.vlan_hdr =\n+\t\t\t\tacts->rule_acts[dr_pos].push_vlan.vlan_hdr =\n \t\t\t\t\tvlan_hdr_to_be32(actions);\n \t\t\telse if (__flow_hw_act_data_general_append\n \t\t\t\t\t(priv, acts, actions->type,\n-\t\t\t\t\t actions - action_start, action_pos))\n+\t\t\t\t\t actions - action_start, dr_pos))\n \t\t\t\tgoto err;\n \t\t\tof_vlan_offset = is_of_vlan_pcp_present(actions) ?\n \t\t\t\t\tMLX5_HW_VLAN_PUSH_PCP_IDX :\n@@ -1594,12 +1590,10 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tmasks += of_vlan_offset;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n-\t\t\tacts->rule_acts[action_pos].action =\n+\t\t\tacts->rule_acts[dr_pos].action =\n \t\t\t\tpriv->hw_pop_vlan[type];\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_JUMP:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (masks->conf &&\n \t\t\t ((const struct rte_flow_action_jump *)\n \t\t\t masks->conf)->group) {\n@@ -1610,17 +1604,16 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t(dev, cfg, jump_group, error);\n \t\t\t\tif (!acts->jump)\n \t\t\t\t\tgoto err;\n-\t\t\t\tacts->rule_acts[action_pos].action = (!!attr->group) ?\n-\t\t\t\t\t\tacts->jump->hws_action :\n-\t\t\t\t\t\tacts->jump->root_action;\n+\t\t\t\tacts->rule_acts[dr_pos].action = (!!attr->group) ?\n+\t\t\t\t\t\t\t\t acts->jump->hws_action :\n+\t\t\t\t\t\t\t\t acts->jump->root_action;\n \t\t\t} else if (__flow_hw_act_data_general_append\n \t\t\t\t\t(priv, acts, actions->type,\n-\t\t\t\t\t actions - action_start, action_pos)){\n+\t\t\t\t\t actions - action_start, dr_pos)){\n \t\t\t\tgoto err;\n \t\t\t}\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (masks->conf &&\n \t\t\t ((const struct rte_flow_action_queue *)\n \t\t\t masks->conf)->index) {\n@@ -1630,16 +1623,15 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\t actions);\n \t\t\t\tif (!acts->tir)\n \t\t\t\t\tgoto err;\n-\t\t\t\tacts->rule_acts[action_pos].action =\n+\t\t\t\tacts->rule_acts[dr_pos].action =\n \t\t\t\t\tacts->tir->action;\n \t\t\t} else if (__flow_hw_act_data_general_append\n \t\t\t\t\t(priv, acts, actions->type,\n-\t\t\t\t\t actions - action_start, action_pos)) {\n+\t\t\t\t\t actions - action_start, dr_pos)) {\n \t\t\t\tgoto err;\n \t\t\t}\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (actions->conf && masks->conf) {\n \t\t\t\tacts->tir = flow_hw_tir_action_register\n \t\t\t\t(dev,\n@@ -1647,11 +1639,11 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\t actions);\n \t\t\t\tif (!acts->tir)\n \t\t\t\t\tgoto err;\n-\t\t\t\tacts->rule_acts[action_pos].action =\n+\t\t\t\tacts->rule_acts[dr_pos].action =\n \t\t\t\t\tacts->tir->action;\n \t\t\t} else if (__flow_hw_act_data_general_append\n \t\t\t\t\t(priv, acts, actions->type,\n-\t\t\t\t\t actions - action_start, action_pos)) {\n+\t\t\t\t\t actions - action_start, dr_pos)) {\n \t\t\t\tgoto err;\n \t\t\t}\n \t\t\tbreak;\n@@ -1720,11 +1712,10 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\t\t\tNULL,\n \t\t\t\t\t\t\"Send to kernel action on root table is not supported in HW steering mode\");\n \t\t\t}\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\ttable_type = attr->ingress ? MLX5DR_TABLE_TYPE_NIC_RX :\n \t\t\t\t ((attr->egress) ? MLX5DR_TABLE_TYPE_NIC_TX :\n-\t\t\t\t MLX5DR_TABLE_TYPE_FDB);\n-\t\t\tacts->rule_acts[action_pos].action = priv->hw_send_to_kernel[table_type];\n+\t\t\t\t MLX5DR_TABLE_TYPE_FDB);\n+\t\t\tacts->rule_acts[dr_pos].action = priv->hw_send_to_kernel[table_type];\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:\n \t\t\terr = flow_hw_modify_field_compile(dev, attr, action_start,\n@@ -1744,10 +1735,9 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\taction_start += 1;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (flow_hw_represented_port_compile\n \t\t\t\t\t(dev, attr, action_start, actions,\n-\t\t\t\t\t masks, acts, action_pos, error))\n+\t\t\t\t\t masks, acts, dr_pos, error))\n \t\t\t\tgoto err;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_METER:\n@@ -1756,19 +1746,18 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t * Calculated DR offset is stored only for ASO_METER and FT\n \t\t\t * is assumed to be the next action.\n \t\t\t */\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n-\t\t\tjump_pos = action_pos + 1;\n+\t\t\tjump_pos = dr_pos + 1;\n \t\t\tif (actions->conf && masks->conf &&\n \t\t\t ((const struct rte_flow_action_meter *)\n \t\t\t masks->conf)->mtr_id) {\n \t\t\t\terr = flow_hw_meter_compile(dev, cfg,\n-\t\t\t\t\t\taction_pos, jump_pos, actions, acts, error);\n+\t\t\t\t\t\t\t dr_pos, jump_pos, actions, acts, error);\n \t\t\t\tif (err)\n \t\t\t\t\tgoto err;\n \t\t\t} else if (__flow_hw_act_data_general_append(priv, acts,\n-\t\t\t\t\t\t\tactions->type,\n+\t\t\t\t\t\t\t\t actions->type,\n \t\t\t\t\t\t\tactions - action_start,\n-\t\t\t\t\t\t\taction_pos))\n+\t\t\t\t\t\t\t\t dr_pos))\n \t\t\t\tgoto err;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_AGE:\n@@ -1781,11 +1770,10 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\t\t\tNULL,\n \t\t\t\t\t\t\"Age action on root table is not supported in HW steering mode\");\n \t\t\t}\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (__flow_hw_act_data_general_append(priv, acts,\n-\t\t\t\t\t\t\t actions->type,\n+\t\t\t\t\t\t\t actions->type,\n \t\t\t\t\t\t\t actions - action_start,\n-\t\t\t\t\t\t\t action_pos))\n+\t\t\t\t\t\t\t dr_pos))\n \t\t\t\tgoto err;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n@@ -1806,49 +1794,46 @@ __flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\t * counter.\n \t\t\t\t */\n \t\t\t\tbreak;\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (masks->conf &&\n \t\t\t ((const struct rte_flow_action_count *)\n \t\t\t masks->conf)->id) {\n-\t\t\t\terr = flow_hw_cnt_compile(dev, action_pos, acts);\n+\t\t\t\terr = flow_hw_cnt_compile(dev, dr_pos, acts);\n \t\t\t\tif (err)\n \t\t\t\t\tgoto err;\n \t\t\t} else if (__flow_hw_act_data_general_append\n \t\t\t\t\t(priv, acts, actions->type,\n-\t\t\t\t\t actions - action_start, action_pos)) {\n+\t\t\t\t\t actions - action_start, dr_pos)) {\n \t\t\t\tgoto err;\n \t\t\t}\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (masks->conf) {\n \t\t\t\tct_idx = MLX5_ACTION_CTX_CT_GET_IDX\n \t\t\t\t\t ((uint32_t)(uintptr_t)actions->conf);\n \t\t\t\tif (flow_hw_ct_compile(dev, MLX5_HW_INV_QUEUE, ct_idx,\n-\t\t\t\t\t\t &acts->rule_acts[action_pos]))\n+\t\t\t\t\t\t &acts->rule_acts[dr_pos]))\n \t\t\t\t\tgoto err;\n \t\t\t} else if (__flow_hw_act_data_general_append\n \t\t\t\t\t(priv, acts, actions->type,\n-\t\t\t\t\t actions - action_start, action_pos)) {\n+\t\t\t\t\t actions - action_start, dr_pos)) {\n \t\t\t\tgoto err;\n \t\t\t}\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_METER_MARK:\n-\t\t\taction_pos = at->actions_off[actions - at->actions];\n \t\t\tif (actions->conf && masks->conf &&\n \t\t\t ((const struct rte_flow_action_meter_mark *)\n \t\t\t masks->conf)->profile) {\n \t\t\t\terr = flow_hw_meter_mark_compile(dev,\n-\t\t\t\t\t\t\taction_pos, actions,\n-\t\t\t\t\t\t\tacts->rule_acts,\n-\t\t\t\t\t\t\t&acts->mtr_id,\n-\t\t\t\t\t\t\tMLX5_HW_INV_QUEUE);\n+\t\t\t\t\t\t\t\t dr_pos, actions,\n+\t\t\t\t\t\t\t\t acts->rule_acts,\n+\t\t\t\t\t\t\t\t &acts->mtr_id,\n+\t\t\t\t\t\t\t\t MLX5_HW_INV_QUEUE);\n \t\t\t\tif (err)\n \t\t\t\t\tgoto err;\n \t\t\t} else if (__flow_hw_act_data_general_append(priv, acts,\n-\t\t\t\t\t\t\tactions->type,\n+\t\t\t\t\t\t\t\t actions->type,\n \t\t\t\t\t\t\tactions - action_start,\n-\t\t\t\t\t\t\taction_pos))\n+\t\t\t\t\t\t\t\t dr_pos))\n \t\t\t\tgoto err;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_END:\n@@ -4681,7 +4666,7 @@ action_template_set_type(struct rte_flow_actions_template *at,\n \t\t\t unsigned int action_src, uint16_t *curr_off,\n \t\t\t enum mlx5dr_action_type type)\n {\n-\tat->actions_off[action_src] = *curr_off;\n+\tat->dr_off[action_src] = *curr_off;\n \taction_types[*curr_off] = type;\n \t*curr_off = *curr_off + 1;\n }\n@@ -4718,7 +4703,7 @@ flow_hw_dr_actions_template_handle_shared(const struct rte_flow_action *mask,\n \t\t\t\t\t\t action_src, curr_off,\n \t\t\t\t\t\t MLX5DR_ACTION_TYP_CTR);\n \t\t}\n-\t\tat->actions_off[action_src] = *cnt_off;\n+\t\tat->dr_off[action_src] = *cnt_off;\n \t\tbreak;\n \tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n \t\taction_template_set_type(at, action_types, action_src, curr_off,\n@@ -4838,7 +4823,7 @@ flow_hw_dr_actions_template_create(struct rte_flow_actions_template *at)\n \t\t\t}\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_METER:\n-\t\t\tat->actions_off[i] = curr_off;\n+\t\t\tat->dr_off[i] = curr_off;\n \t\t\taction_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;\n \t\t\tif (curr_off >= MLX5_HW_MAX_ACTS)\n \t\t\t\tgoto err_actions_num;\n@@ -4846,14 +4831,14 @@ flow_hw_dr_actions_template_create(struct rte_flow_actions_template *at)\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:\n \t\t\ttype = mlx5_hw_dr_action_types[at->actions[i].type];\n-\t\t\tat->actions_off[i] = curr_off;\n+\t\t\tat->dr_off[i] = curr_off;\n \t\t\taction_types[curr_off++] = type;\n \t\t\ti += is_of_vlan_pcp_present(at->actions + i) ?\n \t\t\t\tMLX5_HW_VLAN_PUSH_PCP_IDX :\n \t\t\t\tMLX5_HW_VLAN_PUSH_VID_IDX;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_METER_MARK:\n-\t\t\tat->actions_off[i] = curr_off;\n+\t\t\tat->dr_off[i] = curr_off;\n \t\t\taction_types[curr_off++] = MLX5DR_ACTION_TYP_ASO_METER;\n \t\t\tif (curr_off >= MLX5_HW_MAX_ACTS)\n \t\t\t\tgoto err_actions_num;\n@@ -4869,11 +4854,11 @@ flow_hw_dr_actions_template_create(struct rte_flow_actions_template *at)\n \t\t\t\tcnt_off = curr_off++;\n \t\t\t\taction_types[cnt_off] = MLX5DR_ACTION_TYP_CTR;\n \t\t\t}\n-\t\t\tat->actions_off[i] = cnt_off;\n+\t\t\tat->dr_off[i] = cnt_off;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\ttype = mlx5_hw_dr_action_types[at->actions[i].type];\n-\t\t\tat->actions_off[i] = curr_off;\n+\t\t\tat->dr_off[i] = curr_off;\n \t\t\taction_types[curr_off++] = type;\n \t\t\tbreak;\n \t\t}\n@@ -5234,7 +5219,7 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev,\n \tif (mask_len <= 0)\n \t\treturn NULL;\n \tlen += RTE_ALIGN(mask_len, 16);\n-\tlen += RTE_ALIGN(act_num * sizeof(*at->actions_off), 16);\n+\tlen += RTE_ALIGN(act_num * sizeof(*at->dr_off), 16);\n \tat = mlx5_malloc(MLX5_MEM_ZERO, len + sizeof(*at),\n \t\t\t RTE_CACHE_LINE_SIZE, rte_socket_id());\n \tif (!at) {\n@@ -5258,10 +5243,10 @@ flow_hw_actions_template_create(struct rte_eth_dev *dev,\n \tif (mask_len <= 0)\n \t\tgoto error;\n \t/* DR actions offsets in the third part. */\n-\tat->actions_off = (uint16_t *)((uint8_t *)at->masks + mask_len);\n+\tat->dr_off = (uint16_t *)((uint8_t *)at->masks + mask_len);\n \tat->actions_num = act_num;\n \tfor (i = 0; i < at->actions_num; ++i)\n-\t\tat->actions_off[i] = UINT16_MAX;\n+\t\tat->dr_off[i] = UINT16_MAX;\n \tat->reformat_off = UINT16_MAX;\n \tat->mhdr_off = UINT16_MAX;\n \tat->rx_cpy_pos = pos;\n", "prefixes": [ "v2", "12/16" ] }