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GET /api/patches/132395/?format=api
{ "id": 132395, "url": "https://patches.dpdk.org/api/patches/132395/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20231008031029.30850-3-haifeil@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231008031029.30850-3-haifeil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231008031029.30850-3-haifeil@nvidia.com", "date": "2023-10-08T03:10:26", "name": "[v4,2/5] common/mlx5: extend HCA attribute query for NSH", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "32c817373050b45ca73e2f63b97a0d3d4dc7f1f3", "submitter": { "id": 2131, "url": "https://patches.dpdk.org/api/people/2131/?format=api", "name": "Haifei Luo", "email": "haifeil@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20231008031029.30850-3-haifeil@nvidia.com/mbox/", "series": [ { "id": 29763, "url": "https://patches.dpdk.org/api/series/29763/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29763", "date": "2023-10-08T03:10:24", "name": "support item NSH matching", "version": 4, "mbox": "https://patches.dpdk.org/series/29763/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/132395/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/132395/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 75D76426E8;\n\tSun, 8 Oct 2023 05:11:36 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB53C402DF;\n\tSun, 8 Oct 2023 05:11:29 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2054.outbound.protection.outlook.com [40.107.93.54])\n by mails.dpdk.org (Postfix) with ESMTP id A2EEC402C2\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Haifei Luo <haifeil@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <rasland@nvidia.com>,\n <xuemingl@nvidia.com>, <haifeil@nvidia.com>, Dariusz Sosnowski\n <dsosnowski@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>, Matan Azrad\n <matan@nvidia.com>", "Subject": "[PATCH v4 2/5] common/mlx5: extend HCA attribute query for NSH", "Date": "Sun, 8 Oct 2023 06:10:26 +0300", "Message-ID": "<20231008031029.30850-3-haifeil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20231008031029.30850-1-haifeil@nvidia.com>", "References": "<20230925080746.16438-1-haifeil@nvidia.com>\n <20231008031029.30850-1-haifeil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000971E7:EE_|PH8PR12MB6937:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b304befc-127b-4839-92ee-08dbc7ac41a7", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n FDtW0x6E2VYgzwdeu2wADno/LzUbzgQZoTqjt0KMOyUyeNUFHGB2GdryG8MONgrFrRIS2nk/jTdcusotOqK8yDJyJHtCuy39ImH+mr/42NQe2VY7Lp38j53riuyv3nUHSGXtVquHDz7bhk6K5kmf5pWxQcUxG0ktUfeIFtNLaJcACtHVUPFP0zLQ6Prvy4ocEg79VZA506OGF7mQrqkQ5RgoC19nhIH8fTJKYNt02/e1R/+ppU1ahsK7YQjvxzR8XHXiqC3DBgViEUsdtaHpVaLa1WLfP0t07sUfQjR+skI+5btjjdHcPcLoe8B7UXCtjZnn12+QHkzpurf26wuyY2OQIz5MFfZH54bugmhbB833oFG3l7bh8Gus4GrA+rkS92IvZQoBUqgEDY4Mgf1hh7ueqG6IHqLmv/EZM6D050iHemh1u3eQM/pjUnC0hPi9dpi9y6A7GMh8iG9BGX1Ek/GrwC8YfMZ2yS0aNveBW1/6ympahp8C/CZL1pVOL7VwRANsl+ZnQHBM/LBFuM+NWn3aANTWTOfWei7HqrG8EUqmS3gOm1YTyLoq/xBahWrn6JibB7p3NDvdKSdAVVRiWWSm5jNQVaw+XvP6FqHQOTvl19L4eEu288bXezeAoT0S8d6yDKTuv5X+mhoqogcKMq5YAogdZFVbNPsIrwW+uw72AJ25GeUL8fqD3tyCBpQq1EglbyVJZfwtoabp/f4OBJ4ApeeqQEVm4TH6EXnbh+O7F22SjC9ulCJ8id+sPeih", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(376002)(346002)(39860400002)(136003)(396003)(230922051799003)(1800799009)(64100799003)(451199024)(186009)(82310400011)(40470700004)(36840700001)(46966006)(2616005)(1076003)(6286002)(26005)(336012)(16526019)(426003)(40460700003)(55016003)(36756003)(40480700001)(86362001)(82740400003)(356005)(7636003)(107886003)(83380400001)(4326008)(2906002)(478600001)(8676002)(6666004)(7696005)(47076005)(36860700001)(41300700001)(5660300002)(6916009)(316002)(8936002)(54906003)(70586007)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Oct 2023 03:11:25.1141 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b304befc-127b-4839-92ee-08dbc7ac41a7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000971E7.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB6937", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add NSH supporting field in two places:\n1. New HCA capability indicating NSH is supported\n2. New field in \"mlx5_ifc_per_protocol_networking_offload_caps_bits\"\n structure\n\nSigned-off-by: Haifei Luo <haifeil@nvidia.com>\nAcked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 4 +++-\n 3 files changed, 7 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 66a77159a0..830199212e 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1313,6 +1313,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->tunnel_stateless_gtp = MLX5_GET\n \t\t\t\t\t(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, tunnel_stateless_gtp);\n+\tattr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET\n+\t\t\t\t\t(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, tunnel_stateless_vxlan_gpe_nsh);\n \tattr->rss_ind_tbl_cap = MLX5_GET\n \t\t\t\t\t(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, rss_ind_tbl_cap);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex e071cd841f..11772431ae 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -196,6 +196,7 @@ struct mlx5_hca_attr {\n \tuint32_t tunnel_stateless_geneve_rx:1;\n \tuint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */\n \tuint32_t tunnel_stateless_gtp:1;\n+\tuint32_t tunnel_stateless_vxlan_gpe_nsh:1;\n \tuint32_t max_lso_cap;\n \tuint32_t scatter_fcs:1;\n \tuint32_t lro_cap:1;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 51f426c614..f005877dd7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1964,7 +1964,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 swp_lso[0x1];\n \tu8 reserved_at_23[0x8];\n \tu8 tunnel_stateless_gtp[0x1];\n-\tu8 reserved_at_25[0x4];\n+\tu8 reserved_at_25[0x2];\n+\tu8 tunnel_stateless_vxlan_gpe_nsh[0x1];\n+\tu8 reserved_at_28[0x1];\n \tu8 max_vxlan_udp_ports[0x8];\n \tu8 reserved_at_38[0x6];\n \tu8 max_geneve_opt_len[0x1];\n", "prefixes": [ "v4", "2/5" ] }