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GET /api/patches/131983/?format=api
{ "id": 131983, "url": "https://patches.dpdk.org/api/patches/131983/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230926200027.210276-1-sivaprasad.tummala@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230926200027.210276-1-sivaprasad.tummala@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230926200027.210276-1-sivaprasad.tummala@amd.com", "date": "2023-09-26T20:00:27", "name": "[v2] power: support amd-pstate cpufreq driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "02e50a12184888b41cf659b40a58dd6135fff720", "submitter": { "id": 2510, "url": "https://patches.dpdk.org/api/people/2510/?format=api", "name": "Sivaprasad Tummala", "email": "Sivaprasad.Tummala@amd.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230926200027.210276-1-sivaprasad.tummala@amd.com/mbox/", "series": [ { "id": 29647, "url": "https://patches.dpdk.org/api/series/29647/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29647", "date": "2023-09-26T20:00:27", "name": "[v2] power: support amd-pstate cpufreq driver", "version": 2, "mbox": "https://patches.dpdk.org/series/29647/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131983/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/131983/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9380142649;\n\tTue, 26 Sep 2023 22:00:49 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 33ACF40271;\n\tTue, 26 Sep 2023 22:00:49 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2058.outbound.protection.outlook.com [40.107.220.58])\n by mails.dpdk.org (Postfix) with ESMTP id 9C63940269\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Sivaprasad Tummala <sivaprasad.tummala@amd.com>", "To": "<anatoly.burakov@intel.com>, <david.hunt@intel.com>, <thomas@monjalon.net>", "CC": "<dev@dpdk.org>, <kevin.laatz@intel.com>, <ferruh.yigit@amd.com>", "Subject": "[PATCH v2] power: support amd-pstate cpufreq driver", "Date": "Tue, 26 Sep 2023 13:00:27 -0700", "Message-ID": "<20230926200027.210276-1-sivaprasad.tummala@amd.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS1PEPF0001709C:EE_|LV2PR12MB5870:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c9d47d7c-b33a-421a-0376-08dbbecb43b1", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n PoynYHn7F6N6IFyEz0ZFV0yyI1wyqq+DIcwVknCMq/Z8StZnRF+584UnpdalKu2Vpfc9I55mPRF2G9KCv5N4uClTV7xELnZxxFM0H9129/PLnFCH7MwpmtCp9Kar1/RsttZYbJnGBk++ueXyFFB3YGg88XCiVOtAuBJNXCDjbV/OKm3vkZIeGMpOuZoZ3xre83DPZwj4gBMgnQdh19VJyfWaNQ+YacXGdhnc62jKdnY+jsRG601EmrhR9+enaX94NQpQ5Pg4vFs5MCfQTCKbLDRFB0AAlMbRhSv4GejvQD82G1NbHUAtwyI5NdQtrv0SLHwQT0BipJK5X4etqU5d6pVYn9kFBrek86DDu3fXkh9vs2YqWa2KdJTeQ1OI7fOMVCH1U6uppEIACgRbxp24Vm4GwUjnLtb8CYA9ON2lhdsjEm0rz2DUWCGAUFsc+QlPSzZQpcDFd/QjWVignJ3zJy6VHHK8qEUhhkB8sBSNUjj8SPMhCjTckeP+tcQFiOfGn5dkMk/5MnryxErYfDPxsT/eljxmlWfOl6ZJ+o0IFQ3P5un8qTHYmJ9v5bhUmvkUjOavUoU7lEki6V5aF4J0DzNmBzb2Pf0uqKVpwPmdRkE42IB12K6aq3TioyZg19FsQ/B69OxtuKlXj0Hs7gOT3orbl89+CqxpqPzg+xtALv819ueNAHofjaDphsMs7zT9ZDCov/lfYsqw74HCtJRcgjynqc35ZLUR6xNcrxLjidK4opGbwC3VRfZ/hLCOI6sMYF+isUuoBbX9G0VbC9d9bc7kfr34VgDJ7Rjg5cwrYoM=", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS1PEPF0001709C.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5870", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "amd-pstate introduces a new CPU frequency control mechanism for AMD\nEPYC processors using the ACPI Collaborative Performance Power Control\nfeature for a finer grained frequency management.\n\nPatch to add support for amd-pstate driver.\n\nSigned-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>\n\nv2:\n1. error logged when scaling min freq exceeds max freq\n2. workaound in test app to allow frequency deviation of upto 50Mhz\n2. fixed indentation in release notes\n---\n app/test/test_power.c | 1 +\n app/test/test_power_cpufreq.c | 13 +-\n doc/guides/rel_notes/release_23_11.rst | 4 +\n examples/l3fwd-power/main.c | 3 +\n lib/power/meson.build | 1 +\n lib/power/power_amd_pstate_cpufreq.c | 701 +++++++++++++++++++++++++\n lib/power/power_amd_pstate_cpufreq.h | 219 ++++++++\n lib/power/rte_power.c | 26 +\n lib/power/rte_power.h | 3 +-\n lib/power/rte_power_pmd_mgmt.c | 6 +-\n 10 files changed, 973 insertions(+), 4 deletions(-)\n create mode 100644 lib/power/power_amd_pstate_cpufreq.c\n create mode 100644 lib/power/power_amd_pstate_cpufreq.h", "diff": "diff --git a/app/test/test_power.c b/app/test/test_power.c\nindex 02ebc54d19..f1e80299d3 100644\n--- a/app/test/test_power.c\n+++ b/app/test/test_power.c\n@@ -134,6 +134,7 @@ test_power(void)\n \tconst enum power_management_env envs[] = {PM_ENV_ACPI_CPUFREQ,\n \t\t\tPM_ENV_KVM_VM,\n \t\t\tPM_ENV_PSTATE_CPUFREQ,\n+\t\t\tPM_ENV_AMD_PSTATE_CPUFREQ,\n \t\t\tPM_ENV_CPPC_CPUFREQ};\n \n \tunsigned int i;\ndiff --git a/app/test/test_power_cpufreq.c b/app/test/test_power_cpufreq.c\nindex 10755a0d41..612f41c705 100644\n--- a/app/test/test_power_cpufreq.c\n+++ b/app/test/test_power_cpufreq.c\n@@ -93,6 +93,17 @@ check_cur_freq(unsigned int lcore_id, uint32_t idx, bool turbo)\n \t\t\tfreq_conv = (cur_freq + TEST_FREQ_ROUNDING_DELTA)\n \t\t\t\t\t\t/ TEST_ROUND_FREQ_TO_N_100000;\n \t\t\tfreq_conv = freq_conv * TEST_ROUND_FREQ_TO_N_100000;\n+\t\t} else if (env == PM_ENV_AMD_PSTATE_CPUFREQ) {\n+\t\t\tfreq_conv = cur_freq > freqs[idx] ? (cur_freq - freqs[idx]) :\n+\t\t\t\t\t\t\t(freqs[idx] - cur_freq);\n+\t\t\tif (freq_conv <= TEST_FREQ_ROUNDING_DELTA) {\n+\t\t\t\t/* workaround: current frequency may deviate from\n+\t\t\t\t * nominal freq. Allow deviation of upto 50Mhz\n+\t\t\t\t */\n+\t\t\t\tprintf(\"current frequency deviated from nominal \"\n+\t\t\t\t\t\"frequency by %d Khz!\\n\", freq_conv);\n+\t\t\t\tfreq_conv = freqs[idx];\n+\t\t\t}\n \t\t}\n \n \t\tif (turbo)\n@@ -502,7 +513,7 @@ test_power_cpufreq(void)\n \t/* Test environment configuration */\n \tenv = rte_power_get_env();\n \tif ((env != PM_ENV_ACPI_CPUFREQ) && (env != PM_ENV_PSTATE_CPUFREQ) &&\n-\t\t\t(env != PM_ENV_CPPC_CPUFREQ)) {\n+\t\t(env != PM_ENV_CPPC_CPUFREQ) && (env != PM_ENV_AMD_PSTATE_CPUFREQ)) {\n \t\tprintf(\"Unexpectedly got an environment other than ACPI/PSTATE\\n\");\n \t\tgoto fail_all;\n \t}\ndiff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst\nindex 9746809a66..01e17ad220 100644\n--- a/doc/guides/rel_notes/release_23_11.rst\n+++ b/doc/guides/rel_notes/release_23_11.rst\n@@ -78,6 +78,10 @@ New Features\n * build: Optional libraries can now be selected with the new ``enable_libs``\n build option similarly to the existing ``enable_drivers`` build option.\n \n+* **Added amd-pstate driver support to power management library.**\n+\n+ Added support for amd-pstate driver which works on AMD EPYC processors.\n+\n \n Removed Items\n -------------\ndiff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c\nindex 3f01cbd9e2..b9bec79cb2 100644\n--- a/examples/l3fwd-power/main.c\n+++ b/examples/l3fwd-power/main.c\n@@ -2245,6 +2245,7 @@ init_power_library(void)\n \t\tenv = rte_power_get_env();\n \t\tif (env != PM_ENV_ACPI_CPUFREQ &&\n \t\t\t\tenv != PM_ENV_PSTATE_CPUFREQ &&\n+\t\t\t\tenv != PM_ENV_AMD_PSTATE_CPUFREQ &&\n \t\t\t\tenv != PM_ENV_CPPC_CPUFREQ) {\n \t\t\tRTE_LOG(ERR, POWER,\n \t\t\t\t\"Only ACPI, PSTATE and CPPC mode are supported\\n\");\n@@ -2417,6 +2418,8 @@ autodetect_mode(void)\n \t\treturn APP_MODE_LEGACY;\n \tif (rte_power_check_env_supported(PM_ENV_PSTATE_CPUFREQ))\n \t\treturn APP_MODE_LEGACY;\n+\tif (rte_power_check_env_supported(PM_ENV_AMD_PSTATE_CPUFREQ))\n+\t\treturn APP_MODE_LEGACY;\n \tif (rte_power_check_env_supported(PM_ENV_CPPC_CPUFREQ))\n \t\treturn APP_MODE_LEGACY;\n \ndiff --git a/lib/power/meson.build b/lib/power/meson.build\nindex 1ce8b7c07d..532aa4fbd6 100644\n--- a/lib/power/meson.build\n+++ b/lib/power/meson.build\n@@ -18,6 +18,7 @@ sources = files(\n 'power_cppc_cpufreq.c',\n 'power_kvm_vm.c',\n 'power_pstate_cpufreq.c',\n+ 'power_amd_pstate_cpufreq.c',\n 'rte_power.c',\n 'rte_power_intel_uncore.c',\n 'rte_power_pmd_mgmt.c',\ndiff --git a/lib/power/power_amd_pstate_cpufreq.c b/lib/power/power_amd_pstate_cpufreq.c\nnew file mode 100644\nindex 0000000000..e0f4d99676\n--- /dev/null\n+++ b/lib/power/power_amd_pstate_cpufreq.c\n@@ -0,0 +1,701 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2021 Intel Corporation\n+ * Copyright(c) 2021 Arm Limited\n+ * Copyright(c) 2023 Amd Limited\n+ */\n+\n+#include <stdlib.h>\n+\n+#include <rte_memcpy.h>\n+\n+#include \"power_amd_pstate_cpufreq.h\"\n+#include \"power_common.h\"\n+\n+/* macros used for rounding frequency to nearest 1000 */\n+#define FREQ_ROUNDING_DELTA 500\n+#define ROUND_FREQ_TO_N_1000 1000\n+\n+#define POWER_CONVERT_TO_DECIMAL 10\n+\n+#define POWER_GOVERNOR_USERSPACE \"userspace\"\n+#define POWER_SYSFILE_SETSPEED \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_setspeed\"\n+#define POWER_SYSFILE_SCALING_MAX_FREQ \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_max_freq\"\n+#define POWER_SYSFILE_SCALING_MIN_FREQ \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_min_freq\"\n+#define POWER_SYSFILE_HIGHEST_PERF \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/acpi_cppc/highest_perf\"\n+#define POWER_SYSFILE_NOMINAL_PERF \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/acpi_cppc/nominal_perf\"\n+#define POWER_SYSFILE_NOMINAL_FREQ \\\n+\t\t\"/sys/devices/system/cpu/cpu%u/acpi_cppc/nominal_freq\"\n+\n+#define POWER_AMD_PSTATE_DRIVER \"amd-pstate\"\n+#define BUS_FREQ 1000\t/* khz */\n+\n+enum power_state {\n+\tPOWER_IDLE = 0,\n+\tPOWER_ONGOING,\n+\tPOWER_USED,\n+\tPOWER_UNKNOWN\n+};\n+\n+/**\n+ * Power info per lcore.\n+ */\n+struct amd_pstate_power_info {\n+\tuint32_t lcore_id; /**< Logical core id */\n+\tuint32_t state; /**< Power in use state */\n+\tFILE *f; /**< FD of scaling_setspeed */\n+\tchar governor_ori[28]; /**< Original governor name */\n+\tuint32_t curr_idx; /**< Freq index in freqs array */\n+\tuint32_t nom_idx; /**< Nominal index in freqs array */\n+\tuint32_t highest_perf;\t\t /**< system wide max freq */\n+\tuint32_t nominal_perf;\t\t /**< system wide nominal freq */\n+\tuint16_t turbo_available; /**< Turbo Boost available */\n+\tuint16_t turbo_enable; /**< Turbo Boost enable/disable */\n+\tuint32_t nb_freqs; /**< number of available freqs */\n+\tuint32_t freqs[RTE_MAX_LCORE_FREQS]; /**< Frequency array */\n+} __rte_cache_aligned;\n+\n+static struct amd_pstate_power_info lcore_power_info[RTE_MAX_LCORE];\n+\n+/**\n+ * It is to set specific freq for specific logical core, according to the index\n+ * of supported frequencies.\n+ */\n+static int\n+set_freq_internal(struct amd_pstate_power_info *pi, uint32_t idx)\n+{\n+\tif (idx >= RTE_MAX_LCORE_FREQS || idx >= pi->nb_freqs) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid frequency index %u, which \"\n+\t\t\t\t\"should be less than %u\\n\", idx, pi->nb_freqs);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Check if it is the same as current */\n+\tif (idx == pi->curr_idx)\n+\t\treturn 0;\n+\n+\tPOWER_DEBUG_TRACE(\"Frequency[%u] %u to be set for lcore %u\\n\",\n+\t\t\tidx, pi->freqs[idx], pi->lcore_id);\n+\tif (fseek(pi->f, 0, SEEK_SET) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Fail to set file position indicator to 0 \"\n+\t\t\t\"for setting frequency for lcore %u\\n\", pi->lcore_id);\n+\t\treturn -1;\n+\t}\n+\tif (fprintf(pi->f, \"%u\", pi->freqs[idx]) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Fail to write new frequency for \"\n+\t\t\t\t\"lcore %u\\n\", pi->lcore_id);\n+\t\treturn -1;\n+\t}\n+\tfflush(pi->f);\n+\tpi->curr_idx = idx;\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * It is to check the current scaling governor by reading sys file, and then\n+ * set it into 'userspace' if it is not by writing the sys file. The original\n+ * governor will be saved for rolling back.\n+ */\n+static int\n+power_set_governor_userspace(struct amd_pstate_power_info *pi)\n+{\n+\treturn power_set_governor(pi->lcore_id, POWER_GOVERNOR_USERSPACE,\n+\t\t\tpi->governor_ori, sizeof(pi->governor_ori));\n+}\n+\n+static int\n+power_check_turbo(struct amd_pstate_power_info *pi)\n+{\n+\tFILE *f_nom = NULL, *f_max = NULL;\n+\tint ret = -1;\n+\tuint32_t nominal_perf = 0, highest_perf = 0;\n+\n+\topen_core_sysfs_file(&f_max, \"r\", POWER_SYSFILE_HIGHEST_PERF,\n+\t\t\tpi->lcore_id);\n+\tif (f_max == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"failed to open %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_HIGHEST_PERF);\n+\t\tgoto err;\n+\t}\n+\n+\topen_core_sysfs_file(&f_nom, \"r\", POWER_SYSFILE_NOMINAL_PERF,\n+\t\t\tpi->lcore_id);\n+\tif (f_nom == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"failed to open %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_NOMINAL_PERF);\n+\t\tgoto err;\n+\t}\n+\n+\tret = read_core_sysfs_u32(f_max, &highest_perf);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Failed to read %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_HIGHEST_PERF);\n+\t\tgoto err;\n+\t}\n+\n+\tret = read_core_sysfs_u32(f_nom, &nominal_perf);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Failed to read %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_NOMINAL_PERF);\n+\t\tgoto err;\n+\t}\n+\n+\tpi->highest_perf = highest_perf;\n+\tpi->nominal_perf = nominal_perf;\n+\n+\tif (highest_perf > nominal_perf) {\n+\t\tpi->turbo_available = 1;\n+\t\tpi->turbo_enable = 1;\n+\t\tret = 0;\n+\t\tPOWER_DEBUG_TRACE(\"Lcore %u can do Turbo Boost! highest perf %u, \"\n+\t\t\t\t\"nominal perf %u\\n\",\n+\t\t\t\tpi->lcore_id, highest_perf, nominal_perf);\n+\t} else {\n+\t\tpi->turbo_available = 0;\n+\t\tpi->turbo_enable = 0;\n+\t\tPOWER_DEBUG_TRACE(\"Lcore %u Turbo not available! highest perf %u, \"\n+\t\t\t\t\"nominal perf %u\\n\",\n+\t\t\t\tpi->lcore_id, highest_perf, nominal_perf);\n+\t}\n+\n+err:\n+\tif (f_max != NULL)\n+\t\tfclose(f_max);\n+\tif (f_nom != NULL)\n+\t\tfclose(f_nom);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * It is to get the available frequencies of the specific lcore by reading the\n+ * sys file.\n+ */\n+static int\n+power_get_available_freqs(struct amd_pstate_power_info *pi)\n+{\n+\tFILE *f_min = NULL, *f_max = NULL, *f_nom = NULL;\n+\tint ret = -1, nominal_idx = -1;\n+\tuint32_t scaling_min_freq = 0, scaling_max_freq = 0;\n+\tuint32_t i, num_freqs = RTE_MAX_LCORE_FREQS;\n+\tuint32_t nominal_freq = 0, scaling_freq = 0;\n+\tuint32_t freq_calc = 0;\n+\n+\topen_core_sysfs_file(&f_max, \"r\", POWER_SYSFILE_SCALING_MAX_FREQ,\n+\t\t\tpi->lcore_id);\n+\tif (f_max == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"failed to open %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_SCALING_MAX_FREQ);\n+\t\tgoto out;\n+\t}\n+\n+\topen_core_sysfs_file(&f_min, \"r\", POWER_SYSFILE_SCALING_MIN_FREQ,\n+\t\t\tpi->lcore_id);\n+\tif (f_min == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"failed to open %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_SCALING_MIN_FREQ);\n+\t\tgoto out;\n+\t}\n+\n+\topen_core_sysfs_file(&f_nom, \"r\", POWER_SYSFILE_NOMINAL_FREQ,\n+\t\t\tpi->lcore_id);\n+\tif (f_nom == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"failed to open %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_NOMINAL_FREQ);\n+\t\tgoto out;\n+\t}\n+\n+\tret = read_core_sysfs_u32(f_max, &scaling_max_freq);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Failed to read %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_SCALING_MAX_FREQ);\n+\t\tgoto out;\n+\t}\n+\n+\tret = read_core_sysfs_u32(f_min, &scaling_min_freq);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Failed to read %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_SCALING_MIN_FREQ);\n+\t\tgoto out;\n+\t}\n+\n+\tret = read_core_sysfs_u32(f_nom, &nominal_freq);\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Failed to read %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_NOMINAL_FREQ);\n+\t\tgoto out;\n+\t}\n+\n+\tpower_check_turbo(pi);\n+\n+\tif (scaling_max_freq < scaling_min_freq) {\n+\t\tRTE_LOG(ERR, POWER, \"scaling min freq exceeds max freq, \"\n+\t\t\t\"not expected! Check system power policy\\n\");\n+\t\tgoto out;\n+\t} else if (scaling_max_freq == scaling_min_freq) {\n+\t\tnum_freqs = 1;\n+\t}\n+\n+\tif (num_freqs > 1) {\n+\t\tscaling_freq = (scaling_max_freq - scaling_min_freq);\n+\t\tscaling_freq <<= 10;\n+\t\tscaling_freq /= (num_freqs - 1);\n+\t\tscaling_freq >>= 10;\n+\t} else {\n+\t\tscaling_freq = 0;\n+\t}\n+\n+\t/* Generate the freq bucket array. */\n+\tfor (i = 0, pi->nb_freqs = 0; i < num_freqs; i++) {\n+\t\tfreq_calc = scaling_max_freq - (i * scaling_freq);\n+\t\t/* convert the frequency to nearest 1000 value\n+\t\t * Ex: if freq=1396789 then freq_conv=1397000\n+\t\t * Ex: if freq=800030 then freq_conv=800000\n+\t\t */\n+\t\tfreq_calc = (freq_calc + FREQ_ROUNDING_DELTA)\n+\t\t\t\t\t/ ROUND_FREQ_TO_N_1000;\n+\t\tfreq_calc = freq_calc * ROUND_FREQ_TO_N_1000;\n+\n+\t\t/* update the frequency table only if required */\n+\t\tif ((pi->nb_freqs == 0) ||\n+\t\t\t\tpi->freqs[pi->nb_freqs-1] != freq_calc) {\n+\t\t\tpi->freqs[pi->nb_freqs++] = freq_calc;\n+\t\t}\n+\t\tif (nominal_idx == -1) {\n+\t\t\tif ((nominal_freq * BUS_FREQ) >= freq_calc) {\n+\t\t\t\tpi->nom_idx = pi->nb_freqs - 1;\n+\t\t\t\tnominal_idx = pi->nom_idx;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tret = 0;\n+\n+\tPOWER_DEBUG_TRACE(\"%d frequency(s) of lcore %u are available\\n\",\n+\t\t\tnum_freqs, pi->lcore_id);\n+\n+out:\n+\tif (f_min != NULL)\n+\t\tfclose(f_min);\n+\tif (f_max != NULL)\n+\t\tfclose(f_max);\n+\tif (f_nom != NULL)\n+\t\tfclose(f_nom);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * It is to fopen the sys file for the future setting the lcore frequency.\n+ */\n+static int\n+power_init_for_setting_freq(struct amd_pstate_power_info *pi)\n+{\n+\tFILE *f = NULL;\n+\tchar buf[BUFSIZ];\n+\tuint32_t i, freq;\n+\tint ret;\n+\n+\topen_core_sysfs_file(&f, \"rw+\", POWER_SYSFILE_SETSPEED, pi->lcore_id);\n+\tif (f == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"failed to open %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_SETSPEED);\n+\t\tgoto err;\n+\t}\n+\n+\tret = read_core_sysfs_s(f, buf, sizeof(buf));\n+\tif (ret < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Failed to read %s\\n\",\n+\t\t\t\tPOWER_SYSFILE_SETSPEED);\n+\t\tgoto err;\n+\t}\n+\n+\tfreq = strtoul(buf, NULL, POWER_CONVERT_TO_DECIMAL);\n+\n+\t/* convert the frequency to nearest 1000 value\n+\t * Ex: if freq=1396789 then freq_conv=1397000\n+\t * Ex: if freq=800030 then freq_conv=800000\n+\t */\n+\tunsigned int freq_conv = 0;\n+\tfreq_conv = (freq + FREQ_ROUNDING_DELTA)\n+\t\t\t\t/ ROUND_FREQ_TO_N_1000;\n+\tfreq_conv = freq_conv * ROUND_FREQ_TO_N_1000;\n+\n+\tfor (i = 0; i < pi->nb_freqs; i++) {\n+\t\tif (freq_conv == pi->freqs[i]) {\n+\t\t\tpi->curr_idx = i;\n+\t\t\tpi->f = f;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+err:\n+\tif (f != NULL)\n+\t\tfclose(f);\n+\n+\treturn -1;\n+}\n+\n+int\n+power_amd_pstate_cpufreq_check_supported(void)\n+{\n+\treturn cpufreq_check_scaling_driver(POWER_AMD_PSTATE_DRIVER);\n+}\n+\n+int\n+power_amd_pstate_cpufreq_init(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\tuint32_t exp_state;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n+\t\t\t\tlcore_id, RTE_MAX_LCORE - 1U);\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\texp_state = POWER_IDLE;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are done under the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n+\t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n+\t\t\t\t\"in use\\n\", lcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\tpi->lcore_id = lcore_id;\n+\t/* Check and set the governor */\n+\tif (power_set_governor_userspace(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot set governor of lcore %u to \"\n+\t\t\t\t\"userspace\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Get the available frequencies */\n+\tif (power_get_available_freqs(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot get available frequencies of \"\n+\t\t\t\t\"lcore %u\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Init for setting lcore frequency */\n+\tif (power_init_for_setting_freq(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot init for setting frequency for \"\n+\t\t\t\t\"lcore %u\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Set freq to max by default */\n+\tif (power_amd_pstate_cpufreq_freq_max(lcore_id) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot set frequency of lcore %u \"\n+\t\t\t\t\"to max\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\tRTE_LOG(INFO, POWER, \"Initialized successfully for lcore %u \"\n+\t\t\t\"power management\\n\", lcore_id);\n+\n+\t__atomic_store_n(&(pi->state), POWER_USED, __ATOMIC_RELEASE);\n+\n+\treturn 0;\n+\n+fail:\n+\t__atomic_store_n(&(pi->state), POWER_UNKNOWN, __ATOMIC_RELEASE);\n+\treturn -1;\n+}\n+\n+/**\n+ * It is to check the governor and then set the original governor back if\n+ * needed by writing the sys file.\n+ */\n+static int\n+power_set_governor_original(struct amd_pstate_power_info *pi)\n+{\n+\treturn power_set_governor(pi->lcore_id, pi->governor_ori, NULL, 0);\n+}\n+\n+int\n+power_amd_pstate_cpufreq_exit(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\tuint32_t exp_state;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n+\t\t\t\tlcore_id, RTE_MAX_LCORE - 1U);\n+\t\treturn -1;\n+\t}\n+\tpi = &lcore_power_info[lcore_id];\n+\texp_state = POWER_USED;\n+\t/* The power in use state works as a guard variable between\n+\t * the CPU frequency control initialization and exit process.\n+\t * The ACQUIRE memory ordering here pairs with the RELEASE\n+\t * ordering below as lock to make sure the frequency operations\n+\t * in the critical section are done under the correct state.\n+\t */\n+\tif (!__atomic_compare_exchange_n(&(pi->state), &exp_state,\n+\t\t\t\t\tPOWER_ONGOING, 0,\n+\t\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n+\t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n+\t\t\t\t\"not used\\n\", lcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Close FD of setting freq */\n+\tfclose(pi->f);\n+\tpi->f = NULL;\n+\n+\t/* Set the governor back to the original */\n+\tif (power_set_governor_original(pi) < 0) {\n+\t\tRTE_LOG(ERR, POWER, \"Cannot set the governor of %u back \"\n+\t\t\t\t\"to the original\\n\", lcore_id);\n+\t\tgoto fail;\n+\t}\n+\n+\tRTE_LOG(INFO, POWER, \"Power management of lcore %u has exited from \"\n+\t\t\t\"'userspace' mode and been set back to the \"\n+\t\t\t\"original\\n\", lcore_id);\n+\t__atomic_store_n(&(pi->state), POWER_IDLE, __ATOMIC_RELEASE);\n+\n+\treturn 0;\n+\n+fail:\n+\t__atomic_store_n(&(pi->state), POWER_UNKNOWN, __ATOMIC_RELEASE);\n+\n+\treturn -1;\n+}\n+\n+uint32_t\n+power_amd_pstate_cpufreq_freqs(unsigned int lcore_id, uint32_t *freqs, uint32_t num)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tif (freqs == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"NULL buffer supplied\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tif (num < pi->nb_freqs) {\n+\t\tRTE_LOG(ERR, POWER, \"Buffer size is not enough\\n\");\n+\t\treturn 0;\n+\t}\n+\trte_memcpy(freqs, pi->freqs, pi->nb_freqs * sizeof(uint32_t));\n+\n+\treturn pi->nb_freqs;\n+}\n+\n+uint32_t\n+power_amd_pstate_cpufreq_get_freq(unsigned int lcore_id)\n+{\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn RTE_POWER_INVALID_FREQ_INDEX;\n+\t}\n+\n+\treturn lcore_power_info[lcore_id].curr_idx;\n+}\n+\n+int\n+power_amd_pstate_cpufreq_set_freq(unsigned int lcore_id, uint32_t index)\n+{\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn set_freq_internal(&(lcore_power_info[lcore_id]), index);\n+}\n+\n+int\n+power_amd_pstate_cpufreq_freq_down(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tif (pi->curr_idx + 1 == pi->nb_freqs)\n+\t\treturn 0;\n+\n+\t/* Frequencies in the array are from high to low. */\n+\treturn set_freq_internal(pi, pi->curr_idx + 1);\n+}\n+\n+int\n+power_amd_pstate_cpufreq_freq_up(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tif (pi->curr_idx == 0 || (pi->curr_idx == pi->nom_idx &&\n+\t\tpi->turbo_available && !pi->turbo_enable))\n+\t\treturn 0;\n+\n+\t/* Frequencies in the array are from high to low. */\n+\treturn set_freq_internal(pi, pi->curr_idx - 1);\n+}\n+\n+int\n+power_amd_pstate_cpufreq_freq_max(unsigned int lcore_id)\n+{\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* Frequencies in the array are from high to low. */\n+\tif (lcore_power_info[lcore_id].turbo_available) {\n+\t\tif (lcore_power_info[lcore_id].turbo_enable)\n+\t\t\t/* Set to Turbo */\n+\t\t\treturn set_freq_internal(\n+\t\t\t\t&lcore_power_info[lcore_id], 0);\n+\t\telse\n+\t\t\t/* Set to max non-turbo */\n+\t\t\treturn set_freq_internal(\n+\t\t\t\t&lcore_power_info[lcore_id],\n+\t\t\t\tlcore_power_info[lcore_id].nom_idx);\n+\t} else\n+\t\treturn set_freq_internal(&lcore_power_info[lcore_id], 0);\n+}\n+\n+int\n+power_amd_pstate_cpufreq_freq_min(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\t/* Frequencies in the array are from high to low. */\n+\treturn set_freq_internal(pi, pi->nb_freqs - 1);\n+}\n+\n+int\n+power_amd_pstate_turbo_status(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\treturn pi->turbo_enable;\n+}\n+\n+int\n+power_amd_pstate_enable_turbo(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\tif (pi->turbo_available)\n+\t\tpi->turbo_enable = 1;\n+\telse {\n+\t\tpi->turbo_enable = 0;\n+\t\tRTE_LOG(ERR, POWER,\n+\t\t\t\"Failed to enable turbo on lcore %u\\n\",\n+\t\t\tlcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\t/* TODO: must set to max once enabling Turbo? Considering add condition:\n+\t * if ((pi->turbo_available) && (pi->curr_idx <= 1))\n+\t */\n+\t/* Max may have changed, so call to max function */\n+\tif (power_amd_pstate_cpufreq_freq_max(lcore_id) < 0) {\n+\t\tRTE_LOG(ERR, POWER,\n+\t\t\t\"Failed to set frequency of lcore %u to max\\n\",\n+\t\t\tlcore_id);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+power_amd_pstate_disable_turbo(unsigned int lcore_id)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\n+\tpi->turbo_enable = 0;\n+\n+\tif ((pi->turbo_available) && (pi->curr_idx <= pi->nom_idx)) {\n+\t\t/* Try to set freq to max by default coming out of turbo */\n+\t\tif (power_amd_pstate_cpufreq_freq_max(lcore_id) < 0) {\n+\t\t\tRTE_LOG(ERR, POWER,\n+\t\t\t\t\"Failed to set frequency of lcore %u to max\\n\",\n+\t\t\t\tlcore_id);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+power_amd_pstate_get_capabilities(unsigned int lcore_id,\n+\t\tstruct rte_power_core_capabilities *caps)\n+{\n+\tstruct amd_pstate_power_info *pi;\n+\n+\tif (lcore_id >= RTE_MAX_LCORE) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n+\t\treturn -1;\n+\t}\n+\tif (caps == NULL) {\n+\t\tRTE_LOG(ERR, POWER, \"Invalid argument\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpi = &lcore_power_info[lcore_id];\n+\tcaps->capabilities = 0;\n+\tcaps->turbo = !!(pi->turbo_available);\n+\n+\treturn 0;\n+}\ndiff --git a/lib/power/power_amd_pstate_cpufreq.h b/lib/power/power_amd_pstate_cpufreq.h\nnew file mode 100644\nindex 0000000000..b02f9f98e4\n--- /dev/null\n+++ b/lib/power/power_amd_pstate_cpufreq.h\n@@ -0,0 +1,219 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2021 Intel Corporation\n+ * Copyright(c) 2021 Arm Limited\n+ * Copyright(c) 2023 Amd Limited\n+ */\n+\n+#ifndef _POWER_AMD_PSTATE_CPUFREQ_H\n+#define _POWER_AMD_PSTATE_CPUFREQ_H\n+\n+/**\n+ * @file\n+ * RTE Power Management via userspace AMD pstate cpufreq\n+ */\n+\n+#include \"rte_power.h\"\n+\n+/**\n+ * Check if amd p-state power management is supported.\n+ *\n+ * @return\n+ * - 1 if supported\n+ * - 0 if unsupported\n+ * - -1 if error, with rte_errno indicating reason for error.\n+ */\n+int power_amd_pstate_cpufreq_check_supported(void);\n+\n+/**\n+ * Initialize power management for a specific lcore. It will check and set the\n+ * governor to userspace for the lcore, get the available frequencies, and\n+ * prepare to set new lcore frequency.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 0 on success.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_cpufreq_init(unsigned int lcore_id);\n+\n+/**\n+ * Exit power management on a specific lcore. It will set the governor to which\n+ * is before initialized.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 0 on success.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_cpufreq_exit(unsigned int lcore_id);\n+\n+/**\n+ * Get the available frequencies of a specific lcore. The return value will be\n+ * the minimal one of the total number of available frequencies and the number\n+ * of buffer. The index of available frequencies used in other interfaces\n+ * should be in the range of 0 to this return value.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ * @param freqs\n+ * The buffer array to save the frequencies.\n+ * @param num\n+ * The number of frequencies to get.\n+ *\n+ * @return\n+ * The number of available frequencies.\n+ */\n+uint32_t power_amd_pstate_cpufreq_freqs(unsigned int lcore_id, uint32_t *freqs,\n+\t\tuint32_t num);\n+\n+/**\n+ * Return the current index of available frequencies of a specific lcore. It\n+ * will return 'RTE_POWER_INVALID_FREQ_INDEX = (~0)' if error.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * The current index of available frequencies.\n+ */\n+uint32_t power_amd_pstate_cpufreq_get_freq(unsigned int lcore_id);\n+\n+/**\n+ * Set the new frequency for a specific lcore by indicating the index of\n+ * available frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ * @param index\n+ * The index of available frequencies.\n+ *\n+ * @return\n+ * - 1 on success with frequency changed.\n+ * - 0 on success without frequency changed.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_cpufreq_set_freq(unsigned int lcore_id, uint32_t index);\n+\n+/**\n+ * Scale up the frequency of a specific lcore according to the available\n+ * frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 1 on success with frequency changed.\n+ * - 0 on success without frequency changed.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_cpufreq_freq_up(unsigned int lcore_id);\n+\n+/**\n+ * Scale down the frequency of a specific lcore according to the available\n+ * frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 1 on success with frequency changed.\n+ * - 0 on success without frequency changed.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_cpufreq_freq_down(unsigned int lcore_id);\n+\n+/**\n+ * Scale up the frequency of a specific lcore to the highest according to the\n+ * available frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 1 on success with frequency changed.\n+ * - 0 on success without frequency changed.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_cpufreq_freq_max(unsigned int lcore_id);\n+\n+/**\n+ * Scale down the frequency of a specific lcore to the lowest according to the\n+ * available frequencies.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 1 on success with frequency changed.\n+ * - 0 on success without frequency changed.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_cpufreq_freq_min(unsigned int lcore_id);\n+\n+/**\n+ * Get the turbo status of a specific lcore.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 1 Turbo Boost is enabled on this lcore.\n+ * - 0 Turbo Boost is disabled on this lcore.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_turbo_status(unsigned int lcore_id);\n+\n+/**\n+ * Enable Turbo Boost on a specific lcore.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 0 Turbo Boost is enabled successfully on this lcore.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_enable_turbo(unsigned int lcore_id);\n+\n+/**\n+ * Disable Turbo Boost on a specific lcore.\n+ * It should be protected outside of this function for threadsafe.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ *\n+ * @return\n+ * - 0 Turbo Boost disabled successfully on this lcore.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_disable_turbo(unsigned int lcore_id);\n+\n+/**\n+ * Returns power capabilities for a specific lcore.\n+ *\n+ * @param lcore_id\n+ * lcore id.\n+ * @param caps\n+ * pointer to rte_power_core_capabilities object.\n+ *\n+ * @return\n+ * - 0 on success.\n+ * - Negative on error.\n+ */\n+int power_amd_pstate_get_capabilities(unsigned int lcore_id,\n+\t\tstruct rte_power_core_capabilities *caps);\n+\n+#endif /* _POWER_AMD_PSTATET_CPUFREQ_H */\ndiff --git a/lib/power/rte_power.c b/lib/power/rte_power.c\nindex 63a43bd8f5..48c2e6b428 100644\n--- a/lib/power/rte_power.c\n+++ b/lib/power/rte_power.c\n@@ -12,6 +12,7 @@\n #include \"power_cppc_cpufreq.h\"\n #include \"power_kvm_vm.h\"\n #include \"power_pstate_cpufreq.h\"\n+#include \"power_amd_pstate_cpufreq.h\"\n \n enum power_management_env global_default_env = PM_ENV_NOT_SET;\n \n@@ -58,6 +59,8 @@ rte_power_check_env_supported(enum power_management_env env)\n \t\treturn power_kvm_vm_check_supported();\n \tcase PM_ENV_CPPC_CPUFREQ:\n \t\treturn power_cppc_cpufreq_check_supported();\n+\tcase PM_ENV_AMD_PSTATE_CPUFREQ:\n+\t\treturn power_amd_pstate_cpufreq_check_supported();\n \tdefault:\n \t\trte_errno = EINVAL;\n \t\treturn -1;\n@@ -126,6 +129,18 @@ rte_power_set_env(enum power_management_env env)\n \t\trte_power_freq_enable_turbo = power_cppc_enable_turbo;\n \t\trte_power_freq_disable_turbo = power_cppc_disable_turbo;\n \t\trte_power_get_capabilities = power_cppc_get_capabilities;\n+\t} else if (env == PM_ENV_AMD_PSTATE_CPUFREQ) {\n+\t\trte_power_freqs = power_amd_pstate_cpufreq_freqs;\n+\t\trte_power_get_freq = power_amd_pstate_cpufreq_get_freq;\n+\t\trte_power_set_freq = power_amd_pstate_cpufreq_set_freq;\n+\t\trte_power_freq_up = power_amd_pstate_cpufreq_freq_up;\n+\t\trte_power_freq_down = power_amd_pstate_cpufreq_freq_down;\n+\t\trte_power_freq_min = power_amd_pstate_cpufreq_freq_min;\n+\t\trte_power_freq_max = power_amd_pstate_cpufreq_freq_max;\n+\t\trte_power_turbo_status = power_amd_pstate_turbo_status;\n+\t\trte_power_freq_enable_turbo = power_amd_pstate_enable_turbo;\n+\t\trte_power_freq_disable_turbo = power_amd_pstate_disable_turbo;\n+\t\trte_power_get_capabilities = power_amd_pstate_get_capabilities;\n \t} else {\n \t\tRTE_LOG(ERR, POWER, \"Invalid Power Management Environment(%d) set\\n\",\n \t\t\t\tenv);\n@@ -171,6 +186,8 @@ rte_power_init(unsigned int lcore_id)\n \t\treturn power_pstate_cpufreq_init(lcore_id);\n \tcase PM_ENV_CPPC_CPUFREQ:\n \t\treturn power_cppc_cpufreq_init(lcore_id);\n+\tcase PM_ENV_AMD_PSTATE_CPUFREQ:\n+\t\treturn power_amd_pstate_cpufreq_init(lcore_id);\n \tdefault:\n \t\tRTE_LOG(INFO, POWER, \"Env isn't set yet!\\n\");\n \t}\n@@ -190,6 +207,13 @@ rte_power_init(unsigned int lcore_id)\n \t\tgoto out;\n \t}\n \n+\tRTE_LOG(INFO, POWER, \"Attempting to initialise AMD PSTATE power management...\\n\");\n+\tret = power_amd_pstate_cpufreq_init(lcore_id);\n+\tif (ret == 0) {\n+\t\trte_power_set_env(PM_ENV_AMD_PSTATE_CPUFREQ);\n+\t\tgoto out;\n+\t}\n+\n \tRTE_LOG(INFO, POWER, \"Attempting to initialise CPPC power management...\\n\");\n \tret = power_cppc_cpufreq_init(lcore_id);\n \tif (ret == 0) {\n@@ -221,6 +245,8 @@ rte_power_exit(unsigned int lcore_id)\n \t\treturn power_pstate_cpufreq_exit(lcore_id);\n \tcase PM_ENV_CPPC_CPUFREQ:\n \t\treturn power_cppc_cpufreq_exit(lcore_id);\n+\tcase PM_ENV_AMD_PSTATE_CPUFREQ:\n+\t\treturn power_amd_pstate_cpufreq_exit(lcore_id);\n \tdefault:\n \t\tRTE_LOG(ERR, POWER, \"Environment has not been set, unable to exit gracefully\\n\");\n \ndiff --git a/lib/power/rte_power.h b/lib/power/rte_power.h\nindex 4d70d9a8d2..e79bf1c4dd 100644\n--- a/lib/power/rte_power.h\n+++ b/lib/power/rte_power.h\n@@ -21,7 +21,8 @@ extern \"C\" {\n \n /* Power Management Environment State */\n enum power_management_env {PM_ENV_NOT_SET, PM_ENV_ACPI_CPUFREQ, PM_ENV_KVM_VM,\n-\t\tPM_ENV_PSTATE_CPUFREQ, PM_ENV_CPPC_CPUFREQ};\n+\t\tPM_ENV_PSTATE_CPUFREQ, PM_ENV_CPPC_CPUFREQ,\n+\t\tPM_ENV_AMD_PSTATE_CPUFREQ};\n \n /**\n * @warning\ndiff --git a/lib/power/rte_power_pmd_mgmt.c b/lib/power/rte_power_pmd_mgmt.c\nindex ca1840387c..3fe8ed77ba 100644\n--- a/lib/power/rte_power_pmd_mgmt.c\n+++ b/lib/power/rte_power_pmd_mgmt.c\n@@ -421,7 +421,8 @@ check_scale(unsigned int lcore)\n \n \t/* only PSTATE and ACPI modes are supported */\n \tif (!rte_power_check_env_supported(PM_ENV_ACPI_CPUFREQ) &&\n-\t !rte_power_check_env_supported(PM_ENV_PSTATE_CPUFREQ)) {\n+\t !rte_power_check_env_supported(PM_ENV_PSTATE_CPUFREQ) &&\n+\t !rte_power_check_env_supported(PM_ENV_AMD_PSTATE_CPUFREQ)) {\n \t\tRTE_LOG(DEBUG, POWER, \"Neither ACPI nor PSTATE modes are supported\\n\");\n \t\treturn -ENOTSUP;\n \t}\n@@ -431,7 +432,8 @@ check_scale(unsigned int lcore)\n \n \t/* ensure we initialized the correct env */\n \tenv = rte_power_get_env();\n-\tif (env != PM_ENV_ACPI_CPUFREQ && env != PM_ENV_PSTATE_CPUFREQ) {\n+\tif (env != PM_ENV_ACPI_CPUFREQ && env != PM_ENV_PSTATE_CPUFREQ &&\n+\t\t\tenv != PM_ENV_AMD_PSTATE_CPUFREQ) {\n \t\tRTE_LOG(DEBUG, POWER, \"Neither ACPI nor PSTATE modes were initialized\\n\");\n \t\treturn -ENOTSUP;\n \t}\n", "prefixes": [ "v2" ] }