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GET /api/patches/131861/?format=api
{ "id": 131861, "url": "https://patches.dpdk.org/api/patches/131861/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230925020921.4607-3-haifeil@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230925020921.4607-3-haifeil@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230925020921.4607-3-haifeil@nvidia.com", "date": "2023-09-25T02:09:17", "name": "[v2,2/5] common/mlx5: extend HCA attribute query for NSH", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "32c817373050b45ca73e2f63b97a0d3d4dc7f1f3", "submitter": { "id": 2131, "url": "https://patches.dpdk.org/api/people/2131/?format=api", "name": "Haifei Luo", "email": "haifeil@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230925020921.4607-3-haifeil@nvidia.com/mbox/", "series": [ { "id": 29612, "url": "https://patches.dpdk.org/api/series/29612/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29612", "date": "2023-09-25T02:09:15", "name": "support item NSH matching", "version": 2, "mbox": "https://patches.dpdk.org/series/29612/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131861/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131861/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE04E42630;\n\tMon, 25 Sep 2023 04:10:13 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1387B402D3;\n\tMon, 25 Sep 2023 04:10:06 +0200 (CEST)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2045.outbound.protection.outlook.com [40.107.243.45])\n by mails.dpdk.org (Postfix) with ESMTP id 0368F402E0\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Haifei Luo <haifeil@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<orika@nvidia.com>, <viacheslavo@nvidia.com>, <rasland@nvidia.com>,\n <xuemingl@nvidia.com>, <haifeil@nvidia.com>, Dariusz Sosnowski\n <dsosnowski@nvidia.com>, Matan Azrad <matan@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "Subject": "[PATCH v2 2/5] common/mlx5: extend HCA attribute query for NSH", "Date": "Mon, 25 Sep 2023 05:09:17 +0300", "Message-ID": "<20230925020921.4607-3-haifeil@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230925020921.4607-1-haifeil@nvidia.com>", "References": "<20230809074046.121807-1-haifeil@nvidia.com>\n <20230925020921.4607-1-haifeil@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail202.nvidia.com (10.129.68.7)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000971E4:EE_|MN0PR12MB6003:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ab755446-86ec-42ee-ed48-08dbbd6c8776", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n JkpqzWp+HmS60X9HjK6wqUejcSRQewKNNhgUbrdgDH9ogwN2OH6VJDcnx7SYs9XqD+SUVBrzMZo3tJT5r8+ZhB5j1zACClKv0jJID6quTfA1Rho1vwm2boZo3d/ufrYsfB9wZXghg+GGVBPYBd5z9Eh/25dGZW8J6GsSAXso0nXHQpfLyQU1uJN1PSz3AiN2coNgHCz5WensspSh1nXoenz+MvkiQiPruaF5tIXCnrPsAipMvh4+X3LfwZOrQFSLlSaPrveOeX0WcTiM84ue1xe9X1vfFCyGhjWRH/1ZF+m4sUxF/QchbPQL7rRfatU2dgnGnrtg+t6PrHjbRzpNUVezlxVoCEt/ORHcMhc5XpsCxVfT0+tUnmYl57xOBQ1ISauf8nci/OMlUgLTwF3Q0ZlchBA2idSy4Gjoh6nulX06yljI/5e8Yv5zYqZfGXgRAazTV1yAlIdeAY8dsClSP0eWqRH6Qv1To3UfpfEG4JiFKQZTrkkCfa5od+zJlrP8O/K/xRoKhA1Wu4PUOC5q3/FTVUMS2cbrP8l3oo4y8vJf1A86GVM1p8cKEbu0Ymi127bE4hoaKmxI36wVgsx3p6frHP42OXKNI2xylA4UZx6NxTIQfs5AdNksvwyoFrzBaH4zRIzloekkoESgCOnjLlgUIwAkMln5kA2tYSlKXpPYJD/K2FlP/OY8Kuhfof0UsVdsCSeSh3n2d+Zu6ffPGMIRgPiO9OBpR8nZP8iSMXMdzfggA5aEEyhJspGczxCL", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(396003)(376002)(39860400002)(136003)(230922051799003)(451199024)(1800799009)(186009)(82310400011)(36840700001)(46966006)(40470700004)(36860700001)(7636003)(36756003)(8936002)(41300700001)(70586007)(70206006)(86362001)(316002)(47076005)(4326008)(5660300002)(336012)(6916009)(8676002)(54906003)(83380400001)(478600001)(107886003)(356005)(16526019)(2616005)(6286002)(1076003)(26005)(40460700003)(82740400003)(426003)(6666004)(2906002)(55016003)(40480700001)(7696005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Sep 2023 02:10:02.8330 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ab755446-86ec-42ee-ed48-08dbbd6c8776", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000971E4.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB6003", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add NSH supporting field in two places:\n1. New HCA capability indicating NSH is supported\n2. New field in \"mlx5_ifc_per_protocol_networking_offload_caps_bits\"\n structure\n\nSigned-off-by: Haifei Luo <haifeil@nvidia.com>\nAcked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 4 +++-\n 3 files changed, 7 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 66a77159a0..830199212e 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1313,6 +1313,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->tunnel_stateless_gtp = MLX5_GET\n \t\t\t\t\t(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, tunnel_stateless_gtp);\n+\tattr->tunnel_stateless_vxlan_gpe_nsh = MLX5_GET\n+\t\t\t\t\t(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, tunnel_stateless_vxlan_gpe_nsh);\n \tattr->rss_ind_tbl_cap = MLX5_GET\n \t\t\t\t\t(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, rss_ind_tbl_cap);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex e071cd841f..11772431ae 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -196,6 +196,7 @@ struct mlx5_hca_attr {\n \tuint32_t tunnel_stateless_geneve_rx:1;\n \tuint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */\n \tuint32_t tunnel_stateless_gtp:1;\n+\tuint32_t tunnel_stateless_vxlan_gpe_nsh:1;\n \tuint32_t max_lso_cap;\n \tuint32_t scatter_fcs:1;\n \tuint32_t lro_cap:1;\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 51f426c614..f005877dd7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1964,7 +1964,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 swp_lso[0x1];\n \tu8 reserved_at_23[0x8];\n \tu8 tunnel_stateless_gtp[0x1];\n-\tu8 reserved_at_25[0x4];\n+\tu8 reserved_at_25[0x2];\n+\tu8 tunnel_stateless_vxlan_gpe_nsh[0x1];\n+\tu8 reserved_at_28[0x1];\n \tu8 max_vxlan_udp_ports[0x8];\n \tu8 reserved_at_38[0x6];\n \tu8 max_geneve_opt_len[0x1];\n", "prefixes": [ "v2", "2/5" ] }