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GET /api/patches/131777/?format=api
{ "id": 131777, "url": "https://patches.dpdk.org/api/patches/131777/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230921102830.2765-3-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230921102830.2765-3-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230921102830.2765-3-pbhagavatula@marvell.com", "date": "2023-09-21T10:28:29", "name": "[v3,2/3] event/cnxk: implement event link profiles", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3d93ebee1f12d8d701792fcce1067605be52bb48", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230921102830.2765-3-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 29587, "url": "https://patches.dpdk.org/api/series/29587/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29587", "date": "2023-09-21T10:28:27", "name": "Introduce event link profiles", "version": 3, "mbox": "https://patches.dpdk.org/series/29587/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131777/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131777/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BA959425FF;\n\tThu, 21 Sep 2023 12:28:55 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 73F8B40A84;\n\tThu, 21 Sep 2023 12:28:52 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 003D140A84\n for <dev@dpdk.org>; Thu, 21 Sep 2023 12:28:50 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 38L7SXc2007707; Thu, 21 Sep 2023 03:28:50 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3t85ptts67-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 21 Sep 2023 03:28:50 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 21 Sep 2023 03:28:47 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 21 Sep 2023 03:28:47 -0700", "from MININT-80QBFE8.corp.innovium.com (MININT-80QBFE8.marvell.com\n [10.28.164.106])\n by maili.marvell.com (Postfix) with ESMTP id 2382B5B693F;\n Thu, 21 Sep 2023 03:28:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=QqsrQ4kRouqAxlviMpf+wNy4ZQS9mFE1T2NNoQzlNS4=;\n b=dbnXFkNAVcGIMOXqZQ+BACKakIxq9D01uZxjTD6zSTcUgk9cbJ1qxqon5qtunCnPU01I\n sOvI0xeipV1vqYcL1u9JXSQtunoIXvJxoqCvr85m2RB+Bwup3go5ChuJ2HJVjBDXj9WT\n cPfQdamErQVFq3S6pPix3QZloAZgPN1ZeXxXFvELahSn0SEEqU/MXoS4ErRbwEsXSfaj\n hCP1GP7dU04hyvKMakgSw7ZuYDPHgnQG2ecnfzfqXjFunvHEuhY/+a1Kc4lJIb0W+543\n lwJVfUU6DhqjCf2Y6Tzlji+UUqLQduoDgeVXLQkIJvFGZ9G+GWLMBylvOdJVsEst3RvM yA==", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, <pbhagavatula@marvell.com>, <sthotton@marvell.com>,\n <timothy.mcdaniel@intel.com>, <hemant.agrawal@nxp.com>,\n <sachin.saxena@nxp.com>, <mattias.ronnblom@ericsson.com>,\n <liangma@liangbit.com>, <peter.mccarthy@intel.com>,\n <harry.van.haaren@intel.com>, <erik.g.carrillo@intel.com>,\n <abhinandan.gujjar@intel.com>, <s.v.naga.harish.k@intel.com>,\n <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v3 2/3] event/cnxk: implement event link profiles", "Date": "Thu, 21 Sep 2023 15:58:29 +0530", "Message-ID": "<20230921102830.2765-3-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230921102830.2765-1-pbhagavatula@marvell.com>", "References": "<20230831204424.13367-1-pbhagavatula@marvell.com>\n <20230921102830.2765-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "qsQvOD1J-gxwxMFu8OQBpQfZcPXW5gHI", "X-Proofpoint-ORIG-GUID": "qsQvOD1J-gxwxMFu8OQBpQfZcPXW5gHI", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26\n definitions=2023-09-21_07,2023-09-20_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nImplement event link profiles support on CN10K and CN9K.\nBoth the platforms support up to 2 link profiles.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/cnxk.rst | 1 +\n doc/guides/eventdevs/features/cnxk.ini | 3 +-\n doc/guides/rel_notes/release_23_11.rst | 5 ++\n drivers/common/cnxk/roc_nix_inl_dev.c | 4 +-\n drivers/common/cnxk/roc_sso.c | 18 +++----\n drivers/common/cnxk/roc_sso.h | 8 +--\n drivers/common/cnxk/roc_sso_priv.h | 4 +-\n drivers/event/cnxk/cn10k_eventdev.c | 45 +++++++++++-----\n drivers/event/cnxk/cn10k_worker.c | 11 ++++\n drivers/event/cnxk/cn10k_worker.h | 1 +\n drivers/event/cnxk/cn9k_eventdev.c | 74 ++++++++++++++++----------\n drivers/event/cnxk/cn9k_worker.c | 22 ++++++++\n drivers/event/cnxk/cn9k_worker.h | 2 +\n drivers/event/cnxk/cnxk_eventdev.c | 38 +++++++------\n drivers/event/cnxk/cnxk_eventdev.h | 10 ++--\n 15 files changed, 164 insertions(+), 82 deletions(-)", "diff": "diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst\nindex 1a59233282..cccb8a0304 100644\n--- a/doc/guides/eventdevs/cnxk.rst\n+++ b/doc/guides/eventdevs/cnxk.rst\n@@ -48,6 +48,7 @@ Features of the OCTEON cnxk SSO PMD are:\n - HW managed event vectorization on CN10K for packets enqueued from ethdev to\n eventdev configurable per each Rx queue in Rx adapter.\n - Event vector transmission via Tx adapter.\n+- Up to 2 event link profiles.\n \n Prerequisites and Compilation procedure\n ---------------------------------------\ndiff --git a/doc/guides/eventdevs/features/cnxk.ini b/doc/guides/eventdevs/features/cnxk.ini\nindex bee69bf8f4..5d353e3670 100644\n--- a/doc/guides/eventdevs/features/cnxk.ini\n+++ b/doc/guides/eventdevs/features/cnxk.ini\n@@ -12,7 +12,8 @@ runtime_port_link = Y\n multiple_queue_port = Y\n carry_flow_id = Y\n maintenance_free = Y\n-runtime_queue_attr = y\n+runtime_queue_attr = Y\n+profile_links = Y\n \n [Eth Rx adapter Features]\n internal_port = Y\ndiff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst\nindex e714fc2be5..69b3e4a1d8 100644\n--- a/doc/guides/rel_notes/release_23_11.rst\n+++ b/doc/guides/rel_notes/release_23_11.rst\n@@ -107,6 +107,11 @@ New Features\n \n * Added ``rte_event_port_profile_switch`` to switch between profiles as needed.\n \n+* **Added support for link profiles for Marvell CNXK event device driver.**\n+\n+ Marvell CNXK event device driver supports up to two link profiles per event\n+ port. Added support to advertise link profile capabilities and supporting APIs.\n+\n Removed Items\n -------------\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex d76158e30d..690d47c045 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -285,7 +285,7 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)\n \t}\n \n \t/* Setup hwgrp->hws link */\n-\tsso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, true);\n+\tsso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, 0, true);\n \n \t/* Enable HWGRP */\n \tplt_write64(0x1, inl_dev->sso_base + SSO_LF_GGRP_QCTL);\n@@ -315,7 +315,7 @@ nix_inl_sso_release(struct nix_inl_dev *inl_dev)\n \tnix_inl_sso_unregister_irqs(inl_dev);\n \n \t/* Unlink hws */\n-\tsso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, false);\n+\tsso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, 0, false);\n \n \t/* Release XAQ aura */\n \tsso_hwgrp_release_xaq(&inl_dev->dev, 1);\ndiff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex c37da685da..748d287bad 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -186,8 +186,8 @@ sso_rsrc_get(struct roc_sso *roc_sso)\n }\n \n void\n-sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n-\t\t uint16_t hwgrp[], uint16_t n, uint16_t enable)\n+sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, uint16_t hwgrp[],\n+\t\t uint16_t n, uint8_t set, uint16_t enable)\n {\n \tuint64_t reg;\n \tint i, j, k;\n@@ -204,7 +204,7 @@ sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n \t\tk = n % 4;\n \t\tk = k ? k : 4;\n \t\tfor (j = 0; j < k; j++) {\n-\t\t\tmask[j] = hwgrp[i + j] | enable << 14;\n+\t\t\tmask[j] = hwgrp[i + j] | (uint32_t)set << 12 | enable << 14;\n \t\t\tif (bmp) {\n \t\t\t\tenable ? plt_bitmap_set(bmp, hwgrp[i + j]) :\n \t\t\t\t\t plt_bitmap_clear(bmp, hwgrp[i + j]);\n@@ -290,8 +290,8 @@ roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns)\n }\n \n int\n-roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n-\t\t uint16_t nb_hwgrp)\n+roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp,\n+\t\t uint8_t set)\n {\n \tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n \tstruct sso *sso;\n@@ -299,14 +299,14 @@ roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n \n \tsso = roc_sso_to_sso_priv(roc_sso);\n \tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12);\n-\tsso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, 1);\n+\tsso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, set, 1);\n \n \treturn nb_hwgrp;\n }\n \n int\n-roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n-\t\t uint16_t nb_hwgrp)\n+roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp,\n+\t\t uint8_t set)\n {\n \tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n \tstruct sso *sso;\n@@ -314,7 +314,7 @@ roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n \n \tsso = roc_sso_to_sso_priv(roc_sso);\n \tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12);\n-\tsso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, 0);\n+\tsso_hws_link_modify(hws, base, sso->link_map[hws], hwgrp, nb_hwgrp, set, 0);\n \n \treturn nb_hwgrp;\n }\ndiff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h\nindex 8ee62afb9a..64f14b8119 100644\n--- a/drivers/common/cnxk/roc_sso.h\n+++ b/drivers/common/cnxk/roc_sso.h\n@@ -84,10 +84,10 @@ int __roc_api roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso,\n \t\t\t\t\t uint16_t hwgrp, uint8_t weight,\n \t\t\t\t\t uint8_t affinity, uint8_t priority);\n uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns);\n-int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws,\n-\t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n-int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws,\n-\t\t\t\t uint16_t hwgrp[], uint16_t nb_hwgrp);\n+int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n+\t\t\t uint16_t nb_hwgrp, uint8_t set);\n+int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],\n+\t\t\t\t uint16_t nb_hwgrp, uint8_t set);\n int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso,\n \t\t\t\t\t uint8_t hws, uint16_t hwgrp);\n uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws);\ndiff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h\nindex 09729d4f62..21c59c57e6 100644\n--- a/drivers/common/cnxk/roc_sso_priv.h\n+++ b/drivers/common/cnxk/roc_sso_priv.h\n@@ -44,8 +44,8 @@ roc_sso_to_sso_priv(struct roc_sso *roc_sso)\n int sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf,\n \t\t void **rsp);\n int sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf);\n-void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp,\n-\t\t\t uint16_t hwgrp[], uint16_t n, uint16_t enable);\n+void sso_hws_link_modify(uint8_t hws, uintptr_t base, struct plt_bitmap *bmp, uint16_t hwgrp[],\n+\t\t\t uint16_t n, uint8_t set, uint16_t enable);\n int sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps);\n int sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps);\n int sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex cf186b9af4..bb0c910553 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -66,21 +66,21 @@ cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)\n }\n \n static int\n-cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)\n+cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = arg;\n \tstruct cn10k_sso_hws *ws = port;\n \n-\treturn roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);\n+\treturn roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile);\n }\n \n static int\n-cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)\n+cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = arg;\n \tstruct cn10k_sso_hws *ws = port;\n \n-\treturn roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);\n+\treturn roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile);\n }\n \n static void\n@@ -107,10 +107,11 @@ cn10k_sso_hws_release(void *arg, void *hws)\n {\n \tstruct cnxk_sso_evdev *dev = arg;\n \tstruct cn10k_sso_hws *ws = hws;\n-\tuint16_t i;\n+\tuint16_t i, j;\n \n-\tfor (i = 0; i < dev->nb_event_queues; i++)\n-\t\troc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);\n+\tfor (i = 0; i < CNXK_SSO_MAX_PROFILES; i++)\n+\t\tfor (j = 0; j < dev->nb_event_queues; j++)\n+\t\t\troc_sso_hws_unlink(&dev->sso, ws->hws_id, &j, 1, i);\n \tmemset(ws, 0, sizeof(*ws));\n }\n \n@@ -482,6 +483,7 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\tCN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue, sso_hws_tx_adptr_enq);\n \n \tevent_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;\n+\tevent_dev->profile_switch = cn10k_sso_hws_profile_switch;\n #else\n \tRTE_SET_USED(event_dev);\n #endif\n@@ -633,9 +635,8 @@ cn10k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port,\n }\n \n static int\n-cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,\n-\t\t const uint8_t queues[], const uint8_t priorities[],\n-\t\t uint16_t nb_links)\n+cn10k_sso_port_link_profile(struct rte_eventdev *event_dev, void *port, const uint8_t queues[],\n+\t\t\t const uint8_t priorities[], uint16_t nb_links, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint16_t hwgrp_ids[nb_links];\n@@ -644,14 +645,14 @@ cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,\n \tRTE_SET_USED(priorities);\n \tfor (link = 0; link < nb_links; link++)\n \t\thwgrp_ids[link] = queues[link];\n-\tnb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);\n+\tnb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links, profile);\n \n \treturn (int)nb_links;\n }\n \n static int\n-cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n-\t\t uint8_t queues[], uint16_t nb_unlinks)\n+cn10k_sso_port_unlink_profile(struct rte_eventdev *event_dev, void *port, uint8_t queues[],\n+\t\t\t uint16_t nb_unlinks, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint16_t hwgrp_ids[nb_unlinks];\n@@ -659,11 +660,25 @@ cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n \n \tfor (unlink = 0; unlink < nb_unlinks; unlink++)\n \t\thwgrp_ids[unlink] = queues[unlink];\n-\tnb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);\n+\tnb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks, profile);\n \n \treturn (int)nb_unlinks;\n }\n \n+static int\n+cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port, const uint8_t queues[],\n+\t\t const uint8_t priorities[], uint16_t nb_links)\n+{\n+\treturn cn10k_sso_port_link_profile(event_dev, port, queues, priorities, nb_links, 0);\n+}\n+\n+static int\n+cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, uint8_t queues[],\n+\t\t uint16_t nb_unlinks)\n+{\n+\treturn cn10k_sso_port_unlink_profile(event_dev, port, queues, nb_unlinks, 0);\n+}\n+\n static void\n cn10k_sso_configure_queue_stash(struct rte_eventdev *event_dev)\n {\n@@ -1020,6 +1035,8 @@ static struct eventdev_ops cn10k_sso_dev_ops = {\n \t.port_quiesce = cn10k_sso_port_quiesce,\n \t.port_link = cn10k_sso_port_link,\n \t.port_unlink = cn10k_sso_port_unlink,\n+\t.port_link_profile = cn10k_sso_port_link_profile,\n+\t.port_unlink_profile = cn10k_sso_port_unlink_profile,\n \t.timeout_ticks = cnxk_sso_timeout_ticks,\n \n \t.eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,\ndiff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c\nindex 9b5bf90159..d59769717e 100644\n--- a/drivers/event/cnxk/cn10k_worker.c\n+++ b/drivers/event/cnxk/cn10k_worker.c\n@@ -431,3 +431,14 @@ cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \n \treturn 1;\n }\n+\n+int __rte_hot\n+cn10k_sso_hws_profile_switch(void *port, uint8_t profile)\n+{\n+\tstruct cn10k_sso_hws *ws = port;\n+\n+\tws->gw_wdata &= ~(0xFFUL);\n+\tws->gw_wdata |= (profile + 1);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex e71ab3c523..26fecf21fb 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -329,6 +329,7 @@ uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,\n uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,\n \t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t uint16_t nb_events);\n+int __rte_hot cn10k_sso_hws_profile_switch(void *port, uint8_t profile);\n \n #define R(name, flags) \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex fe6f5d9f86..9fb9ca0d63 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -15,7 +15,7 @@\n \tenq_op = enq_ops[dev->tx_offloads & (NIX_TX_OFFLOAD_MAX - 1)]\n \n static int\n-cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)\n+cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = arg;\n \tstruct cn9k_sso_hws_dual *dws;\n@@ -24,22 +24,20 @@ cn9k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)\n \n \tif (dev->dual_ws) {\n \t\tdws = port;\n-\t\trc = roc_sso_hws_link(&dev->sso,\n-\t\t\t\t CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,\n-\t\t\t\t nb_link);\n-\t\trc |= roc_sso_hws_link(&dev->sso,\n-\t\t\t\t CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),\n-\t\t\t\t map, nb_link);\n+\t\trc = roc_sso_hws_link(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map, nb_link,\n+\t\t\t\t profile);\n+\t\trc |= roc_sso_hws_link(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), map,\n+\t\t\t\t nb_link, profile);\n \t} else {\n \t\tws = port;\n-\t\trc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);\n+\t\trc = roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link, profile);\n \t}\n \n \treturn rc;\n }\n \n static int\n-cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)\n+cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = arg;\n \tstruct cn9k_sso_hws_dual *dws;\n@@ -48,15 +46,13 @@ cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)\n \n \tif (dev->dual_ws) {\n \t\tdws = port;\n-\t\trc = roc_sso_hws_unlink(&dev->sso,\n-\t\t\t\t\tCN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),\n-\t\t\t\t\tmap, nb_link);\n-\t\trc |= roc_sso_hws_unlink(&dev->sso,\n-\t\t\t\t\t CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),\n-\t\t\t\t\t map, nb_link);\n+\t\trc = roc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), map,\n+\t\t\t\t\tnb_link, profile);\n+\t\trc |= roc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), map,\n+\t\t\t\t\t nb_link, profile);\n \t} else {\n \t\tws = port;\n-\t\trc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);\n+\t\trc = roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link, profile);\n \t}\n \n \treturn rc;\n@@ -97,21 +93,24 @@ cn9k_sso_hws_release(void *arg, void *hws)\n \tstruct cnxk_sso_evdev *dev = arg;\n \tstruct cn9k_sso_hws_dual *dws;\n \tstruct cn9k_sso_hws *ws;\n-\tuint16_t i;\n+\tuint16_t i, k;\n \n \tif (dev->dual_ws) {\n \t\tdws = hws;\n \t\tfor (i = 0; i < dev->nb_event_queues; i++) {\n-\t\t\troc_sso_hws_unlink(&dev->sso,\n-\t\t\t\t\t CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0), &i, 1);\n-\t\t\troc_sso_hws_unlink(&dev->sso,\n-\t\t\t\t\t CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1), &i, 1);\n+\t\t\tfor (k = 0; k < CNXK_SSO_MAX_PROFILES; k++) {\n+\t\t\t\troc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 0),\n+\t\t\t\t\t\t &i, 1, k);\n+\t\t\t\troc_sso_hws_unlink(&dev->sso, CN9K_DUAL_WS_PAIR_ID(dws->hws_id, 1),\n+\t\t\t\t\t\t &i, 1, k);\n+\t\t\t}\n \t\t}\n \t\tmemset(dws, 0, sizeof(*dws));\n \t} else {\n \t\tws = hws;\n \t\tfor (i = 0; i < dev->nb_event_queues; i++)\n-\t\t\troc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1);\n+\t\t\tfor (k = 0; k < CNXK_SSO_MAX_PROFILES; k++)\n+\t\t\t\troc_sso_hws_unlink(&dev->sso, ws->hws_id, &i, 1, k);\n \t\tmemset(ws, 0, sizeof(*ws));\n \t}\n }\n@@ -438,6 +437,7 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \tevent_dev->enqueue_burst = cn9k_sso_hws_enq_burst;\n \tevent_dev->enqueue_new_burst = cn9k_sso_hws_enq_new_burst;\n \tevent_dev->enqueue_forward_burst = cn9k_sso_hws_enq_fwd_burst;\n+\tevent_dev->profile_switch = cn9k_sso_hws_profile_switch;\n \tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n \t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq_seg);\n \t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,\n@@ -475,6 +475,7 @@ cn9k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\tevent_dev->enqueue_forward_burst =\n \t\t\tcn9k_sso_hws_dual_enq_fwd_burst;\n \t\tevent_dev->ca_enqueue = cn9k_sso_hws_dual_ca_enq;\n+\t\tevent_dev->profile_switch = cn9k_sso_hws_dual_profile_switch;\n \n \t\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n \t\t\tCN9K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,\n@@ -708,9 +709,8 @@ cn9k_sso_port_quiesce(struct rte_eventdev *event_dev, void *port,\n }\n \n static int\n-cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,\n-\t\t const uint8_t queues[], const uint8_t priorities[],\n-\t\t uint16_t nb_links)\n+cn9k_sso_port_link_profile(struct rte_eventdev *event_dev, void *port, const uint8_t queues[],\n+\t\t\t const uint8_t priorities[], uint16_t nb_links, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint16_t hwgrp_ids[nb_links];\n@@ -719,14 +719,14 @@ cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port,\n \tRTE_SET_USED(priorities);\n \tfor (link = 0; link < nb_links; link++)\n \t\thwgrp_ids[link] = queues[link];\n-\tnb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links);\n+\tnb_links = cn9k_sso_hws_link(dev, port, hwgrp_ids, nb_links, profile);\n \n \treturn (int)nb_links;\n }\n \n static int\n-cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n-\t\t uint8_t queues[], uint16_t nb_unlinks)\n+cn9k_sso_port_unlink_profile(struct rte_eventdev *event_dev, void *port, uint8_t queues[],\n+\t\t\t uint16_t nb_unlinks, uint8_t profile)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint16_t hwgrp_ids[nb_unlinks];\n@@ -734,11 +734,25 @@ cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n \n \tfor (unlink = 0; unlink < nb_unlinks; unlink++)\n \t\thwgrp_ids[unlink] = queues[unlink];\n-\tnb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);\n+\tnb_unlinks = cn9k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks, profile);\n \n \treturn (int)nb_unlinks;\n }\n \n+static int\n+cn9k_sso_port_link(struct rte_eventdev *event_dev, void *port, const uint8_t queues[],\n+\t\t const uint8_t priorities[], uint16_t nb_links)\n+{\n+\treturn cn9k_sso_port_link_profile(event_dev, port, queues, priorities, nb_links, 0);\n+}\n+\n+static int\n+cn9k_sso_port_unlink(struct rte_eventdev *event_dev, void *port, uint8_t queues[],\n+\t\t uint16_t nb_unlinks)\n+{\n+\treturn cn9k_sso_port_unlink_profile(event_dev, port, queues, nb_unlinks, 0);\n+}\n+\n static int\n cn9k_sso_start(struct rte_eventdev *event_dev)\n {\n@@ -1019,6 +1033,8 @@ static struct eventdev_ops cn9k_sso_dev_ops = {\n \t.port_quiesce = cn9k_sso_port_quiesce,\n \t.port_link = cn9k_sso_port_link,\n \t.port_unlink = cn9k_sso_port_unlink,\n+\t.port_link_profile = cn9k_sso_port_link_profile,\n+\t.port_unlink_profile = cn9k_sso_port_unlink_profile,\n \t.timeout_ticks = cnxk_sso_timeout_ticks,\n \n \t.eth_rx_adapter_caps_get = cn9k_sso_rx_adapter_caps_get,\ndiff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c\nindex abbbfffd85..a9ac49a5a7 100644\n--- a/drivers/event/cnxk/cn9k_worker.c\n+++ b/drivers/event/cnxk/cn9k_worker.c\n@@ -66,6 +66,17 @@ cn9k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \treturn 1;\n }\n \n+int __rte_hot\n+cn9k_sso_hws_profile_switch(void *port, uint8_t profile)\n+{\n+\tstruct cn9k_sso_hws *ws = port;\n+\n+\tws->gw_wdata &= ~(0xFFUL);\n+\tws->gw_wdata |= (profile + 1);\n+\n+\treturn 0;\n+}\n+\n /* Dual ws ops. */\n \n uint16_t __rte_hot\n@@ -149,3 +160,14 @@ cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n \treturn cn9k_cpt_crypto_adapter_enqueue(dws->base[!dws->vws],\n \t\t\t\t\t ev->event_ptr);\n }\n+\n+int __rte_hot\n+cn9k_sso_hws_dual_profile_switch(void *port, uint8_t profile)\n+{\n+\tstruct cn9k_sso_hws_dual *dws = port;\n+\n+\tdws->gw_wdata &= ~(0xFFUL);\n+\tdws->gw_wdata |= (profile + 1);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h\nindex ee659e80d6..6936b7ad04 100644\n--- a/drivers/event/cnxk/cn9k_worker.h\n+++ b/drivers/event/cnxk/cn9k_worker.h\n@@ -366,6 +366,7 @@ uint16_t __rte_hot cn9k_sso_hws_enq_new_burst(void *port,\n uint16_t __rte_hot cn9k_sso_hws_enq_fwd_burst(void *port,\n \t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t uint16_t nb_events);\n+int __rte_hot cn9k_sso_hws_profile_switch(void *port, uint8_t profile);\n \n uint16_t __rte_hot cn9k_sso_hws_dual_enq(void *port,\n \t\t\t\t\t const struct rte_event *ev);\n@@ -382,6 +383,7 @@ uint16_t __rte_hot cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[],\n \t\t\t\t uint16_t nb_events);\n uint16_t __rte_hot cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[],\n \t\t\t\t\t uint16_t nb_events);\n+int __rte_hot cn9k_sso_hws_dual_profile_switch(void *port, uint8_t profile);\n \n #define R(name, flags) \\\n \tuint16_t __rte_hot cn9k_sso_hws_deq_##name( \\\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c\nindex f3394a20b1..0c61f4c20e 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.c\n+++ b/drivers/event/cnxk/cnxk_eventdev.c\n@@ -30,8 +30,9 @@ cnxk_sso_info_get(struct cnxk_sso_evdev *dev,\n \t\t\t\t RTE_EVENT_DEV_CAP_NONSEQ_MODE |\n \t\t\t\t RTE_EVENT_DEV_CAP_CARRY_FLOW_ID |\n \t\t\t\t RTE_EVENT_DEV_CAP_MAINTENANCE_FREE |\n-\t\t\t\t RTE_EVENT_DEV_CAP_RUNTIME_QUEUE_ATTR;\n-\tdev_info->max_profiles_per_port = 1;\n+\t\t\t\t RTE_EVENT_DEV_CAP_RUNTIME_QUEUE_ATTR |\n+\t\t\t\t RTE_EVENT_DEV_CAP_PROFILE_LINK;\n+\tdev_info->max_profiles_per_port = CNXK_SSO_MAX_PROFILES;\n }\n \n int\n@@ -129,23 +130,25 @@ cnxk_sso_restore_links(const struct rte_eventdev *event_dev,\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint16_t *links_map, hwgrp[CNXK_SSO_MAX_HWGRP];\n-\tint i, j;\n+\tint i, j, k;\n \n \tfor (i = 0; i < dev->nb_event_ports; i++) {\n-\t\tuint16_t nb_hwgrp = 0;\n-\n-\t\tlinks_map = event_dev->data->links_map[0];\n-\t\t/* Point links_map to this port specific area */\n-\t\tlinks_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);\n+\t\tfor (k = 0; k < CNXK_SSO_MAX_PROFILES; k++) {\n+\t\t\tuint16_t nb_hwgrp = 0;\n+\n+\t\t\tlinks_map = event_dev->data->links_map[k];\n+\t\t\t/* Point links_map to this port specific area */\n+\t\t\tlinks_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);\n+\n+\t\t\tfor (j = 0; j < dev->nb_event_queues; j++) {\n+\t\t\t\tif (links_map[j] == 0xdead)\n+\t\t\t\t\tcontinue;\n+\t\t\t\thwgrp[nb_hwgrp] = j;\n+\t\t\t\tnb_hwgrp++;\n+\t\t\t}\n \n-\t\tfor (j = 0; j < dev->nb_event_queues; j++) {\n-\t\t\tif (links_map[j] == 0xdead)\n-\t\t\t\tcontinue;\n-\t\t\thwgrp[nb_hwgrp] = j;\n-\t\t\tnb_hwgrp++;\n+\t\t\tlink_fn(dev, event_dev->data->ports[i], hwgrp, nb_hwgrp, k);\n \t\t}\n-\n-\t\tlink_fn(dev, event_dev->data->ports[i], hwgrp, nb_hwgrp);\n \t}\n }\n \n@@ -436,7 +439,7 @@ cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn)\n {\n \tstruct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);\n \tuint16_t all_queues[CNXK_SSO_MAX_HWGRP];\n-\tuint16_t i;\n+\tuint16_t i, j;\n \tvoid *ws;\n \n \tif (!dev->configured)\n@@ -447,7 +450,8 @@ cnxk_sso_close(struct rte_eventdev *event_dev, cnxk_sso_unlink_t unlink_fn)\n \n \tfor (i = 0; i < dev->nb_event_ports; i++) {\n \t\tws = event_dev->data->ports[i];\n-\t\tunlink_fn(dev, ws, all_queues, dev->nb_event_queues);\n+\t\tfor (j = 0; j < CNXK_SSO_MAX_PROFILES; j++)\n+\t\t\tunlink_fn(dev, ws, all_queues, dev->nb_event_queues, j);\n \t\trte_free(cnxk_sso_hws_get_cookie(ws));\n \t\tevent_dev->data->ports[i] = NULL;\n \t}\ndiff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h\nindex bd50de87c0..d42d1afa1a 100644\n--- a/drivers/event/cnxk/cnxk_eventdev.h\n+++ b/drivers/event/cnxk/cnxk_eventdev.h\n@@ -33,6 +33,8 @@\n #define CN10K_SSO_GW_MODE \"gw_mode\"\n #define CN10K_SSO_STASH\t \"stash\"\n \n+#define CNXK_SSO_MAX_PROFILES 2\n+\n #define NSEC2USEC(__ns)\t\t((__ns) / 1E3)\n #define USEC2NSEC(__us)\t\t((__us)*1E3)\n #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)\n@@ -57,10 +59,10 @@\n typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);\n typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t grp_base);\n typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);\n-typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map,\n-\t\t\t uint16_t nb_link);\n-typedef int (*cnxk_sso_unlink_t)(void *dev, void *ws, uint16_t *map,\n-\t\t\t\t uint16_t nb_link);\n+typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map, uint16_t nb_link,\n+\t\t\t uint8_t profile);\n+typedef int (*cnxk_sso_unlink_t)(void *dev, void *ws, uint16_t *map, uint16_t nb_link,\n+\t\t\t\t uint8_t profile);\n typedef void (*cnxk_handle_event_t)(void *arg, struct rte_event ev);\n typedef void (*cnxk_sso_hws_reset_t)(void *arg, void *ws);\n typedef int (*cnxk_sso_hws_flush_t)(void *ws, uint8_t queue_id, uintptr_t base,\n", "prefixes": [ "v3", "2/3" ] }