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GET /api/patches/131665/?format=api
{ "id": 131665, "url": "https://patches.dpdk.org/api/patches/131665/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230920062236.375308-9-simei.su@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230920062236.375308-9-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230920062236.375308-9-simei.su@intel.com", "date": "2023-09-20T06:22:33", "name": "[v5,08/11] common/idpf/base: refine code and alignments", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "27a48f550125cf39276c6101ceca0ddd53ec1aec", "submitter": { "id": 1298, "url": "https://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230920062236.375308-9-simei.su@intel.com/mbox/", "series": [ { "id": 29562, "url": "https://patches.dpdk.org/api/series/29562/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29562", "date": "2023-09-20T06:22:25", "name": "update idpf base code", "version": 5, "mbox": "https://patches.dpdk.org/series/29562/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131665/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131665/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 243BC425E9;\n\tWed, 20 Sep 2023 08:23:10 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A8E8440E2D;\n\tWed, 20 Sep 2023 08:22:37 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id BFC7A40DFD\n for <dev@dpdk.org>; Wed, 20 Sep 2023 08:22:35 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Sep 2023 23:22:35 -0700", "from dpdk-simei-icelake.sh.intel.com ([10.67.110.167])\n by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:32 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695190955; x=1726726955;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=2YADc4NirdxRm8Nym/PH3jVe9h4hmbfH8HqDCLfJqVA=;\n b=ZXLmo5Z30xbBVRrDTJE23wbzz9kq3/QdKORpLnxIgQTDwYxvMTTzFftl\n bgs+7V4QkleNOwx3OmncNag6RCwQsMJlSvjWDveMCenBo/NDduHcR5PCk\n taLc4QNcCl6AxxGCS6ztWWuIdcy8AG3c2vEkQYWCcObLlQCXPzswhaBGG\n AB9sgZJs7JLqX5HpQ5ZTsDqhSq2EDqRSxsA4c9aA5zp077MxnI5f65ndm\n 70iFh46XTLFYAZ0GSvcbh+qXIMwTdxkSjIoYQGMm9kBXBvNepQGMozYee\n Y4zecRy+Yu8waP0uofBBrg0vqrKQl4Fft1HBIjf7DCIryDON91tUCCVd+ A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10838\"; a=\"466453269\"", "E=Sophos;i=\"6.02,161,1688454000\"; d=\"scan'208\";a=\"466453269\"", "E=McAfee;i=\"6600,9927,10838\"; a=\"920154732\"", "E=Sophos;i=\"6.02,161,1688454000\"; d=\"scan'208\";a=\"920154732\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com,\n wenjing.qiao@intel.com, Simei Su <simei.su@intel.com>,\n Pavan Kumar Linga <pavan.kumar.linga@intel.com>", "Subject": "[PATCH v5 08/11] common/idpf/base: refine code and alignments", "Date": "Wed, 20 Sep 2023 14:22:33 +0800", "Message-Id": "<20230920062236.375308-9-simei.su@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230920062236.375308-1-simei.su@intel.com>", "References": "<20230918021130.192982-1-simei.su@intel.com>\n <20230920062236.375308-1-simei.su@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "a) Refine double pointer with a local pointer.\nb) Refine return type for function instead of only returning success.\nc) Remove unnecessary check and comments.\nd) Use tab spaces and new lines wherever necessary.\n\nSigned-off-by: Pavan Kumar Linga <pavan.kumar.linga@intel.com>\nSigned-off-by: Simei Su <simei.su@intel.com>\nAcked-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/base/idpf_common.c | 4 +-\n drivers/common/idpf/base/idpf_controlq.c | 64 +++++++++----------\n drivers/common/idpf/base/idpf_controlq_api.h | 12 +---\n .../common/idpf/base/idpf_controlq_setup.c | 5 +-\n drivers/common/idpf/base/idpf_lan_pf_regs.h | 7 +-\n drivers/common/idpf/base/idpf_lan_txrx.h | 46 ++++++-------\n drivers/common/idpf/base/idpf_lan_vf_regs.h | 25 +++++---\n drivers/common/idpf/base/idpf_prototype.h | 2 +-\n 8 files changed, 80 insertions(+), 85 deletions(-)", "diff": "diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c\nindex 9610916aa9..7181a7f14c 100644\n--- a/drivers/common/idpf/base/idpf_common.c\n+++ b/drivers/common/idpf/base/idpf_common.c\n@@ -262,12 +262,12 @@ int idpf_clean_arq_element(struct idpf_hw *hw,\n * idpf_deinit_hw - shutdown routine\n * @hw: pointer to the hardware structure\n */\n-int idpf_deinit_hw(struct idpf_hw *hw)\n+void idpf_deinit_hw(struct idpf_hw *hw)\n {\n \thw->asq = NULL;\n \thw->arq = NULL;\n \n-\treturn idpf_ctlq_deinit(hw);\n+\tidpf_ctlq_deinit(hw);\n }\n \n /**\ndiff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c\nindex 6815153e1d..a82ca628de 100644\n--- a/drivers/common/idpf/base/idpf_controlq.c\n+++ b/drivers/common/idpf/base/idpf_controlq.c\n@@ -9,11 +9,10 @@\n * @cq: pointer to the specific control queue\n * @q_create_info: structs containing info for each queue to be initialized\n */\n-static void\n-idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq,\n-\t\t struct idpf_ctlq_create_info *q_create_info)\n+static void idpf_ctlq_setup_regs(struct idpf_ctlq_info *cq,\n+\t\t\t\t struct idpf_ctlq_create_info *q_create_info)\n {\n-\t/* set head and tail registers in our local struct */\n+\t/* set control queue registers in our local struct */\n \tcq->reg.head = q_create_info->reg.head;\n \tcq->reg.tail = q_create_info->reg.tail;\n \tcq->reg.len = q_create_info->reg.len;\n@@ -75,7 +74,7 @@ static void idpf_ctlq_init_rxq_bufs(struct idpf_ctlq_info *cq)\n \t\tdesc->flags =\n \t\t\tCPU_TO_LE16(IDPF_CTLQ_FLAG_BUF | IDPF_CTLQ_FLAG_RD);\n \t\tdesc->opcode = 0;\n-\t\tdesc->datalen = (__le16)CPU_TO_LE16(bi->size);\n+\t\tdesc->datalen = CPU_TO_LE16(bi->size);\n \t\tdesc->ret_val = 0;\n \t\tdesc->cookie_high = 0;\n \t\tdesc->cookie_low = 0;\n@@ -137,6 +136,7 @@ int idpf_ctlq_add(struct idpf_hw *hw,\n \t\t struct idpf_ctlq_create_info *qinfo,\n \t\t struct idpf_ctlq_info **cq_out)\n {\n+\tstruct idpf_ctlq_info *cq;\n \tbool is_rxq = false;\n \tint status = 0;\n \n@@ -145,26 +145,26 @@ int idpf_ctlq_add(struct idpf_hw *hw,\n \t qinfo->buf_size > IDPF_CTLQ_MAX_BUF_LEN)\n \t\treturn -EINVAL;\n \n-\t*cq_out = (struct idpf_ctlq_info *)\n-\t\tidpf_calloc(hw, 1, sizeof(struct idpf_ctlq_info));\n-\tif (!(*cq_out))\n+\tcq = (struct idpf_ctlq_info *)\n+\t idpf_calloc(hw, 1, sizeof(struct idpf_ctlq_info));\n+\tif (!cq)\n \t\treturn -ENOMEM;\n \n-\t(*cq_out)->cq_type = qinfo->type;\n-\t(*cq_out)->q_id = qinfo->id;\n-\t(*cq_out)->buf_size = qinfo->buf_size;\n-\t(*cq_out)->ring_size = qinfo->len;\n+\tcq->cq_type = qinfo->type;\n+\tcq->q_id = qinfo->id;\n+\tcq->buf_size = qinfo->buf_size;\n+\tcq->ring_size = qinfo->len;\n \n-\t(*cq_out)->next_to_use = 0;\n-\t(*cq_out)->next_to_clean = 0;\n-\t(*cq_out)->next_to_post = (*cq_out)->ring_size - 1;\n+\tcq->next_to_use = 0;\n+\tcq->next_to_clean = 0;\n+\tcq->next_to_post = cq->ring_size - 1;\n \n \tswitch (qinfo->type) {\n \tcase IDPF_CTLQ_TYPE_MAILBOX_RX:\n \t\tis_rxq = true;\n \t\t/* fallthrough */\n \tcase IDPF_CTLQ_TYPE_MAILBOX_TX:\n-\t\tstatus = idpf_ctlq_alloc_ring_res(hw, *cq_out);\n+\t\tstatus = idpf_ctlq_alloc_ring_res(hw, cq);\n \t\tbreak;\n \tdefault:\n \t\tstatus = -EINVAL;\n@@ -175,33 +175,35 @@ int idpf_ctlq_add(struct idpf_hw *hw,\n \t\tgoto init_free_q;\n \n \tif (is_rxq) {\n-\t\tidpf_ctlq_init_rxq_bufs(*cq_out);\n+\t\tidpf_ctlq_init_rxq_bufs(cq);\n \t} else {\n \t\t/* Allocate the array of msg pointers for TX queues */\n-\t\t(*cq_out)->bi.tx_msg = (struct idpf_ctlq_msg **)\n+\t\tcq->bi.tx_msg = (struct idpf_ctlq_msg **)\n \t\t\tidpf_calloc(hw, qinfo->len,\n \t\t\t\t sizeof(struct idpf_ctlq_msg *));\n-\t\tif (!(*cq_out)->bi.tx_msg) {\n+\t\tif (!cq->bi.tx_msg) {\n \t\t\tstatus = -ENOMEM;\n \t\t\tgoto init_dealloc_q_mem;\n \t\t}\n \t}\n \n-\tidpf_ctlq_setup_regs(*cq_out, qinfo);\n+\tidpf_ctlq_setup_regs(cq, qinfo);\n \n-\tidpf_ctlq_init_regs(hw, *cq_out, is_rxq);\n+\tidpf_ctlq_init_regs(hw, cq, is_rxq);\n \n-\tidpf_init_lock(&(*cq_out)->cq_lock);\n+\tidpf_init_lock(&(cq->cq_lock));\n \n-\tLIST_INSERT_HEAD(&hw->cq_list_head, (*cq_out), cq_list);\n+\tLIST_INSERT_HEAD(&hw->cq_list_head, cq, cq_list);\n \n+\t*cq_out = cq;\n \treturn status;\n \n init_dealloc_q_mem:\n \t/* free ring buffers and the ring itself */\n-\tidpf_ctlq_dealloc_ring_res(hw, *cq_out);\n+\tidpf_ctlq_dealloc_ring_res(hw, cq);\n init_free_q:\n-\tidpf_free(hw, *cq_out);\n+\tidpf_free(hw, cq);\n+\tcq = NULL;\n \n \treturn status;\n }\n@@ -261,16 +263,13 @@ int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q,\n * idpf_ctlq_deinit - destroy all control queues\n * @hw: pointer to hw struct\n */\n-int idpf_ctlq_deinit(struct idpf_hw *hw)\n+void idpf_ctlq_deinit(struct idpf_hw *hw)\n {\n \tstruct idpf_ctlq_info *cq = NULL, *tmp = NULL;\n-\tint ret_code = 0;\n \n \tLIST_FOR_EACH_ENTRY_SAFE(cq, tmp, &hw->cq_list_head,\n \t\t\t\t idpf_ctlq_info, cq_list)\n \t\tidpf_ctlq_remove(hw, cq);\n-\n-\treturn ret_code;\n }\n \n /**\n@@ -426,11 +425,8 @@ static int __idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,\n \t\tif (!force && !(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD))\n \t\t\tbreak;\n \n-\t\tdesc_err = LE16_TO_CPU(desc->ret_val);\n-\t\tif (desc_err) {\n-\t\t\t/* strip off FW internal code */\n-\t\t\tdesc_err &= 0xff;\n-\t\t}\n+\t\t/* strip off FW internal code */\n+\t\tdesc_err = LE16_TO_CPU(desc->ret_val) & 0xff;\n \n \t\tmsg_status[i] = cq->bi.tx_msg[ntc];\n \t\tif (!msg_status[i])\ndiff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h\nindex f4e7b53ac9..38f5d2df3c 100644\n--- a/drivers/common/idpf/base/idpf_controlq_api.h\n+++ b/drivers/common/idpf/base/idpf_controlq_api.h\n@@ -21,10 +21,7 @@ enum idpf_ctlq_type {\n \tIDPF_CTLQ_TYPE_RDMA_COMPL\t= 7\n };\n \n-/*\n- * Generic Control Queue Structures\n- */\n-\n+/* Generic Control Queue Structures */\n struct idpf_ctlq_reg {\n \t/* used for queue tracking */\n \tu32 head;\n@@ -157,10 +154,7 @@ enum idpf_mbx_opc {\n \tidpf_mbq_opc_send_msg_to_peer_drv\t= 0x0804,\n };\n \n-/*\n- * API supported for control queue management\n- */\n-\n+/* API supported for control queue management */\n /* Will init all required q including default mb. \"q_info\" is an array of\n * create_info structs equal to the number of control queues to be created.\n */\n@@ -205,6 +199,6 @@ int idpf_ctlq_post_rx_buffs(struct idpf_hw *hw,\n \t\t\t struct idpf_dma_mem **buffs);\n \n /* Will destroy all q including the default mb */\n-int idpf_ctlq_deinit(struct idpf_hw *hw);\n+void idpf_ctlq_deinit(struct idpf_hw *hw);\n \n #endif /* _IDPF_CONTROLQ_API_H_ */\ndiff --git a/drivers/common/idpf/base/idpf_controlq_setup.c b/drivers/common/idpf/base/idpf_controlq_setup.c\nindex 0f1b52a7e9..21f43c74f5 100644\n--- a/drivers/common/idpf/base/idpf_controlq_setup.c\n+++ b/drivers/common/idpf/base/idpf_controlq_setup.c\n@@ -11,9 +11,8 @@\n * @hw: pointer to hw struct\n * @cq: pointer to the specific Control queue\n */\n-static int\n-idpf_ctlq_alloc_desc_ring(struct idpf_hw *hw,\n-\t\t\t struct idpf_ctlq_info *cq)\n+static int idpf_ctlq_alloc_desc_ring(struct idpf_hw *hw,\n+\t\t\t\t struct idpf_ctlq_info *cq)\n {\n \tsize_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc);\n \ndiff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h\nindex 8542620e01..eab23f279a 100644\n--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h\n@@ -80,10 +80,11 @@\n /* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is\n * spacing b/w itrn registers of the same vector.\n */\n-#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n-\t\t((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing)\t\\\n+\t((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))\n /* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */\n-#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n+#define PF_GLINT_ITR(_ITR, _INT)\t\\\n+\t(PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))\n #define PF_GLINT_ITR_MAX_INDEX\t\t2\n #define PF_GLINT_ITR_INTERVAL_S\t\t0\n #define PF_GLINT_ITR_INTERVAL_M\t\tIDPF_M(0xFFF, PF_GLINT_ITR_INTERVAL_S)\ndiff --git a/drivers/common/idpf/base/idpf_lan_txrx.h b/drivers/common/idpf/base/idpf_lan_txrx.h\nindex 7b03693eb1..aec6422c15 100644\n--- a/drivers/common/idpf/base/idpf_lan_txrx.h\n+++ b/drivers/common/idpf/base/idpf_lan_txrx.h\n@@ -8,9 +8,9 @@\n #include \"idpf_osdep.h\"\n \n enum idpf_rss_hash {\n-\t/* Values 0 - 28 are reserved for future use */\n-\tIDPF_HASH_INVALID\t\t= 0,\n-\tIDPF_HASH_NONF_UNICAST_IPV4_UDP\t= 29,\n+\tIDPF_HASH_INVALID\t\t\t= 0,\n+\t/* Values 1 - 28 are reserved for future use */\n+\tIDPF_HASH_NONF_UNICAST_IPV4_UDP\t\t= 29,\n \tIDPF_HASH_NONF_MULTICAST_IPV4_UDP,\n \tIDPF_HASH_NONF_IPV4_UDP,\n \tIDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK,\n@@ -19,7 +19,7 @@ enum idpf_rss_hash {\n \tIDPF_HASH_NONF_IPV4_OTHER,\n \tIDPF_HASH_FRAG_IPV4,\n \t/* Values 37-38 are reserved */\n-\tIDPF_HASH_NONF_UNICAST_IPV6_UDP\t= 39,\n+\tIDPF_HASH_NONF_UNICAST_IPV6_UDP\t\t= 39,\n \tIDPF_HASH_NONF_MULTICAST_IPV6_UDP,\n \tIDPF_HASH_NONF_IPV6_UDP,\n \tIDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK,\n@@ -32,34 +32,30 @@ enum idpf_rss_hash {\n \tIDPF_HASH_NONF_FCOE_RX,\n \tIDPF_HASH_NONF_FCOE_OTHER,\n \t/* Values 51-62 are reserved */\n-\tIDPF_HASH_L2_PAYLOAD\t\t= 63,\n+\tIDPF_HASH_L2_PAYLOAD\t\t\t= 63,\n \tIDPF_HASH_MAX\n };\n \n /* Supported RSS offloads */\n-#define IDPF_DEFAULT_RSS_HASH ( \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) | \\\n-\tBIT_ULL(IDPF_HASH_FRAG_IPV4) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) | \\\n-\tBIT_ULL(IDPF_HASH_FRAG_IPV6) | \\\n+#define IDPF_DEFAULT_RSS_HASH\t\t\t\\\n+\t(BIT_ULL(IDPF_HASH_NONF_IPV4_UDP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_SCTP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_OTHER) |\t\\\n+\tBIT_ULL(IDPF_HASH_FRAG_IPV4) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_UDP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_SCTP) |\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_OTHER) |\t\\\n+\tBIT_ULL(IDPF_HASH_FRAG_IPV6) |\t\t\\\n \tBIT_ULL(IDPF_HASH_L2_PAYLOAD))\n \n-\t/* TODO: Wrap below comment under internal flag\n-\t * Below 6 pcktypes are not supported by FVL or older products\n-\t * They are supported by FPK and future products\n-\t */\n #define IDPF_DEFAULT_RSS_HASH_EXPANDED (IDPF_DEFAULT_RSS_HASH | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) | \\\n-\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) | \\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV4_TCP_SYN_NO_ACK) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV4_UDP) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV4_UDP) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_IPV6_TCP_SYN_NO_ACK) |\t\t\\\n+\tBIT_ULL(IDPF_HASH_NONF_UNICAST_IPV6_UDP) |\t\t\\\n \tBIT_ULL(IDPF_HASH_NONF_MULTICAST_IPV6_UDP))\n \n /* For idpf_splitq_base_tx_compl_desc */\ndiff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h\nindex b5ff9b2cc9..2caa07fdfd 100644\n--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h\n+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h\n@@ -94,14 +94,23 @@\n * b/w itrn registers of the same vector\n */\n #define VF_INT_ITR0(_ITR)\t\t(0x00004C00 + ((_ITR) * 4))\n-#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \\\n-\t\t ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))\n-/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */\n-#define VF_INT_ITRN(_INT, _ITR)\t(0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))\n-/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */\n-#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))\n-/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */\n-#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing)\t\\\n+\t((_reg_start) + ((_ITR) * (_itrn_indx_spacing)))\n+/* For VF with 16 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing\n+ * is 0x40 and base register offset is 0x00002800\n+ */\n+#define VF_INT_ITRN(_INT, _ITR)\t\t\\\n+\t(0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))\n+/* For VF with 64 vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing\n+ * is 0x100 and base register offset is 0x00002C00\n+ */\n+#define VF_INT_ITRN_64(_INT, _ITR)\t\\\n+\t(0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))\n+/* For VF with 2k vector support, itrn_reg_spacing is 0x4, itrn_indx_spacing\n+ * is 0x2000 and base register offset is 0x00072000\n+ */\n+#define VF_INT_ITRN_2K(_INT, _ITR)\t\\\n+\t(0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))\n #define VF_INT_ITRN_MAX_INDEX\t\t2\n #define VF_INT_ITRN_INTERVAL_S\t\t0\n #define VF_INT_ITRN_INTERVAL_M\t\tIDPF_M(0xFFF, VF_INT_ITRN_INTERVAL_S)\ndiff --git a/drivers/common/idpf/base/idpf_prototype.h b/drivers/common/idpf/base/idpf_prototype.h\nindex 988ff00506..e2f090a9e3 100644\n--- a/drivers/common/idpf/base/idpf_prototype.h\n+++ b/drivers/common/idpf/base/idpf_prototype.h\n@@ -20,7 +20,7 @@\n #define APF\n \n int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size ctlq_size);\n-int idpf_deinit_hw(struct idpf_hw *hw);\n+void idpf_deinit_hw(struct idpf_hw *hw);\n \n int idpf_clean_arq_element(struct idpf_hw *hw,\n \t\t\t struct idpf_arq_event_info *e,\n", "prefixes": [ "v5", "08/11" ] }