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GET /api/patches/131662/?format=api
{ "id": 131662, "url": "https://patches.dpdk.org/api/patches/131662/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230920062236.375308-6-simei.su@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230920062236.375308-6-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230920062236.375308-6-simei.su@intel.com", "date": "2023-09-20T06:22:30", "name": "[v5,05/11] common/idpf/base: remove mailbox registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "25537d50079677fab8a3893deaabe70f6e22d060", "submitter": { "id": 1298, "url": "https://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230920062236.375308-6-simei.su@intel.com/mbox/", "series": [ { "id": 29562, "url": "https://patches.dpdk.org/api/series/29562/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29562", "date": "2023-09-20T06:22:25", "name": "update idpf base code", "version": 5, "mbox": "https://patches.dpdk.org/series/29562/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131662/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131662/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 85332425E9;\n\tWed, 20 Sep 2023 08:22:50 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2367940A8A;\n\tWed, 20 Sep 2023 08:22:28 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.43])\n by mails.dpdk.org (Postfix) with ESMTP id 3D52240A79\n for <dev@dpdk.org>; Wed, 20 Sep 2023 08:22:27 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 Sep 2023 23:22:26 -0700", "from dpdk-simei-icelake.sh.intel.com ([10.67.110.167])\n by orsmga005.jf.intel.com with ESMTP; 19 Sep 2023 23:22:24 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695190947; x=1726726947;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=+Wh15aWIk/wzfgF29k4NXHSyOqacjwu1IeVkW3v0Muo=;\n b=dB10+CLhjm34vRhAS1vyn+6+QSotIZPm/Sq2/h8JjRWucPWr0SL8Td4M\n avQ+Dh41eWnX4aFDtZixjVcxazswUHXr5WDakOHJh4flsJfshWtPls4kA\n SklhtI0Erxd2HO4hC5KqbisMc9V5/xnLatzd2bEkjTOYW5ZPBN4dIlREw\n iGtOWNimtLD6nm+MbEFJNjQq++qeGnW7zaL5lpM6qYodvfzMg+2nZNq9c\n LnljHXSWq1ryTIj5ncxgAsNHkazFC/y1iKbCVZQM0M+8kfGApQxUea2lj\n eGI1OiFkx49aYyNgI1efTaoYoeFOJ/xhSWmSeLnWJTMCF1Tq+txyibnqu g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10838\"; a=\"466453251\"", "E=Sophos;i=\"6.02,161,1688454000\"; d=\"scan'208\";a=\"466453251\"", "E=McAfee;i=\"6600,9927,10838\"; a=\"920154629\"", "E=Sophos;i=\"6.02,161,1688454000\"; d=\"scan'208\";a=\"920154629\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org, wenjun1.wu@intel.com, mingxia.liu@intel.com,\n wenjing.qiao@intel.com, Simei Su <simei.su@intel.com>,\n Madhu Chittim <madhu.chittim@intel.com>", "Subject": "[PATCH v5 05/11] common/idpf/base: remove mailbox registers", "Date": "Wed, 20 Sep 2023 14:22:30 +0800", "Message-Id": "<20230920062236.375308-6-simei.su@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230920062236.375308-1-simei.su@intel.com>", "References": "<20230918021130.192982-1-simei.su@intel.com>\n <20230920062236.375308-1-simei.su@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Remove mailbox register offsets because individual drivers will define\nthe offsets based on how registers address the registers.\n\nSigned-off-by: Madhu Chittim <madhu.chittim@intel.com>\nSigned-off-by: Simei Su <simei.su@intel.com>\nAcked-by: Beilei Xing <beilei.xing@intel.com>\n---\n .mailmap | 1 +\n drivers/common/idpf/base/siov_regs.h | 13 ++-----------\n 2 files changed, 3 insertions(+), 11 deletions(-)", "diff": "diff --git a/.mailmap b/.mailmap\nindex 91d8cca78f..d8782cd67e 100644\n--- a/.mailmap\n+++ b/.mailmap\n@@ -1642,3 +1642,4 @@ Zyta Szpak <zyta@marvell.com> <zr@semihalf.com> <zyta.szpak@semihalf.com>\n Jayaprakash Shanmugam <jayaprakash.shanmugam@intel.com>\n Zhenning Xiao <zhenning.xiao@intel.com>\n Josh Hay <joshua.a.hay@intel.com>\n+Madhu Chittim <madhu.chittim@intel.com>\ndiff --git a/drivers/common/idpf/base/siov_regs.h b/drivers/common/idpf/base/siov_regs.h\nindex fad329601a..7e1ae2e300 100644\n--- a/drivers/common/idpf/base/siov_regs.h\n+++ b/drivers/common/idpf/base/siov_regs.h\n@@ -4,16 +4,6 @@\n #ifndef _SIOV_REGS_H_\n #define _SIOV_REGS_H_\n #define VDEV_MBX_START\t\t\t0x20000 /* Begin at 128KB */\n-#define VDEV_MBX_ATQBAL\t\t\t(VDEV_MBX_START + 0x0000)\n-#define VDEV_MBX_ATQBAH\t\t\t(VDEV_MBX_START + 0x0004)\n-#define VDEV_MBX_ATQLEN\t\t\t(VDEV_MBX_START + 0x0008)\n-#define VDEV_MBX_ATQH\t\t\t(VDEV_MBX_START + 0x000C)\n-#define VDEV_MBX_ATQT\t\t\t(VDEV_MBX_START + 0x0010)\n-#define VDEV_MBX_ARQBAL\t\t\t(VDEV_MBX_START + 0x0014)\n-#define VDEV_MBX_ARQBAH\t\t\t(VDEV_MBX_START + 0x0018)\n-#define VDEV_MBX_ARQLEN\t\t\t(VDEV_MBX_START + 0x001C)\n-#define VDEV_MBX_ARQH\t\t\t(VDEV_MBX_START + 0x0020)\n-#define VDEV_MBX_ARQT\t\t\t(VDEV_MBX_START + 0x0024)\n #define VDEV_GET_RSTAT\t\t\t0x21000 /* 132KB for RSTAT */\n \n /* Begin at offset after 1MB (after 256 4k pages) */\n@@ -43,5 +33,6 @@\n #define VDEV_INT_ITR_1(_i)\t\t(VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x08)\n #define VDEV_INT_ITR_2(_i)\t\t(VDEV_INT_DYN_START + ((_i) * 0x1000) + 0x0C)\n \n-/* Next offset to begin at 42MB (0x2A00000) */\n+#define SIOV_REG_BAR_SIZE 0x2A00000\n+/* Next offset to begin at 42MB + 4K (0x2A00000 + 0x1000) */\n #endif /* _SIOV_REGS_H_ */\n", "prefixes": [ "v5", "05/11" ] }