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GET /api/patches/131584/?format=api
{ "id": 131584, "url": "https://patches.dpdk.org/api/patches/131584/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230919012136.2818396-5-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230919012136.2818396-5-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230919012136.2818396-5-nicolas.chautru@intel.com", "date": "2023-09-19T01:21:33", "name": "[v1,4/7] baseband/acc: allocate FCW memory separately", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6e0bb9bb3b01d8441b2cf6005363fe26378a65d2", "submitter": { "id": 1314, "url": "https://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "https://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230919012136.2818396-5-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 29539, "url": "https://patches.dpdk.org/api/series/29539/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29539", "date": "2023-09-19T01:21:29", "name": "VRB2 BBDEV PMD introduction", "version": 1, "mbox": "https://patches.dpdk.org/series/29539/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131584/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131584/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9676D425F2;\n\tTue, 19 Sep 2023 03:25:24 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2CEA0402D2;\n\tTue, 19 Sep 2023 03:25:00 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id DD0F740275\n for <dev@dpdk.org>; Tue, 19 Sep 2023 03:24:55 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Sep 2023 18:24:53 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by orsmga002.jf.intel.com with ESMTP; 18 Sep 2023 18:24:53 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1695086696; x=1726622696;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=BVscYISFx+kOCMZxfY4+M5WUvOV/qIFDblUTSu+ML/Y=;\n b=nUuYFyUP9LysnbQ0fqk1PP4ofnChjsoqfzJikbyfmalSFroKhV78tMAF\n UNAN2sMZb3eCXjRSt3Mfceob4nhmTA6zjxsrWihniRYHmiR8K7FndxNqB\n steXjnc8+8toP1LHfqWgzn3TvJj57PgQhki3pJhrRhDW9MYOT8/Gfovac\n RaM5e9nTU1b5PkPR2eAEjufBSDCLXVAis2KVC5b//FuTkqtLU4bdOzubJ\n BZETQ3xtuD94aESBpl269VbVVgmjwhESB6UPAvx3hVqcpnDkC2k4lqAlO\n os1VLYrUXJ9ugZzM5boF1b0mPfRbUH/IyI8KCRRd46oy4FCcFIrwRdv6r A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10837\"; a=\"360078100\"", "E=Sophos;i=\"6.02,158,1688454000\"; d=\"scan'208\";a=\"360078100\"", "E=McAfee;i=\"6600,9927,10837\"; a=\"746039453\"", "E=Sophos;i=\"6.02,158,1688454000\"; d=\"scan'208\";a=\"746039453\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v1 4/7] baseband/acc: allocate FCW memory separately", "Date": "Tue, 19 Sep 2023 01:21:33 +0000", "Message-Id": "<20230919012136.2818396-5-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230919012136.2818396-1-nicolas.chautru@intel.com>", "References": "<20230919012136.2818396-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This allows more flexibility to the FCW size for the\nunified driver. No actual functional change.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/acc_common.h | 4 +++-\n drivers/baseband/acc/rte_vrb_pmd.c | 25 ++++++++++++++++++++++++-\n 2 files changed, 27 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/acc_common.h b/drivers/baseband/acc/acc_common.h\nindex df18506e75..b5ee113faf 100644\n--- a/drivers/baseband/acc/acc_common.h\n+++ b/drivers/baseband/acc/acc_common.h\n@@ -101,6 +101,7 @@\n #define ACC_NUM_QGRPS_PER_WORD 8\n #define ACC_MAX_NUM_QGRPS 32\n #define ACC_RING_SIZE_GRANULARITY 64\n+#define ACC_MAX_FCW_SIZE 128\n \n /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */\n #define ACC_N_ZC_1 66 /* N = 66 Zc for BG 1 */\n@@ -582,13 +583,14 @@ struct __rte_cache_aligned acc_queue {\n \tuint32_t aq_enqueued; /* Count how many \"batches\" have been enqueued */\n \tuint32_t aq_dequeued; /* Count how many \"batches\" have been dequeued */\n \tuint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */\n-\tstruct rte_mempool *fcw_mempool; /* FCW mempool */\n \tenum rte_bbdev_op_type op_type; /* Type of this Queue: TE or TD */\n \t/* Internal Buffers for loopback input */\n \tuint8_t *lb_in;\n \tuint8_t *lb_out;\n+\tuint8_t *fcw_ring;\n \trte_iova_t lb_in_addr_iova;\n \trte_iova_t lb_out_addr_iova;\n+\trte_iova_t fcw_ring_addr_iova;\n \tint8_t *derm_buffer; /* interim buffer for de-rm in SDK */\n \tstruct acc_device *d;\n };\ndiff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex e0f50460bd..78f465b25b 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -883,6 +883,25 @@ vrb_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,\n \t\tgoto free_companion_ring_addr;\n \t}\n \n+\tq->fcw_ring = rte_zmalloc_socket(dev->device->driver->name,\n+\t\t\tACC_MAX_FCW_SIZE * d->sw_ring_max_depth,\n+\t\t\tRTE_CACHE_LINE_SIZE, conf->socket);\n+\tif (q->fcw_ring == NULL) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate fcw_ring memory\");\n+\t\tret = -ENOMEM;\n+\t\tgoto free_companion_ring_addr;\n+\t}\n+\tq->fcw_ring_addr_iova = rte_malloc_virt2iova(q->fcw_ring);\n+\n+\t/* For FFT we need to store the FCW separately */\n+\tif (conf->op_type == RTE_BBDEV_OP_FFT) {\n+\t\tfor (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) {\n+\t\t\tdesc = q->ring_addr + desc_idx;\n+\t\t\tdesc->req.data_ptrs[0].address = q->fcw_ring_addr_iova +\n+\t\t\t\t\tdesc_idx * ACC_MAX_FCW_SIZE;\n+\t\t}\n+\t}\n+\n \tq->qgrp_id = (q_idx >> VRB1_GRP_ID_SHIFT) & 0xF;\n \tq->vf_id = (q_idx >> VRB1_VF_ID_SHIFT) & 0x3F;\n \tq->aq_id = q_idx & 0xF;\n@@ -994,6 +1013,7 @@ vrb_queue_release(struct rte_bbdev *dev, uint16_t q_id)\n \tif (q != NULL) {\n \t\t/* Mark the Queue as un-assigned. */\n \t\td->q_assigned_bit_map[q->qgrp_id] &= (~0ULL - (1 << (uint64_t) q->aq_id));\n+\t\trte_free(q->fcw_ring);\n \t\trte_free(q->companion_ring_addr);\n \t\trte_free(q->lb_in);\n \t\trte_free(q->lb_out);\n@@ -3225,7 +3245,10 @@ vrb_enqueue_fft_one_op(struct acc_queue *q, struct rte_bbdev_fft_op *op,\n \toutput = op->fft.base_output.data;\n \tin_offset = op->fft.base_input.offset;\n \tout_offset = op->fft.base_output.offset;\n-\tfcw = &desc->req.fcw_fft;\n+\n+\tfcw = (struct acc_fcw_fft *) (q->fcw_ring +\n+\t\t\t((q->sw_ring_head + total_enqueued_cbs) & q->sw_ring_wrap_mask)\n+\t\t\t* ACC_MAX_FCW_SIZE);\n \n \tvrb1_fcw_fft_fill(op, fcw);\n \tvrb1_dma_desc_fft_fill(op, &desc->req, input, output, &in_offset, &out_offset);\n", "prefixes": [ "v1", "4/7" ] }