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GET /api/patches/131405/?format=api
{ "id": 131405, "url": "https://patches.dpdk.org/api/patches/131405/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230914015031.2560501-2-simei.su@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230914015031.2560501-2-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230914015031.2560501-2-simei.su@intel.com", "date": "2023-09-14T01:50:29", "name": "[v4,1/3] common/idpf: refactor single queue Tx data path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c1a56066aa7d102ca971bd965a2269e364166521", "submitter": { "id": 1298, "url": "https://patches.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230914015031.2560501-2-simei.su@intel.com/mbox/", "series": [ { "id": 29501, "url": "https://patches.dpdk.org/api/series/29501/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29501", "date": "2023-09-14T01:50:28", "name": "refactor single queue Tx data path", "version": 4, "mbox": "https://patches.dpdk.org/series/29501/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131405/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/131405/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5A22D4258F;\n\tThu, 14 Sep 2023 03:49:53 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E4B03402E4;\n\tThu, 14 Sep 2023 03:49:50 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 464AE4026B\n for <dev@dpdk.org>; Thu, 14 Sep 2023 03:49:46 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Sep 2023 18:49:45 -0700", "from dpdk-simei-icelake.sh.intel.com ([10.67.110.167])\n by orsmga008.jf.intel.com with ESMTP; 13 Sep 2023 18:49:42 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1694656187; x=1726192187;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=pcKpgbKcARUGcN+v4pP/2MQLjkoF1HRp03sQEaFv/Qk=;\n b=FrPwqHET6jZAm0lVa1VmVOniBOt1hIsk69hJYD0kXxkxHKMOPvmPXCWF\n iHgj5NOvBT4xcERvffr/BHP/7O/3Sv1LtqSqWK1mmP1RBIKIJ/WQ7fqXM\n j2fzjLM6amSqtB2dIP1hUAEhcPDiwMvx5Xsg15u8gkDWDIsx+R4d1iRPO\n ZTVbEzY4ZrSvAp/8zo7ZOCcpI5ClhWdn7nbQz4Q6iPw+MVLq0F2goTPuS\n XAiIjs6h/8Yo50mNFkD0uNc+AxcKjWq1LVmBR5EtyrBQY0DKCmdysNueT\n BXVTBfAxfN5SIr9I4hkShJWM8Dnh7NN3gvv7tIVSAPsyAqcMMh0st4M1B A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10832\"; a=\"369101403\"", "E=Sophos;i=\"6.02,144,1688454000\"; d=\"scan'208\";a=\"369101403\"", "E=McAfee;i=\"6600,9927,10832\"; a=\"773699521\"", "E=Sophos;i=\"6.02,144,1688454000\"; d=\"scan'208\";a=\"773699521\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "jingjing.wu@intel.com,\n\tbeilei.xing@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org,\n\twenjun1.wu@intel.com,\n\tSimei Su <simei.su@intel.com>", "Subject": "[PATCH v4 1/3] common/idpf: refactor single queue Tx data path", "Date": "Thu, 14 Sep 2023 09:50:29 +0800", "Message-Id": "<20230914015031.2560501-2-simei.su@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230914015031.2560501-1-simei.su@intel.com>", "References": "<20230908102827.2256297-1-simei.su@intel.com>\n <20230914015031.2560501-1-simei.su@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Currently, single queue Tx data path uses flex Tx data descriptor\nwhich is changed in the latest idpf spec. This patch replaces flex\nTx data descriptor with base Tx data descriptor for single queue Tx\ndata path.\n\nSigned-off-by: Simei Su <simei.su@intel.com>\nAcked-by: Wenjun Wu <wenjun1.wu@intel.com>\n---\n drivers/common/idpf/idpf_common_rxtx.c | 39 +++++++++----------\n drivers/common/idpf/idpf_common_rxtx.h | 2 +-\n drivers/common/idpf/idpf_common_rxtx_avx512.c | 37 +++++++++---------\n 3 files changed, 38 insertions(+), 40 deletions(-)", "diff": "diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c\nindex fc87e3e243..e6d2486272 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.c\n+++ b/drivers/common/idpf/idpf_common_rxtx.c\n@@ -276,14 +276,14 @@ idpf_qc_single_tx_queue_reset(struct idpf_tx_queue *txq)\n \t}\n \n \ttxe = txq->sw_ring;\n-\tsize = sizeof(struct idpf_flex_tx_desc) * txq->nb_tx_desc;\n+\tsize = sizeof(struct idpf_base_tx_desc) * txq->nb_tx_desc;\n \tfor (i = 0; i < size; i++)\n \t\t((volatile char *)txq->tx_ring)[i] = 0;\n \n \tprev = (uint16_t)(txq->nb_tx_desc - 1);\n \tfor (i = 0; i < txq->nb_tx_desc; i++) {\n-\t\ttxq->tx_ring[i].qw1.cmd_dtype =\n-\t\t\trte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_DESC_DONE);\n+\t\ttxq->tx_ring[i].qw1 =\n+\t\t\trte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE);\n \t\ttxe[i].mbuf = NULL;\n \t\ttxe[i].last_id = i;\n \t\ttxe[prev].next_id = i;\n@@ -1307,17 +1307,16 @@ idpf_xmit_cleanup(struct idpf_tx_queue *txq)\n \tuint16_t nb_tx_to_clean;\n \tuint16_t i;\n \n-\tvolatile struct idpf_flex_tx_desc *txd = txq->tx_ring;\n+\tvolatile struct idpf_base_tx_desc *txd = txq->tx_ring;\n \n \tdesc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);\n \tif (desc_to_clean_to >= nb_tx_desc)\n \t\tdesc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);\n \n \tdesc_to_clean_to = sw_ring[desc_to_clean_to].last_id;\n-\t/* In the writeback Tx desccriptor, the only significant fields are the 4-bit DTYPE */\n-\tif ((txd[desc_to_clean_to].qw1.cmd_dtype &\n-\t rte_cpu_to_le_16(IDPF_TXD_QW1_DTYPE_M)) !=\n-\t rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_DESC_DONE)) {\n+\tif ((txd[desc_to_clean_to].qw1 &\n+\t rte_cpu_to_le_64(IDPF_TXD_QW1_DTYPE_M)) !=\n+\t rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE)) {\n \t\tTX_LOG(DEBUG, \"TX descriptor %4u is not done \"\n \t\t \"(port=%d queue=%d)\", desc_to_clean_to,\n \t\t txq->port_id, txq->queue_id);\n@@ -1331,10 +1330,7 @@ idpf_xmit_cleanup(struct idpf_tx_queue *txq)\n \t\tnb_tx_to_clean = (uint16_t)(desc_to_clean_to -\n \t\t\t\t\t last_desc_cleaned);\n \n-\ttxd[desc_to_clean_to].qw1.cmd_dtype = 0;\n-\ttxd[desc_to_clean_to].qw1.buf_size = 0;\n-\tfor (i = 0; i < RTE_DIM(txd[desc_to_clean_to].qw1.flex.raw); i++)\n-\t\ttxd[desc_to_clean_to].qw1.flex.raw[i] = 0;\n+\ttxd[desc_to_clean_to].qw1 = 0;\n \n \ttxq->last_desc_cleaned = desc_to_clean_to;\n \ttxq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);\n@@ -1347,8 +1343,8 @@ uint16_t\n idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts)\n {\n-\tvolatile struct idpf_flex_tx_desc *txd;\n-\tvolatile struct idpf_flex_tx_desc *txr;\n+\tvolatile struct idpf_base_tx_desc *txd;\n+\tvolatile struct idpf_base_tx_desc *txr;\n \tunion idpf_tx_offload tx_offload = {0};\n \tstruct idpf_tx_entry *txe, *txn;\n \tstruct idpf_tx_entry *sw_ring;\n@@ -1356,6 +1352,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tstruct rte_mbuf *tx_pkt;\n \tstruct rte_mbuf *m_seg;\n \tuint64_t buf_dma_addr;\n+\tuint32_t td_offset;\n \tuint64_t ol_flags;\n \tuint16_t tx_last;\n \tuint16_t nb_used;\n@@ -1382,6 +1379,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \n \tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n \t\ttd_cmd = 0;\n+\t\ttd_offset = 0;\n \n \t\ttx_pkt = *tx_pkts++;\n \t\tRTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);\n@@ -1462,9 +1460,10 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\tslen = m_seg->data_len;\n \t\t\tbuf_dma_addr = rte_mbuf_data_iova(m_seg);\n \t\t\ttxd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);\n-\t\t\ttxd->qw1.buf_size = slen;\n-\t\t\ttxd->qw1.cmd_dtype = rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_FLEX_DATA <<\n-\t\t\t\t\t\t\t IDPF_FLEX_TXD_QW1_DTYPE_S);\n+\t\t\ttxd->qw1 = rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DATA |\n+\t\t\t\t((uint64_t)td_cmd << IDPF_TXD_QW1_CMD_S) |\n+\t\t\t\t((uint64_t)td_offset << IDPF_TXD_QW1_OFFSET_S) |\n+\t\t\t\t((uint64_t)slen << IDPF_TXD_QW1_TX_BUF_SZ_S));\n \n \t\t\ttxe->last_id = tx_last;\n \t\t\ttx_id = txe->next_id;\n@@ -1473,7 +1472,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t} while (m_seg);\n \n \t\t/* The last packet data descriptor needs End Of Packet (EOP) */\n-\t\ttd_cmd |= IDPF_TX_FLEX_DESC_CMD_EOP;\n+\t\ttd_cmd |= IDPF_TX_DESC_CMD_EOP;\n \t\ttxq->nb_used = (uint16_t)(txq->nb_used + nb_used);\n \t\ttxq->nb_free = (uint16_t)(txq->nb_free - nb_used);\n \n@@ -1482,7 +1481,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t \"%4u (port=%d queue=%d)\",\n \t\t\t tx_last, txq->port_id, txq->queue_id);\n \n-\t\t\ttd_cmd |= IDPF_TX_FLEX_DESC_CMD_RS;\n+\t\t\ttd_cmd |= IDPF_TX_DESC_CMD_RS;\n \n \t\t\t/* Update txq RS bit counters */\n \t\t\ttxq->nb_used = 0;\n@@ -1491,7 +1490,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tif (ol_flags & IDPF_TX_CKSUM_OFFLOAD_MASK)\n \t\t\ttd_cmd |= IDPF_TX_FLEX_DESC_CMD_CS_EN;\n \n-\t\ttxd->qw1.cmd_dtype |= rte_cpu_to_le_16(td_cmd << IDPF_FLEX_TXD_QW1_CMD_S);\n+\t\ttxd->qw1 |= rte_cpu_to_le_16(td_cmd << IDPF_TXD_QW1_CMD_S);\n \t}\n \n end_of_tx:\ndiff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h\nindex 6cb83fc0a6..b49b1ed737 100644\n--- a/drivers/common/idpf/idpf_common_rxtx.h\n+++ b/drivers/common/idpf/idpf_common_rxtx.h\n@@ -157,7 +157,7 @@ struct idpf_tx_entry {\n /* Structure associated with each TX queue. */\n struct idpf_tx_queue {\n \tconst struct rte_memzone *mz;\t\t/* memzone for Tx ring */\n-\tvolatile struct idpf_flex_tx_desc *tx_ring;\t/* Tx ring virtual address */\n+\tvolatile struct idpf_base_tx_desc *tx_ring;\t/* Tx ring virtual address */\n \tvolatile union {\n \t\tstruct idpf_flex_tx_sched_desc *desc_ring;\n \t\tstruct idpf_splitq_tx_compl_desc *compl_ring;\ndiff --git a/drivers/common/idpf/idpf_common_rxtx_avx512.c b/drivers/common/idpf/idpf_common_rxtx_avx512.c\nindex 2ac46fb1d2..f65e8d512b 100644\n--- a/drivers/common/idpf/idpf_common_rxtx_avx512.c\n+++ b/drivers/common/idpf/idpf_common_rxtx_avx512.c\n@@ -1005,7 +1005,7 @@ idpf_tx_singleq_free_bufs_avx512(struct idpf_tx_queue *txq)\n \tstruct rte_mbuf *m, *free[txq->rs_thresh];\n \n \t/* check DD bits on threshold descriptor */\n-\tif ((txq->tx_ring[txq->next_dd].qw1.cmd_dtype &\n+\tif ((txq->tx_ring[txq->next_dd].qw1 &\n \t\t\trte_cpu_to_le_64(IDPF_TXD_QW1_DTYPE_M)) !=\n \t\t\trte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE))\n \t\treturn 0;\n@@ -1113,15 +1113,14 @@ tx_backlog_entry_avx512(struct idpf_tx_vec_entry *txep,\n \t\ttxep[i].mbuf = tx_pkts[i];\n }\n \n-#define IDPF_FLEX_TXD_QW1_BUF_SZ_S 48\n static __rte_always_inline void\n-idpf_singleq_vtx1(volatile struct idpf_flex_tx_desc *txdp,\n+idpf_singleq_vtx1(volatile struct idpf_base_tx_desc *txdp,\n \t struct rte_mbuf *pkt, uint64_t flags)\n {\n \tuint64_t high_qw =\n-\t\t(IDPF_TX_DESC_DTYPE_FLEX_DATA << IDPF_FLEX_TXD_QW1_DTYPE_S |\n-\t\t ((uint64_t)flags << IDPF_FLEX_TXD_QW1_CMD_S) |\n-\t\t ((uint64_t)pkt->data_len << IDPF_FLEX_TXD_QW1_BUF_SZ_S));\n+\t\t(IDPF_TX_DESC_DTYPE_DATA |\n+\t\t ((uint64_t)flags << IDPF_TXD_QW1_CMD_S) |\n+\t\t ((uint64_t)pkt->data_len << IDPF_TXD_QW1_TX_BUF_SZ_S));\n \n \t__m128i descriptor = _mm_set_epi64x(high_qw,\n \t\t\t\t\t pkt->buf_iova + pkt->data_off);\n@@ -1131,11 +1130,11 @@ idpf_singleq_vtx1(volatile struct idpf_flex_tx_desc *txdp,\n #define IDPF_TX_LEN_MASK 0xAA\n #define IDPF_TX_OFF_MASK 0x55\n static __rte_always_inline void\n-idpf_singleq_vtx(volatile struct idpf_flex_tx_desc *txdp,\n+idpf_singleq_vtx(volatile struct idpf_base_tx_desc *txdp,\n \t struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)\n {\n-\tconst uint64_t hi_qw_tmpl = (IDPF_TX_DESC_DTYPE_FLEX_DATA |\n-\t\t\t((uint64_t)flags << IDPF_FLEX_TXD_QW1_CMD_S));\n+\tconst uint64_t hi_qw_tmpl = (IDPF_TX_DESC_DTYPE_DATA |\n+\t\t\t((uint64_t)flags << IDPF_TXD_QW1_CMD_S));\n \n \t/* if unaligned on 32-bit boundary, do one to align */\n \tif (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {\n@@ -1148,19 +1147,19 @@ idpf_singleq_vtx(volatile struct idpf_flex_tx_desc *txdp,\n \t\tuint64_t hi_qw3 =\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[3]->data_len <<\n-\t\t\t IDPF_FLEX_TXD_QW1_BUF_SZ_S);\n+\t\t\t IDPF_TXD_QW1_TX_BUF_SZ_S);\n \t\tuint64_t hi_qw2 =\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[2]->data_len <<\n-\t\t\t IDPF_FLEX_TXD_QW1_BUF_SZ_S);\n+\t\t\t IDPF_TXD_QW1_TX_BUF_SZ_S);\n \t\tuint64_t hi_qw1 =\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[1]->data_len <<\n-\t\t\t IDPF_FLEX_TXD_QW1_BUF_SZ_S);\n+\t\t\t IDPF_TXD_QW1_TX_BUF_SZ_S);\n \t\tuint64_t hi_qw0 =\n \t\t\thi_qw_tmpl |\n \t\t\t((uint64_t)pkt[0]->data_len <<\n-\t\t\t IDPF_FLEX_TXD_QW1_BUF_SZ_S);\n+\t\t\t IDPF_TXD_QW1_TX_BUF_SZ_S);\n \n \t\t__m512i desc0_3 =\n \t\t\t_mm512_set_epi64\n@@ -1187,11 +1186,11 @@ idpf_singleq_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pk\n \t\t\t\t\t uint16_t nb_pkts)\n {\n \tstruct idpf_tx_queue *txq = tx_queue;\n-\tvolatile struct idpf_flex_tx_desc *txdp;\n+\tvolatile struct idpf_base_tx_desc *txdp;\n \tstruct idpf_tx_vec_entry *txep;\n \tuint16_t n, nb_commit, tx_id;\n-\tuint64_t flags = IDPF_TX_FLEX_DESC_CMD_EOP;\n-\tuint64_t rs = IDPF_TX_FLEX_DESC_CMD_RS | flags;\n+\tuint64_t flags = IDPF_TX_DESC_CMD_EOP;\n+\tuint64_t rs = IDPF_TX_DESC_CMD_RS | flags;\n \n \t/* cross rx_thresh boundary is not allowed */\n \tnb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);\n@@ -1238,9 +1237,9 @@ idpf_singleq_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pk\n \n \ttx_id = (uint16_t)(tx_id + nb_commit);\n \tif (tx_id > txq->next_rs) {\n-\t\ttxq->tx_ring[txq->next_rs].qw1.cmd_dtype |=\n-\t\t\trte_cpu_to_le_64(((uint64_t)IDPF_TX_FLEX_DESC_CMD_RS) <<\n-\t\t\t\t\t IDPF_FLEX_TXD_QW1_CMD_S);\n+\t\ttxq->tx_ring[txq->next_rs].qw1 |=\n+\t\t\trte_cpu_to_le_64(((uint64_t)IDPF_TX_DESC_CMD_RS) <<\n+\t\t\t\t\t IDPF_TXD_QW1_CMD_S);\n \t\ttxq->next_rs =\n \t\t\t(uint16_t)(txq->next_rs + txq->rs_thresh);\n \t}\n", "prefixes": [ "v4", "1/3" ] }