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GET /api/patches/1311/?format=api
{ "id": 1311, "url": "https://patches.dpdk.org/api/patches/1311/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416199705-24150-13-git-send-email-chaozhu@linux.vnet.ibm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416199705-24150-13-git-send-email-chaozhu@linux.vnet.ibm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416199705-24150-13-git-send-email-chaozhu@linux.vnet.ibm.com", "date": "2014-11-17T04:48:25", "name": "[dpdk-dev,v2,12/12] Add eal memory support for IBM Power Architecture", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "664bc7a66e5cae64f5c1375e90cabc15d4991ad5", "submitter": { "id": 114, "url": "https://patches.dpdk.org/api/people/114/?format=api", "name": "Chao Zhu", "email": "chaozhu@linux.vnet.ibm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416199705-24150-13-git-send-email-chaozhu@linux.vnet.ibm.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1311/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1311/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id B35E88037;\n\tSun, 16 Nov 2014 17:38:02 +0100 (CET)", "from e28smtp07.in.ibm.com (e28smtp07.in.ibm.com [122.248.162.7])\n\tby dpdk.org (Postfix) with ESMTP id 8DC037EF3\n\tfor <dev@dpdk.org>; Sun, 16 Nov 2014 17:37:41 +0100 (CET)", "from /spool/local\n\tby e28smtp07.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <dev@dpdk.org> from <chaozhu@linux.vnet.ibm.com>;\n\tSun, 16 Nov 2014 22:17:53 +0530", "from d28dlp03.in.ibm.com (9.184.220.128)\n\tby e28smtp07.in.ibm.com (192.168.1.137) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tSun, 16 Nov 2014 22:17:50 +0530", "from d28relay02.in.ibm.com (d28relay02.in.ibm.com [9.184.220.59])\n\tby d28dlp03.in.ibm.com (Postfix) with ESMTP id 35C9B1258044\n\tfor <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:56 +0530 (IST)", "from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63])\n\tby d28relay02.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tsAGGm50E46268416 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:18:05 +0530", "from d28av01.in.ibm.com (localhost [127.0.0.1])\n\tby d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tsAGGlnk5032043 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:49 +0530", "from os_controller.crl.ibm.com ([9.186.57.97])\n\tby d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tsAGGlP3D029091 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:49 +0530" ], "From": "Chao Zhu <chaozhu@linux.vnet.ibm.com>", "To": "dev@dpdk.org", "Date": "Sun, 16 Nov 2014 23:48:25 -0500", "Message-Id": "<1416199705-24150-13-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "References": "<1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "14111616-0025-0000-0000-000001E56EB4", "Subject": "[dpdk-dev] [PATCH v2 12/12] Add eal memory support for IBM Power\n\tArchitecture", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "IBM Power architecture has different memory architecture with x86. When\nthe physical memory address is in ascending order, the mmaped virtual\naddress is in descending order. This patch modified the memory segment\ndetection code to make it work for Power. This patch also added a\ncommond ARCH_PPC_64 defination for 64 bit systems.\n\nSigned-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>\n---\n config/defconfig_ppc_64-power8-linuxapp-gcc | 1 +\n config/defconfig_x86_64-native-linuxapp-clang | 1 +\n config/defconfig_x86_64-native-linuxapp-gcc | 1 +\n config/defconfig_x86_64-native-linuxapp-icc | 1 +\n lib/librte_eal/linuxapp/eal/eal_memory.c | 27 +++++++++++++++++++-----\n 5 files changed, 25 insertions(+), 6 deletions(-)", "diff": "diff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc\nindex b10f60c..23a5591 100644\n--- a/config/defconfig_ppc_64-power8-linuxapp-gcc\n+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc\n@@ -35,6 +35,7 @@ CONFIG_RTE_MACHINE=\"power8\"\n CONFIG_RTE_ARCH=\"ppc_64\"\n CONFIG_RTE_ARCH_PPC_64=y\n CONFIG_RTE_ARCH_BIG_ENDIAN=y\n+CONFIG_RTE_ARCH_64=y\n \n CONFIG_RTE_TOOLCHAIN=\"gcc\"\n CONFIG_RTE_TOOLCHAIN_GCC=y\ndiff --git a/config/defconfig_x86_64-native-linuxapp-clang b/config/defconfig_x86_64-native-linuxapp-clang\nindex bbda080..5f3074e 100644\n--- a/config/defconfig_x86_64-native-linuxapp-clang\n+++ b/config/defconfig_x86_64-native-linuxapp-clang\n@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE=\"native\"\n \n CONFIG_RTE_ARCH=\"x86_64\"\n CONFIG_RTE_ARCH_X86_64=y\n+CONFIG_RTE_ARCH_64=y\n \n CONFIG_RTE_TOOLCHAIN=\"clang\"\n CONFIG_RTE_TOOLCHAIN_CLANG=y\ndiff --git a/config/defconfig_x86_64-native-linuxapp-gcc b/config/defconfig_x86_64-native-linuxapp-gcc\nindex 3de818a..60baf5b 100644\n--- a/config/defconfig_x86_64-native-linuxapp-gcc\n+++ b/config/defconfig_x86_64-native-linuxapp-gcc\n@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE=\"native\"\n \n CONFIG_RTE_ARCH=\"x86_64\"\n CONFIG_RTE_ARCH_X86_64=y\n+CONFIG_RTE_ARCH_64=y\n \n CONFIG_RTE_TOOLCHAIN=\"gcc\"\n CONFIG_RTE_TOOLCHAIN_GCC=y\ndiff --git a/config/defconfig_x86_64-native-linuxapp-icc b/config/defconfig_x86_64-native-linuxapp-icc\nindex 795333b..71d1e28 100644\n--- a/config/defconfig_x86_64-native-linuxapp-icc\n+++ b/config/defconfig_x86_64-native-linuxapp-icc\n@@ -36,6 +36,7 @@ CONFIG_RTE_MACHINE=\"native\"\n \n CONFIG_RTE_ARCH=\"x86_64\"\n CONFIG_RTE_ARCH_X86_64=y\n+CONFIG_RTE_ARCH_64=y\n \n CONFIG_RTE_TOOLCHAIN=\"icc\"\n CONFIG_RTE_TOOLCHAIN_ICC=y\ndiff --git a/lib/librte_eal/linuxapp/eal/eal_memory.c b/lib/librte_eal/linuxapp/eal/eal_memory.c\nindex f2454f4..b9c6d2e 100644\n--- a/lib/librte_eal/linuxapp/eal/eal_memory.c\n+++ b/lib/librte_eal/linuxapp/eal/eal_memory.c\n@@ -316,11 +316,11 @@ map_all_hugepages(struct hugepage_file *hugepg_tbl,\n #endif\n \t\t\thugepg_tbl[i].filepath[sizeof(hugepg_tbl[i].filepath) - 1] = '\\0';\n \t\t}\n-#ifndef RTE_ARCH_X86_64\n-\t\t/* for 32-bit systems, don't remap 1G pages, just reuse original\n+#ifndef RTE_ARCH_64\n+\t\t/* for 32-bit systems, don't remap 1G and 16G pages, just reuse original\n \t\t * map address as final map address.\n \t\t */\n-\t\telse if (hugepage_sz == RTE_PGSIZE_1G){\n+\t\telse if ((hugepage_sz == RTE_PGSIZE_1G) || (hugepage_sz == RTE_PGSIZE_16G)){\n \t\t\thugepg_tbl[i].final_va = hugepg_tbl[i].orig_va;\n \t\t\thugepg_tbl[i].orig_va = NULL;\n \t\t\tcontinue;\n@@ -412,11 +412,11 @@ remap_all_hugepages(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n \n \twhile (i < hpi->num_pages[0]) {\n \n-#ifndef RTE_ARCH_X86_64\n-\t\t/* for 32-bit systems, don't remap 1G pages, just reuse original\n+#ifndef RTE_ARCH_64\n+\t\t/* for 32-bit systems, don't remap 1G pages and 16G pages, just reuse original\n \t\t * map address as final map address.\n \t\t */\n-\t\tif (hugepage_sz == RTE_PGSIZE_1G){\n+\t\tif ((hugepage_sz == RTE_PGSIZE_1G) || (hugepage_sz == RTE_PGSIZE_16G)){\n \t\t\thugepg_tbl[i].final_va = hugepg_tbl[i].orig_va;\n \t\t\thugepg_tbl[i].orig_va = NULL;\n \t\t\ti++;\n@@ -1263,9 +1263,18 @@ rte_eal_hugepage_init(void)\n \t\telse if ((hugepage[i].physaddr - hugepage[i-1].physaddr) !=\n \t\t hugepage[i].size)\n \t\t\tnew_memseg = 1;\n+#ifdef RTE_ARCH_PPC_64\n+\t\t/* IBM Power architecture has different memory layout than x86.\n+\t\t* If the physical address is lower address first, the mmaped virtual\n+\t\t* address will be higher address first */\n+\t\telse if (((unsigned long)hugepage[i-1].final_va -\n+\t\t (unsigned long)hugepage[i].final_va) != hugepage[i].size)\n+\t\t\tnew_memseg = 1;\n+#else\n \t\telse if (((unsigned long)hugepage[i].final_va -\n \t\t (unsigned long)hugepage[i-1].final_va) != hugepage[i].size)\n \t\t\tnew_memseg = 1;\n+#endif\n \n \t\tif (new_memseg) {\n \t\t\tj += 1;\n@@ -1284,6 +1293,12 @@ rte_eal_hugepage_init(void)\n \t\t}\n \t\t/* continuation of previous memseg */\n \t\telse {\n+#ifdef RTE_ARCH_PPC_64\n+\t\t/* Use the phy and virt address of the last page as segment address \n+\t\t * for IBM Power architecture */\n+\t\t\tmcfg->memseg[j].phys_addr = hugepage[i].physaddr;\n+\t\t\tmcfg->memseg[j].addr = hugepage[i].final_va;\n+#endif\n \t\t\tmcfg->memseg[j].len += mcfg->memseg[j].hugepage_sz;\n \t\t}\n \t\thugepage[i].memseg_id = j;\n", "prefixes": [ "dpdk-dev", "v2", "12/12" ] }