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GET /api/patches/131016/?format=api
{ "id": 131016, "url": "https://patches.dpdk.org/api/patches/131016/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230901032842.223547-5-wanry@3snic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230901032842.223547-5-wanry@3snic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230901032842.223547-5-wanry@3snic.com", "date": "2023-09-01T03:28:14", "name": "[v3,04/32] net/sssnic: initialize hardware base", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a0c26d63834ab798241b586e515fdfe111b5a8a9", "submitter": { "id": 3119, "url": "https://patches.dpdk.org/api/people/3119/?format=api", "name": "Renyong Wan", "email": "wanry@3snic.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230901032842.223547-5-wanry@3snic.com/mbox/", "series": [ { "id": 29399, "url": "https://patches.dpdk.org/api/series/29399/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29399", "date": "2023-09-01T03:28:13", "name": "Introduce sssnic PMD for 3SNIC's 9x0 serials Ethernet adapters", "version": 3, "mbox": "https://patches.dpdk.org/series/29399/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/131016/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/131016/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E068F42219;\n\tFri, 1 Sep 2023 05:29:29 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3BA52402B4;\n\tFri, 1 Sep 2023 05:29:17 +0200 (CEST)", "from VLXDG1SPAM1.ramaxel.com (email.unionmem.com [221.4.138.186])\n by mails.dpdk.org (Postfix) with ESMTP id 6EE90402BC\n for <dev@dpdk.org>; Fri, 1 Sep 2023 05:29:14 +0200 (CEST)", "from V12DG1MBS03.ramaxel.local ([172.26.18.33])\n by VLXDG1SPAM1.ramaxel.com with ESMTP id 3813SnVg033287;\n Fri, 1 Sep 2023 11:28:51 +0800 (GMT-8)\n (envelope-from wanry@3snic.com)", "from localhost.localdomain (10.64.136.151) by\n V12DG1MBS03.ramaxel.local (172.26.18.33) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n 15.1.2375.17; Fri, 1 Sep 2023 11:28:50 +0800" ], "From": "<wanry@3snic.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@amd.com>, Renyong Wan <wanry@3snic.com>, Steven Song\n <steven.song@3snic.com>", "Subject": "[PATCH v3 04/32] net/sssnic: initialize hardware base", "Date": "Fri, 1 Sep 2023 11:28:14 +0800", "Message-ID": "<20230901032842.223547-5-wanry@3snic.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230901032842.223547-1-wanry@3snic.com>", "References": "<20230901032842.223547-1-wanry@3snic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "7bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.64.136.151]", "X-ClientProxiedBy": "V12DG1MBS03.ramaxel.local (172.26.18.33) To\n V12DG1MBS03.ramaxel.local (172.26.18.33)", "X-DNSRBL": "", "X-SPAM-SOURCE-CHECK": "pass", "X-MAIL": "VLXDG1SPAM1.ramaxel.com 3813SnVg033287", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Renyong Wan <wanry@3snic.com>\n\nInitializing hardware base make hardware ready to be access.\n\nSigned-off-by: Steven Song <steven.song@3snic.com>\nSigned-off-by: Renyong Wan <wanry@3snic.com>\n---\n drivers/net/sssnic/base/meson.build | 13 ++\n drivers/net/sssnic/base/sssnic_hw.c | 207 +++++++++++++++++++++++++++\n drivers/net/sssnic/base/sssnic_hw.h | 49 +++++++\n drivers/net/sssnic/base/sssnic_reg.h | 169 ++++++++++++++++++++++\n drivers/net/sssnic/meson.build | 3 +\n drivers/net/sssnic/sssnic_ethdev.c | 46 +++++-\n drivers/net/sssnic/sssnic_ethdev.h | 18 +++\n 7 files changed, 501 insertions(+), 4 deletions(-)\n create mode 100644 drivers/net/sssnic/base/meson.build\n create mode 100644 drivers/net/sssnic/base/sssnic_hw.c\n create mode 100644 drivers/net/sssnic/base/sssnic_reg.h\n create mode 100644 drivers/net/sssnic/sssnic_ethdev.h", "diff": "diff --git a/drivers/net/sssnic/base/meson.build b/drivers/net/sssnic/base/meson.build\nnew file mode 100644\nindex 0000000000..3e64112c72\n--- /dev/null\n+++ b/drivers/net/sssnic/base/meson.build\n@@ -0,0 +1,13 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018-2022 Shenzhen 3SNIC Information Technology Co., Ltd.\n+\n+sources = [\n+ 'sssnic_hw.c',\n+]\n+\n+c_args = cflags\n+base_lib = static_library('sssnic_base', sources,\n+\tdependencies: [static_rte_eal, static_rte_ethdev, static_rte_bus_pci, static_rte_net],\n+\tc_args: c_args)\n+\n+base_objs = base_lib.extract_all_objects()\ndiff --git a/drivers/net/sssnic/base/sssnic_hw.c b/drivers/net/sssnic/base/sssnic_hw.c\nnew file mode 100644\nindex 0000000000..8b7bba7644\n--- /dev/null\n+++ b/drivers/net/sssnic/base/sssnic_hw.c\n@@ -0,0 +1,207 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2022 Shenzhen 3SNIC Information Technology Co., Ltd.\n+ */\n+\n+#include <rte_byteorder.h>\n+#include <rte_cycles.h>\n+#include <ethdev_pci.h>\n+\n+#include \"../sssnic_log.h\"\n+#include \"sssnic_hw.h\"\n+#include \"sssnic_reg.h\"\n+\n+static int\n+wait_for_sssnic_hw_ready(struct sssnic_hw *hw)\n+{\n+\tstruct sssnic_attr1_reg reg;\n+\tuint32_t timeout_ms = 10;\n+\n+\tdo {\n+\t\treg.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR1_REG);\n+\t\tif (reg.u32 != 0xffffffff && reg.mgmt_init_status != 0)\n+\t\t\treturn 0;\n+\t\trte_delay_ms(1);\n+\t} while (--timeout_ms);\n+\n+\treturn -EBUSY;\n+}\n+\n+static int\n+wait_for_sssnic_db_enabled(struct sssnic_hw *hw)\n+{\n+\tstruct sssnic_attr4_reg r4;\n+\tstruct sssnic_attr5_reg r5;\n+\tuint32_t timeout_ms = 60000;\n+\n+\tdo {\n+\t\tr4.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR4_REG);\n+\t\tr5.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR5_REG);\n+\t\tif (r4.db_ctrl == SSSNIC_DB_CTRL_ENABLE &&\n+\t\t\tr5.outbound_ctrl == SSSNIC_DB_CTRL_ENABLE)\n+\t\t\treturn 0;\n+\t\trte_delay_ms(1);\n+\t} while (--timeout_ms);\n+\n+\treturn -EBUSY;\n+}\n+\n+static void\n+sssnic_attr_setup(struct sssnic_hw *hw)\n+{\n+\tstruct sssnic_attr0_reg attr0;\n+\tstruct sssnic_attr1_reg attr1;\n+\tstruct sssnic_attr2_reg attr2;\n+\tstruct sssnic_attr3_reg attr3;\n+\tstruct sssnic_hw_attr *attr = &hw->attr;\n+\n+\tattr0.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR0_REG);\n+\tattr1.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR1_REG);\n+\tattr2.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR2_REG);\n+\tattr3.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR3_REG);\n+\n+\tattr->func_idx = attr0.func_idx;\n+\tattr->pf_idx = attr0.pf_idx;\n+\tattr->pci_idx = attr0.pci_idx;\n+\tattr->vf_off = attr0.vf_off;\n+\tattr->func_type = attr0.func_type;\n+\tattr->af_idx = attr1.af_idx;\n+\tattr->num_aeq = RTE_BIT32(attr1.num_aeq);\n+\tattr->num_ceq = attr2.num_ceq;\n+\tattr->num_irq = attr2.num_irq;\n+\tattr->global_vf_off = attr3.global_vf_off;\n+\n+\tPMD_DRV_LOG(DEBUG, \"attr0=0x%x, attr1=0x%x, attr2=0x%x, attr3=0x%x\",\n+\t\tattr0.u32, attr1.u32, attr2.u32, attr3.u32);\n+}\n+\n+/* AF and MF election */\n+static void\n+sssnic_af_setup(struct sssnic_hw *hw)\n+{\n+\tstruct sssnic_af_election_reg reg0;\n+\tstruct sssnic_mf_election_reg reg1;\n+\n+\t/* AF election */\n+\treg0.u32 = sssnic_mgmt_reg_read(hw, SSSNIC_AF_ELECTION_REG);\n+\treg0.func_idx = hw->attr.func_idx;\n+\tsssnic_mgmt_reg_write(hw, SSSNIC_AF_ELECTION_REG, reg0.u32);\n+\treg0.u32 = sssnic_mgmt_reg_read(hw, SSSNIC_AF_ELECTION_REG);\n+\thw->attr.af_idx = reg0.func_idx;\n+\tif (hw->attr.af_idx == hw->attr.func_idx) {\n+\t\thw->attr.func_type = SSSNIC_FUNC_TYPE_AF;\n+\t\tPMD_DRV_LOG(INFO, \"Elected PF %d as AF\", hw->attr.func_idx);\n+\n+\t\t/* MF election */\n+\t\treg1.u32 = sssnic_mgmt_reg_read(hw, SSSNIC_MF_ELECTION_REG);\n+\t\treg1.func_idx = hw->attr.func_idx;\n+\t\tsssnic_mgmt_reg_write(hw, SSSNIC_MF_ELECTION_REG, reg1.u32);\n+\t\treg1.u32 = sssnic_mgmt_reg_read(hw, SSSNIC_MF_ELECTION_REG);\n+\t\thw->attr.mf_idx = reg1.func_idx;\n+\t\tif (hw->attr.mf_idx == hw->attr.func_idx)\n+\t\t\tPMD_DRV_LOG(INFO, \"Elected PF %d as MF\",\n+\t\t\t\thw->attr.func_idx);\n+\t}\n+}\n+\n+void\n+sssnic_msix_state_set(struct sssnic_hw *hw, uint16_t msix_id, int state)\n+{\n+\tstruct sssnic_msix_ctrl_reg reg;\n+\n+\treg.u32 = 0;\n+\tif (state == SSSNIC_MSIX_ENABLE)\n+\t\treg.int_msk_clr = 1;\n+\telse\n+\t\treg.int_msk_set = 1;\n+\treg.msxi_idx = msix_id;\n+\tsssnic_cfg_reg_write(hw, SSSNIC_MSIX_CTRL_REG, reg.u32);\n+}\n+\n+static void\n+sssnic_msix_all_disable(struct sssnic_hw *hw)\n+{\n+\tuint16_t i;\n+\tint num_irqs = hw->attr.num_irq;\n+\n+\tfor (i = 0; i < num_irqs; i++)\n+\t\tsssnic_msix_state_set(hw, i, SSSNIC_MSIX_DISABLE);\n+}\n+\n+static void\n+sssnic_pf_status_set(struct sssnic_hw *hw, enum sssnic_pf_status status)\n+{\n+\tstruct sssnic_attr6_reg reg;\n+\n+\treg.u32 = sssnic_cfg_reg_read(hw, SSSNIC_ATTR6_REG);\n+\treg.pf_status = status;\n+\tsssnic_cfg_reg_write(hw, SSSNIC_ATTR6_REG, reg.u32);\n+}\n+\n+static int\n+sssnic_base_init(struct sssnic_hw *hw)\n+{\n+\tint ret;\n+\tstruct rte_pci_device *pci_dev;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tpci_dev = hw->pci_dev;\n+\n+\t/* get base addresses of hw registers */\n+\thw->cfg_base_addr =\n+\t\t(uint8_t *)pci_dev->mem_resource[SSSNIC_PCI_BAR_CFG].addr;\n+\thw->mgmt_base_addr =\n+\t\t(uint8_t *)pci_dev->mem_resource[SSSNIC_PCI_BAR_MGMT].addr;\n+\thw->db_base_addr =\n+\t\t(uint8_t *)pci_dev->mem_resource[SSSNIC_PCI_BAR_DB].addr;\n+\thw->db_mem_len =\n+\t\t(uint8_t *)pci_dev->mem_resource[SSSNIC_PCI_BAR_DB].len;\n+\n+\tret = wait_for_sssnic_hw_ready(hw);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Hardware is not ready!\");\n+\t\treturn -EBUSY;\n+\t}\n+\tsssnic_attr_setup(hw);\n+\tret = wait_for_sssnic_db_enabled(hw);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Doorbell is not enabled!\");\n+\t\treturn -EBUSY;\n+\t}\n+\tsssnic_af_setup(hw);\n+\tsssnic_msix_all_disable(hw);\n+\tsssnic_pf_status_set(hw, SSSNIC_PF_STATUS_INIT);\n+\n+\tPMD_DRV_LOG(DEBUG,\n+\t\t\"func_idx:%d, func_type:%d, pci_idx:%d, vf_off:%d, global_vf_off:%d \"\n+\t\t\"pf_idx:%d, af_idx:%d, mf_idx:%d, num_aeq:%d, num_ceq:%d, num_irq:%d\",\n+\t\thw->attr.func_idx, hw->attr.func_type, hw->attr.pci_idx,\n+\t\thw->attr.vf_off, hw->attr.global_vf_off, hw->attr.pf_idx,\n+\t\thw->attr.af_idx, hw->attr.mf_idx, hw->attr.num_aeq,\n+\t\thw->attr.num_ceq, hw->attr.num_irq);\n+\n+\treturn 0;\n+}\n+\n+int\n+sssnic_hw_init(struct sssnic_hw *hw)\n+{\n+\tint ret;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tret = sssnic_base_init(hw);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to initialize hardware base\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+void\n+sssnic_hw_shutdown(struct sssnic_hw *hw)\n+{\n+\tRTE_SET_USED(hw);\n+\tPMD_INIT_FUNC_TRACE();\n+}\ndiff --git a/drivers/net/sssnic/base/sssnic_hw.h b/drivers/net/sssnic/base/sssnic_hw.h\nindex db916b1977..65d4d562b4 100644\n--- a/drivers/net/sssnic/base/sssnic_hw.h\n+++ b/drivers/net/sssnic/base/sssnic_hw.h\n@@ -8,4 +8,53 @@\n #define SSSNIC_PCI_VENDOR_ID 0x1F3F\n #define SSSNIC_DEVICE_ID_STD 0x9020\n \n+#define SSSNIC_PCI_BAR_CFG 1\n+#define SSSNIC_PCI_BAR_MGMT 3\n+#define SSSNIC_PCI_BAR_DB 4\n+\n+#define SSSNIC_FUNC_TYPE_PF 0\n+#define SSSNIC_FUNC_TYPE_VF 1\n+#define SSSNIC_FUNC_TYPE_AF 2\n+#define SSSNIC_FUNC_TYPE_INVALID 3\n+\n+#define SSSNIC_DB_CTRL_ENABLE 0x0\n+#define SSSNIC_DB_CTRL_DISABLE 0x1\n+\n+#define SSSNIC_MSIX_ENABLE 0\n+#define SSSNIC_MSIX_DISABLE 1\n+\n+enum sssnic_pf_status {\n+\tSSSNIC_PF_STATUS_INIT = 0x0,\n+\tSSSNIC_PF_STATUS_ACTIVE = 0x11,\n+\tSSSNIC_PF_STATUS_START = 0x12,\n+\tSSSNIC_PF_STATUS_FINI = 0x13,\n+};\n+\n+struct sssnic_hw_attr {\n+\tuint16_t func_idx;\n+\tuint8_t pf_idx;\n+\tuint8_t pci_idx;\n+\tuint8_t vf_off; /* vf offset in pf */\n+\tuint8_t global_vf_off;\n+\tuint8_t func_type;\n+\tuint8_t af_idx;\n+\tuint8_t mf_idx;\n+\tuint8_t num_aeq;\n+\tuint16_t num_ceq;\n+\tuint16_t num_irq;\n+};\n+\n+struct sssnic_hw {\n+\tstruct rte_pci_device *pci_dev;\n+\tuint8_t *cfg_base_addr;\n+\tuint8_t *mgmt_base_addr;\n+\tuint8_t *db_base_addr;\n+\tuint8_t *db_mem_len;\n+\tstruct sssnic_hw_attr attr;\n+};\n+\n+int sssnic_hw_init(struct sssnic_hw *hw);\n+void sssnic_hw_shutdown(struct sssnic_hw *hw);\n+void sssnic_msix_state_set(struct sssnic_hw *hw, uint16_t msix_id, int state);\n+\n #endif /* _SSSNIC_HW_H_ */\ndiff --git a/drivers/net/sssnic/base/sssnic_reg.h b/drivers/net/sssnic/base/sssnic_reg.h\nnew file mode 100644\nindex 0000000000..77d83292eb\n--- /dev/null\n+++ b/drivers/net/sssnic/base/sssnic_reg.h\n@@ -0,0 +1,169 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2022 Shenzhen 3SNIC Information Technology Co., Ltd.\n+ */\n+\n+#ifndef _SSSNIC_REG_H_\n+#define _SSSNIC_REG_H_\n+\n+#include <rte_io.h>\n+\n+/* registers of config */\n+#define SSSNIC_ATTR0_REG 0x0\n+#define SSSNIC_ATTR1_REG 0x4\n+#define SSSNIC_ATTR2_REG 0x8\n+#define SSSNIC_ATTR3_REG 0xC\n+#define SSSNIC_ATTR4_REG 0x10\n+#define SSSNIC_ATTR5_REG 0x14\n+#define SSSNIC_ATTR6_REG 0x18\n+\n+#define SSSNIC_MSIX_CTRL_REG 0x58\n+\n+/* registers of mgmt */\n+#define SSSNIC_AF_ELECTION_REG 0x6000\n+#define SSSNIC_MF_ELECTION_REG 0x6020\n+\n+struct sssnic_attr0_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t func_idx : 12;\n+\t\t\tuint32_t pf_idx : 5;\n+\t\t\tuint32_t pci_idx : 3;\n+\t\t\tuint32_t vf_off : 8; /* vf offset in pf */\n+\t\t\tuint32_t func_type : 1;\n+\t\t\tuint32_t resvd_0 : 4;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_attr1_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t af_idx : 6;\n+\t\t\tuint32_t resvd_0 : 2;\n+\t\t\tuint32_t num_aeq : 2;\n+\t\t\tuint32_t resvd_1 : 20;\n+\t\t\tuint32_t mgmt_init_status : 1;\n+\t\t\tuint32_t pf_init_status : 1;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_attr2_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t num_ceq : 9;\n+\t\t\tuint32_t num_dma_attr : 3;\n+\t\t\tuint32_t resvd_0 : 4;\n+\t\t\tuint32_t num_irq : 11;\n+\t\t\tuint32_t resvd_1 : 5;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_attr3_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t global_vf_off1 : 12;\n+\t\t\tuint32_t resvd_0 : 4;\n+\t\t\tuint32_t global_vf_off : 12; /*global vf offset*/\n+\t\t\tuint32_t resvd_1 : 4;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_attr4_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t db_ctrl : 1;\n+\t\t\tuint32_t resvd_0 : 31;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_attr5_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t outbound_ctrl : 1;\n+\t\t\tuint32_t resvd_0 : 31;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_attr6_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t pf_status : 16;\n+\t\t\tuint32_t resvd_0 : 6;\n+\t\t\tuint32_t msix_en : 1;\n+\t\t\tuint32_t max_queues : 9;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_af_election_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t func_idx : 6;\n+\t\t\tuint32_t resvd_0 : 26;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_mf_election_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t func_idx : 5;\n+\t\t\tuint32_t resvd_0 : 27;\n+\t\t};\n+\t};\n+};\n+\n+struct sssnic_msix_ctrl_reg {\n+\tunion {\n+\t\tuint32_t u32;\n+\t\tstruct {\n+\t\t\tuint32_t resend_timer_clr : 1;\n+\t\t\tuint32_t int_msk_set : 1;\n+\t\t\tuint32_t int_msk_clr : 1;\n+\t\t\tuint32_t auto_msk_set : 1;\n+\t\t\tuint32_t auto_msk_clr : 1;\n+\t\t\tuint32_t resvd_0 : 17;\n+\t\t\tuint32_t msxi_idx : 10;\n+\t\t};\n+\t};\n+};\n+\n+static inline uint32_t\n+sssnic_cfg_reg_read(struct sssnic_hw *hw, uint32_t reg)\n+{\n+\treturn rte_be_to_cpu_32(rte_read32(hw->cfg_base_addr + reg));\n+}\n+\n+static inline void\n+sssnic_cfg_reg_write(struct sssnic_hw *hw, uint32_t reg, uint32_t val)\n+{\n+\trte_write32(rte_cpu_to_be_32(val), hw->cfg_base_addr + reg);\n+}\n+\n+static inline uint32_t\n+sssnic_mgmt_reg_read(struct sssnic_hw *hw, uint32_t reg)\n+{\n+\treturn rte_be_to_cpu_32(rte_read32(hw->mgmt_base_addr + reg));\n+}\n+\n+static inline void\n+sssnic_mgmt_reg_write(struct sssnic_hw *hw, uint32_t reg, uint32_t val)\n+{\n+\trte_write32(rte_cpu_to_be_32(val), hw->mgmt_base_addr + reg);\n+}\n+\n+#endif /*_SSSNIC_REG_H_*/\ndiff --git a/drivers/net/sssnic/meson.build b/drivers/net/sssnic/meson.build\nindex fda65aa380..328bb41436 100644\n--- a/drivers/net/sssnic/meson.build\n+++ b/drivers/net/sssnic/meson.build\n@@ -13,6 +13,9 @@ if (arch_subdir != 'x86' and arch_subdir != 'arm') or (not dpdk_conf.get('RTE_AR\n subdir_done()\n endif\n \n+subdir('base')\n+objs = [base_objs]\n+\n sources = files(\n 'sssnic_ethdev.c',\n )\ndiff --git a/drivers/net/sssnic/sssnic_ethdev.c b/drivers/net/sssnic/sssnic_ethdev.c\nindex 4f8b5c2684..e198b1e1d0 100644\n--- a/drivers/net/sssnic/sssnic_ethdev.c\n+++ b/drivers/net/sssnic/sssnic_ethdev.c\n@@ -7,25 +7,62 @@\n \n #include \"sssnic_log.h\"\n #include \"base/sssnic_hw.h\"\n+#include \"sssnic_ethdev.h\"\n+\n+static void\n+sssnic_ethdev_release(struct rte_eth_dev *ethdev)\n+{\n+\tstruct sssnic_hw *hw = SSSNIC_ETHDEV_TO_HW(ethdev);\n+\n+\tsssnic_hw_shutdown(hw);\n+\trte_free(hw);\n+}\n \n static int\n sssnic_ethdev_init(struct rte_eth_dev *ethdev)\n {\n-\tRTE_SET_USED(ethdev);\n+\tint ret;\n+\tstruct sssnic_hw *hw;\n+\tstruct sssnic_netdev *netdev;\n+\tstruct rte_pci_device *pci_dev;\n+\n \tPMD_INIT_FUNC_TRACE();\n \n-\treturn -EINVAL;\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tnetdev = SSSNIC_ETHDEV_PRIVATE(ethdev);\n+\tpci_dev = RTE_ETH_DEV_TO_PCI(ethdev);\n+\thw = rte_zmalloc(\"sssnic_hw\", sizeof(struct sssnic_hw), 0);\n+\tif (hw == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to alloc memory for hw\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tnetdev->hw = hw;\n+\thw->pci_dev = pci_dev;\n+\tret = sssnic_hw_init(hw);\n+\tif (ret != 0) {\n+\t\trte_free(hw);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n }\n \n static int\n sssnic_ethdev_uninit(struct rte_eth_dev *ethdev)\n {\n-\tRTE_SET_USED(ethdev);\n \tPMD_INIT_FUNC_TRACE();\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\t/* ethdev port has been released */\n+\tif (ethdev->state == RTE_ETH_DEV_UNUSED)\n+\t\treturn 0;\n+\n+\tsssnic_ethdev_release(ethdev);\n+\n \treturn -EINVAL;\n }\n \n@@ -35,7 +72,8 @@ sssnic_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \tRTE_SET_USED(pci_drv);\n \tPMD_INIT_FUNC_TRACE();\n \n-\treturn rte_eth_dev_pci_generic_probe(pci_dev, 0, sssnic_ethdev_init);\n+\treturn rte_eth_dev_pci_generic_probe(pci_dev,\n+\t\tsizeof(struct sssnic_netdev), sssnic_ethdev_init);\n }\n \n static int\ndiff --git a/drivers/net/sssnic/sssnic_ethdev.h b/drivers/net/sssnic/sssnic_ethdev.h\nnew file mode 100644\nindex 0000000000..5d951134cc\n--- /dev/null\n+++ b/drivers/net/sssnic/sssnic_ethdev.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2022 Shenzhen 3SNIC Information Technology Co., Ltd.\n+ */\n+\n+#ifndef _SSSNIC_ETHDEV_H_\n+#define _SSSNIC_ETHDEV_H_\n+\n+struct sssnic_netdev {\n+\tvoid *hw;\n+};\n+\n+#define SSSNIC_ETHDEV_PRIVATE(eth_dev) \\\n+\t((struct sssnic_netdev *)(eth_dev)->data->dev_private)\n+#define SSSNIC_NETDEV_TO_HW(netdev) ((struct sssnic_hw *)(netdev)->hw)\n+#define SSSNIC_ETHDEV_TO_HW(eth_dev) \\\n+\tSSSNIC_NETDEV_TO_HW(SSSNIC_ETHDEV_PRIVATE(eth_dev))\n+\n+#endif /*_SSSNIC_ETHDEV_H_*/\n", "prefixes": [ "v3", "04/32" ] }