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GET /api/patches/130917/?format=api
{ "id": 130917, "url": "https://patches.dpdk.org/api/patches/130917/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230830155919.592390-3-bruce.richardson@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230830155919.592390-3-bruce.richardson@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230830155919.592390-3-bruce.richardson@intel.com", "date": "2023-08-30T15:59:17", "name": "[2/4] net/iavf: fix buffer leak on Tx queue stop", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e468333e88fb2c8d596cfab0372b8e38818c9f7b", "submitter": { "id": 20, "url": "https://patches.dpdk.org/api/people/20/?format=api", "name": "Bruce Richardson", "email": "bruce.richardson@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230830155919.592390-3-bruce.richardson@intel.com/mbox/", "series": [ { "id": 29377, "url": "https://patches.dpdk.org/api/series/29377/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=29377", "date": "2023-08-30T15:59:15", "name": "Fix i40e/iavf queue reconfig and restarting", "version": 1, "mbox": "https://patches.dpdk.org/series/29377/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/130917/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/130917/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 27C4141FD1;\n\tWed, 30 Aug 2023 18:07:05 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BEA7242D2A;\n\tWed, 30 Aug 2023 18:00:18 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id 14376402D4;\n Wed, 30 Aug 2023 17:59:49 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Aug 2023 08:59:49 -0700", "from silpixa00401385.ir.intel.com ([10.237.214.14])\n by orsmga002.jf.intel.com with ESMTP; 30 Aug 2023 08:59:47 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1693411190; x=1724947190;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=dNHN+xna00zMIdi2cuOsslBvvYiBON4ybUk45AVelSs=;\n b=Mt/gfu5twvcErBYAoGfXRuQ/T0faTsbCiaI/ff8WHrJ4q0/ilxz3W6Yt\n /PAdeE4EIt0eJA7/fnDEyCbjzE850jKxdMZgBD2HDwdnLDdoCzhtjwboy\n juvEN3b8oUhjokjgVkd6Xl3OSIYl4MMhvpQr1AFN47duEuEqapDQBYF3F\n o/XXs3gX820gBWBsVcdsbNXwTwol1n0bZ2nD9bFAvGjRm0FaCiazbhPb4\n IdNZQvPP65xU02DgsQpwOBn0xMJxDFLyNssisUJi1phI3U9EXyQnijmYv\n hTvW9ZhXwsnA/G2V53AAeUWl+LZ7U6If6CpRxeadjKB2a4s5nXpg7LPQi w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10818\"; a=\"360674194\"", "E=Sophos;i=\"6.02,214,1688454000\"; d=\"scan'208\";a=\"360674194\"", "E=McAfee;i=\"6600,9927,10818\"; a=\"739142711\"", "E=Sophos;i=\"6.02,214,1688454000\"; d=\"scan'208\";a=\"739142711\"" ], "X-ExtLoop1": "1", "From": "Bruce Richardson <bruce.richardson@intel.com>", "To": "dev@dpdk.org", "Cc": "Yuying Zhang <Yuying.Zhang@intel.com>,\n Beilei Xing <beilei.xing@intel.com>,\n Jingjing Wu <jingjing.wu@intel.com>,\n Bruce Richardson <bruce.richardson@intel.com>, wenzhuo.lu@intel.com,\n stable@dpdk.org", "Subject": "[PATCH 2/4] net/iavf: fix buffer leak on Tx queue stop", "Date": "Wed, 30 Aug 2023 16:59:17 +0100", "Message-Id": "<20230830155919.592390-3-bruce.richardson@intel.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20230830155919.592390-1-bruce.richardson@intel.com>", "References": "<20230830155919.592390-1-bruce.richardson@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "When a queue is stopped all buffers are meant to released from it, and\nthen a new set of buffers reallocated on start. For the iavf code when\nusing vector Tx, some buffers were left in the ring, and so those\nbuffers were leaked. The buffers were missed as the release code only\nhandled one side of a wrap-around case in the ring.\n\nFix the issue by doing a single iteration of the ring freeing all\nbuffers in it, handling wraparound through a simple post-increment\ncheck.\n\nFixes: 319c421f3890 (\"net/avf: enable SSE Rx Tx\")\nFixes: 9ab9514c150e (\"net/iavf: enable AVX512 for Tx\")\nCc: wenzhuo.lu@intel.com\nCc: jingjing.wu@intel.com\nCc: stable@dpdk.org\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n drivers/net/iavf/iavf_rxtx_vec_avx512.c | 17 ++++++++---------\n drivers/net/iavf/iavf_rxtx_vec_common.h | 11 +++++------\n 2 files changed, 13 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx512.c b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\nindex 3e66df5341..48337d5e03 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_avx512.c\n+++ b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\n@@ -2460,20 +2460,19 @@ iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)\n {\n \tunsigned int i;\n \tconst uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);\n+\tconst uint16_t end_desc = txq->tx_tail >> txq->use_ctx; /* next empty slot */\n+\tconst uint16_t wrap_point = txq->nb_tx_desc >> txq->use_ctx; /* end of SW ring */\n \tstruct iavf_tx_vec_entry *swr = (void *)txq->sw_ring;\n \n \tif (!txq->sw_ring || txq->nb_free == max_desc)\n \t\treturn;\n \n-\ti = (txq->next_dd >> txq->use_ctx) + 1 -\n-\t\t\t(txq->rs_thresh >> txq->use_ctx);\n-\n-\tif (txq->tx_tail < i) {\n-\t\tfor (; i < (unsigned int)(txq->nb_tx_desc >> txq->use_ctx); i++) {\n-\t\t\trte_pktmbuf_free_seg(swr[i].mbuf);\n-\t\t\tswr[i].mbuf = NULL;\n-\t\t}\n-\t\ti = 0;\n+\ti = (txq->next_dd - txq->rs_thresh + 1) >> txq->use_ctx;\n+\twhile (i != end_desc) {\n+\t\trte_pktmbuf_free_seg(swr[i].mbuf);\n+\t\tswr[i].mbuf = NULL;\n+\t\tif (++i == wrap_point)\n+\t\t\ti = 0;\n \t}\n }\n \ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_common.h b/drivers/net/iavf/iavf_rxtx_vec_common.h\nindex ddb13ce8c3..1fac957fe1 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_common.h\n+++ b/drivers/net/iavf/iavf_rxtx_vec_common.h\n@@ -186,12 +186,11 @@ _iavf_tx_queue_release_mbufs_vec(struct iavf_tx_queue *txq)\n \t\treturn;\n \n \ti = txq->next_dd - txq->rs_thresh + 1;\n-\tif (txq->tx_tail < i) {\n-\t\tfor (; i < txq->nb_tx_desc; i++) {\n-\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n-\t\t\ttxq->sw_ring[i].mbuf = NULL;\n-\t\t}\n-\t\ti = 0;\n+\twhile (i != txq->tx_tail) {\n+\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n+\t\ttxq->sw_ring[i].mbuf = NULL;\n+\t\tif (++i == txq->nb_tx_desc)\n+\t\t\ti = 0;\n \t}\n }\n \n", "prefixes": [ "2/4" ] }