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GET /api/patches/1307/?format=api
https://patches.dpdk.org/api/patches/1307/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416199705-24150-9-git-send-email-chaozhu@linux.vnet.ibm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416199705-24150-9-git-send-email-chaozhu@linux.vnet.ibm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416199705-24150-9-git-send-email-chaozhu@linux.vnet.ibm.com", "date": "2014-11-17T04:48:21", "name": "[dpdk-dev,v2,08/12] Add CPU flag checking for IBM Power architecture", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ebd20c6632f1bbc4fe9d07fdc697915d5dd9a954", "submitter": { "id": 114, "url": "https://patches.dpdk.org/api/people/114/?format=api", "name": "Chao Zhu", "email": "chaozhu@linux.vnet.ibm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416199705-24150-9-git-send-email-chaozhu@linux.vnet.ibm.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1307/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1307/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 18CC58002;\n\tSun, 16 Nov 2014 17:37:57 +0100 (CET)", "from e28smtp04.in.ibm.com (e28smtp04.in.ibm.com [122.248.162.4])\n\tby dpdk.org (Postfix) with ESMTP id E78337FAC\n\tfor <dev@dpdk.org>; Sun, 16 Nov 2014 17:37:34 +0100 (CET)", "from /spool/local\n\tby e28smtp04.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <dev@dpdk.org> from <chaozhu@linux.vnet.ibm.com>;\n\tSun, 16 Nov 2014 22:17:45 +0530", "from d28dlp03.in.ibm.com (9.184.220.128)\n\tby e28smtp04.in.ibm.com (192.168.1.134) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tSun, 16 Nov 2014 22:17:44 +0530", "from d28relay01.in.ibm.com (d28relay01.in.ibm.com [9.184.220.58])\n\tby d28dlp03.in.ibm.com (Postfix) with ESMTP id 03AE4125804B\n\tfor <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:49 +0530 (IST)", "from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63])\n\tby d28relay01.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tsAGGlNgZ56230040 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:23 +0530", "from d28av01.in.ibm.com (localhost [127.0.0.1])\n\tby d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tsAGGlhpT031275 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:43 +0530", "from os_controller.crl.ibm.com ([9.186.57.97])\n\tby d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tsAGGlP39029091 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:42 +0530" ], "From": "Chao Zhu <chaozhu@linux.vnet.ibm.com>", "To": "dev@dpdk.org", "Date": "Sun, 16 Nov 2014 23:48:21 -0500", "Message-Id": "<1416199705-24150-9-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "References": "<1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "14111616-0013-0000-0000-000002439460", "Subject": "[dpdk-dev] [PATCH v2 08/12] Add CPU flag checking for IBM Power\n\tarchitecture", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "IBM Power processor doesn't have CPU flag hardware registers. This patch\nuses aux vector software register to get CPU flags and add CPU flag\nchecking support for IBM Power architecture.\n\nSigned-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>\n---\n app/test/test_cpuflags.c | 35 ++++\n .../common/include/arch/ppc_64/rte_cpuflags.h | 184 ++++++++++++++++++++\n mk/rte.cpuflags.mk | 17 ++\n 3 files changed, 236 insertions(+), 0 deletions(-)\n create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h", "diff": "diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c\nindex 82c0197..5aeba5d 100644\n--- a/app/test/test_cpuflags.c\n+++ b/app/test/test_cpuflags.c\n@@ -80,6 +80,40 @@ test_cpuflags(void)\n \tint result;\n \tprintf(\"\\nChecking for flags from different registers...\\n\");\n \n+#ifdef RTE_ARCH_PPC_64\n+\tprintf(\"Check for PPC64:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_PPC64);\n+\n+\tprintf(\"Check for PPC32:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_PPC32);\n+\n+\tprintf(\"Check for VSX:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_VSX);\n+\n+\tprintf(\"Check for DFP:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_DFP);\n+\n+\tprintf(\"Check for FPU:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_FPU);\n+\n+\tprintf(\"Check for SMT:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_SMT);\n+\n+\tprintf(\"Check for MMU:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_MMU);\n+\n+\tprintf(\"Check for ALTIVEC:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_ALTIVEC);\n+\n+\tprintf(\"Check for ARCH_2_06:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_06);\n+\n+\tprintf(\"Check for ARCH_2_07:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_07);\n+\n+\tprintf(\"Check for ICACHE_SNOOP:\\t\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_ICACHE_SNOOP);\n+#else\n \tprintf(\"Check for SSE:\\t\\t\");\n \tCHECK_FOR_FLAG(RTE_CPUFLAG_SSE);\n \n@@ -117,6 +151,7 @@ test_cpuflags(void)\n \tCHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);\n \n \n+#endif\n \n \t/*\n \t * Check if invalid data is handled properly\ndiff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h b/lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h\nnew file mode 100644\nindex 0000000..6b38f1c\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h\n@@ -0,0 +1,184 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_CPUFLAGS_PPC_64_H_\n+#define _RTE_CPUFLAGS_PPC_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <elf.h>\n+#include <fcntl.h>\n+#include <assert.h>\n+#include <unistd.h>\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+/* Symbolic values for the entries in the auxiliary table */\n+#define AT_HWCAP 16\n+#define AT_HWCAP2 26\n+\n+/* software based registers */\n+enum cpu_register_t {\n+\tREG_HWCAP = 0,\n+\tREG_HWCAP2,\n+};\n+\n+/**\n+ * Enumeration of all CPU features supported\n+ */\n+enum rte_cpu_flag_t {\n+\tRTE_CPUFLAG_PPC_LE = 0,\n+\tRTE_CPUFLAG_TRUE_LE,\n+\tRTE_CPUFLAG_PSERIES_PERFMON_COMPAT,\n+\tRTE_CPUFLAG_VSX,\n+\tRTE_CPUFLAG_ARCH_2_06,\n+\tRTE_CPUFLAG_POWER6_EXT,\n+\tRTE_CPUFLAG_DFP,\n+\tRTE_CPUFLAG_PA6T,\n+\tRTE_CPUFLAG_ARCH_2_05,\n+\tRTE_CPUFLAG_ICACHE_SNOOP,\n+\tRTE_CPUFLAG_SMT,\n+\tRTE_CPUFLAG_BOOKE,\n+\tRTE_CPUFLAG_CELLBE,\n+\tRTE_CPUFLAG_POWER5_PLUS,\n+\tRTE_CPUFLAG_POWER5,\n+\tRTE_CPUFLAG_POWER4,\n+\tRTE_CPUFLAG_NOTB,\n+\tRTE_CPUFLAG_EFP_DOUBLE,\n+\tRTE_CPUFLAG_EFP_SINGLE,\n+\tRTE_CPUFLAG_SPE,\n+\tRTE_CPUFLAG_UNIFIED_CACHE,\n+\tRTE_CPUFLAG_4xxMAC,\n+\tRTE_CPUFLAG_MMU,\n+\tRTE_CPUFLAG_FPU,\n+\tRTE_CPUFLAG_ALTIVEC,\n+\tRTE_CPUFLAG_PPC601,\n+\tRTE_CPUFLAG_PPC64,\n+\tRTE_CPUFLAG_PPC32,\n+\tRTE_CPUFLAG_TAR,\n+\tRTE_CPUFLAG_LSEL,\n+\tRTE_CPUFLAG_EBB,\n+\tRTE_CPUFLAG_DSCR,\n+\tRTE_CPUFLAG_HTM,\n+\tRTE_CPUFLAG_ARCH_2_07,\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */\n+};\n+\n+static const struct feature_entry cpu_feature_table[] = {\n+\tFEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP, 0)\n+\tFEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP, 1)\n+\tFEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP, 6)\n+\tFEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP, 7)\n+\tFEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP, 8)\n+\tFEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP, 9)\n+\tFEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP, 10)\n+\tFEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP, 11)\n+\tFEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP, 12)\n+\tFEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP, 13)\n+\tFEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP, 14)\n+\tFEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP, 15)\n+\tFEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP, 16)\n+\tFEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP, 17)\n+\tFEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP, 18)\n+\tFEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP, 19)\n+\tFEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP, 20)\n+\tFEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP, 21)\n+\tFEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP, 22)\n+\tFEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP, 23)\n+\tFEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP, 24)\n+\tFEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP, 25)\n+\tFEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP, 26)\n+\tFEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP, 27)\n+\tFEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP, 28)\n+\tFEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP, 29)\n+\tFEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP, 30)\n+\tFEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP, 31)\n+\tFEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2, 26)\n+\tFEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2, 27)\n+\tFEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2, 28)\n+\tFEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2, 29)\n+\tFEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2, 30)\n+\tFEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2, 31)\n+};\n+\n+/*\n+ * Read AUXV software register and get cpu features for Power\n+ */\n+static inline void\n+rte_cpu_get_features( __attribute__((unused)) uint32_t leaf, __attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)\n+{\n+ int auxv_fd;\n+ Elf64_auxv_t auxv;\n+ auxv_fd = open(\"/proc/self/auxv\", O_RDONLY);\n+ assert(auxv_fd);\n+ while (read(auxv_fd, &auxv, sizeof(Elf64_auxv_t))== sizeof(Elf64_auxv_t)) {\n+ if (auxv.a_type == AT_HWCAP)\n+ out[REG_HWCAP] = auxv.a_un.a_val;\n+ else if (auxv.a_type == AT_HWCAP2)\n+ out[REG_HWCAP2] = auxv.a_un.a_val;\n+ }\n+}\n+\n+/*\n+ * Checks if a particular flag is available on current machine.\n+ */\n+static inline int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n+{\n+\tconst struct feature_entry *feat;\n+\tcpuid_registers_t regs={0};\n+\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\t/* Flag does not match anything in the feature tables */\n+\t\treturn -ENOENT;\n+\n+\tfeat = &cpu_feature_table[feature];\n+\n+\tif (!feat->leaf)\n+\t\t/* This entry in the table wasn't filled out! */\n+\t\treturn -EFAULT;\n+\n+\t/* get the cpuid leaf containing the desired feature */\n+\trte_cpu_get_features(feat->leaf, feat->subleaf, regs);\n+\n+\t/* check if the feature is enabled */\n+\treturn (regs[feat->reg] >> feat->bit) & 1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CPUFLAGS_PPC_64_H_ */\ndiff --git a/mk/rte.cpuflags.mk b/mk/rte.cpuflags.mk\nindex 65332e1..f595cd0 100644\n--- a/mk/rte.cpuflags.mk\n+++ b/mk/rte.cpuflags.mk\n@@ -89,6 +89,23 @@ ifneq ($(filter $(AUTO_CPUFLAGS),__AVX2__),)\n CPUFLAGS += AVX2\n endif\n \n+# IBM Power CPU flags\n+ifneq ($(filter $(AUTO_CPUFLAGS),__PPC64__),)\n+CPUFLAGS += PPC64\n+endif\n+\n+ifneq ($(filter $(AUTO_CPUFLAGS),__PPC32__),)\n+CPUFLAGS += PPC32\n+endif\n+\n+ifneq ($(filter $(AUTO_CPUFLAGS),__vector),)\n+CPUFLAGS += ALTIVEC\n+endif\n+\n+ifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),)\n+CPUFLAGS += VSX\n+endif\n+\n MACHINE_CFLAGS += $(addprefix -DRTE_MACHINE_CPUFLAG_,$(CPUFLAGS))\n \n # To strip whitespace\n", "prefixes": [ "dpdk-dev", "v2", "08/12" ] }{ "id": 1307, "url": "