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GET /api/patches/1304/?format=api
{ "id": 1304, "url": "https://patches.dpdk.org/api/patches/1304/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1416199705-24150-5-git-send-email-chaozhu@linux.vnet.ibm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1416199705-24150-5-git-send-email-chaozhu@linux.vnet.ibm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1416199705-24150-5-git-send-email-chaozhu@linux.vnet.ibm.com", "date": "2014-11-17T04:48:17", "name": "[dpdk-dev,v2,04/12] Add CPU cycle operations for IBM Power architecture", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5df8c552c8efd03cadc51b6560c7cc45915b37bf", "submitter": { "id": 114, "url": "https://patches.dpdk.org/api/people/114/?format=api", "name": "Chao Zhu", "email": "chaozhu@linux.vnet.ibm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1416199705-24150-5-git-send-email-chaozhu@linux.vnet.ibm.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/1304/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/1304/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id C80557FCB;\n\tSun, 16 Nov 2014 17:37:38 +0100 (CET)", "from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [122.248.162.2])\n\tby dpdk.org (Postfix) with ESMTP id 1E84A7F95\n\tfor <dev@dpdk.org>; Sun, 16 Nov 2014 17:37:27 +0100 (CET)", "from /spool/local\n\tby e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <dev@dpdk.org> from <chaozhu@linux.vnet.ibm.com>;\n\tSun, 16 Nov 2014 22:17:39 +0530", "from d28dlp03.in.ibm.com (9.184.220.128)\n\tby e28smtp02.in.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tSun, 16 Nov 2014 22:17:36 +0530", "from d28relay05.in.ibm.com (d28relay05.in.ibm.com [9.184.220.62])\n\tby d28dlp03.in.ibm.com (Postfix) with ESMTP id 4D9091258023\n\tfor <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:42 +0530 (IST)", "from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63])\n\tby d28relay05.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tsAGGmAD757868450 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:18:11 +0530", "from d28av01.in.ibm.com (localhost [127.0.0.1])\n\tby d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tsAGGlahU030397 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:36 +0530", "from os_controller.crl.ibm.com ([9.186.57.97])\n\tby d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tsAGGlP35029091 for <dev@dpdk.org>; Sun, 16 Nov 2014 22:17:35 +0530" ], "From": "Chao Zhu <chaozhu@linux.vnet.ibm.com>", "To": "dev@dpdk.org", "Date": "Sun, 16 Nov 2014 23:48:17 -0500", "Message-Id": "<1416199705-24150-5-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "References": "<1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "14111616-0005-0000-0000-0000022A38F8", "Subject": "[dpdk-dev] [PATCH v2 04/12] Add CPU cycle operations for IBM Power\n\tarchitecture", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "IBM Power architecture doesn't have TSC register to get CPU cycles. This\npatch implements the time base register read instead of TSC register of\nx86 on IBM Power architecture.\n\nSigned-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>\n---\n .../common/include/arch/ppc_64/rte_cycles.h | 86 ++++++++++++++++++++\n 1 files changed, 86 insertions(+), 0 deletions(-)\n create mode 100644 lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h", "diff": "diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h\nnew file mode 100644\nindex 0000000..ed66b48\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h\n@@ -0,0 +1,86 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_CYCLES_PPC_64_H_\n+#define _RTE_CYCLES_PPC_64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_cycles.h\"\n+\n+/**\n+ * Read the time base register.\n+ *\n+ * @return\n+ * The time base for this lcore.\n+ */\n+static inline uint64_t\n+rte_rdtsc(void)\n+{\n+\tunion {\n+\t\tuint64_t tsc_64;\n+\t\tstruct {\n+\t\t\tuint32_t hi_32;\n+\t\t\tuint32_t lo_32;\n+\t\t};\n+\t} tsc;\n+\tuint32_t tmp;\n+\tasm volatile(\n+\t\t\t\"0:\\n\"\n+\t\t\t\"mftbu %[hi32]\\n\"\n+\t\t\t\"mftb %[lo32]\\n\"\n+\t\t\t\"mftbu %[tmp]\\n\"\n+\t\t\t\"cmpw %[tmp],%[hi32]\\n\"\n+\t\t\t\"bne 0b\\n\"\n+\t\t\t: [hi32] \"=r\"(tsc.hi_32), [lo32] \"=r\"(tsc.lo_32), [tmp] \"=r\"(tmp)\n+\t\t );\n+\treturn tsc.tsc_64;\n+}\n+\n+static inline uint64_t\n+rte_rdtsc_precise(void)\n+{\n+\trte_mb();\n+\treturn rte_rdtsc();\n+}\n+\n+static inline uint64_t\n+rte_get_tsc_cycles(void) { return rte_rdtsc(); }\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CYCLES_PPC_64_H_ */\n+\n", "prefixes": [ "dpdk-dev", "v2", "04/12" ] }