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GET /api/patches/128760/?format=api
{ "id": 128760, "url": "https://patches.dpdk.org/api/patches/128760/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230615201335.919563-2-wathsala.vithanage@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230615201335.919563-2-wathsala.vithanage@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230615201335.919563-2-wathsala.vithanage@arm.com", "date": "2023-06-15T20:13:35", "name": "[RFC] ring: further performance improvements with C11", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "46ca1a9e2cae8dee0894c2edd8e3a79ff0d8961c", "submitter": { "id": 2969, "url": "https://patches.dpdk.org/api/people/2969/?format=api", "name": "Wathsala Wathawana Vithanage", "email": "wathsala.vithanage@arm.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230615201335.919563-2-wathsala.vithanage@arm.com/mbox/", "series": [ { "id": 28547, "url": "https://patches.dpdk.org/api/series/28547/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=28547", "date": "2023-06-15T20:13:35", "name": "[RFC] ring: further performance improvements with C11", "version": 1, "mbox": "https://patches.dpdk.org/series/28547/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/128760/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/128760/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8761742CCA;\n\tThu, 15 Jun 2023 22:14:01 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 695A542C54;\n\tThu, 15 Jun 2023 22:13:53 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id 570CE41156\n for <dev@dpdk.org>; Thu, 15 Jun 2023 22:13:52 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 06D202F4;\n Thu, 15 Jun 2023 13:14:36 -0700 (PDT)", "from ampere-altra-2-1.usa.Arm.com (ampere-altra-2-1.usa.arm.com\n [10.118.91.158])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BACE43F663;\n Thu, 15 Jun 2023 13:13:51 -0700 (PDT)" ], "From": "Wathsala Vithanage <wathsala.vithanage@arm.com>", "To": "honnappa.nagarahalli@arm.com, konstantin.v.ananyev@yandex.ru,\n thomas@monjalon.net, ruifeng.wang@arm.com", "Cc": "dev@dpdk.org, nd@arm.com, Wathsala Vithanage <wathsala.vithanage@arm.com>", "Subject": "[RFC] ring: further performance improvements with C11", "Date": "Thu, 15 Jun 2023 20:13:35 +0000", "Message-Id": "<20230615201335.919563-2-wathsala.vithanage@arm.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230615201335.919563-1-wathsala.vithanage@arm.com>", "References": "<20230615201335.919563-1-wathsala.vithanage@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "For improved performance over the current C11 based ring implementation\nfollowing changes were made.\n(1) Replace tail store with RELEASE semantics in __rte_ring_update_tail\nwith a RELEASE fence. Replace load of the tail with ACQUIRE semantics \nin __rte_ring_move_prod_head and __rte_ring_move_cons_head with ACQUIRE\nfences.\n(2) Remove ACQUIRE fences between load of the old_head and load of the\ncons_tail in __rte_ring_move_prod_head and __rte_ring_move_cons_head.\nThese two fences are not required for the safety of the ring library.\n\nSigned-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\n---\n .mailmap | 1 +\n lib/ring/rte_ring_c11_pvt.h | 35 ++++++++++++++++++++---------------\n 2 files changed, 21 insertions(+), 15 deletions(-)", "diff": "diff --git a/.mailmap b/.mailmap\nindex 4018f0fc47..367115d134 100644\n--- a/.mailmap\n+++ b/.mailmap\n@@ -1430,6 +1430,7 @@ Walter Heymans <walter.heymans@corigine.com>\n Wang Sheng-Hui <shhuiw@gmail.com>\n Wangyu (Eric) <seven.wangyu@huawei.com>\n Waterman Cao <waterman.cao@intel.com>\n+Wathsala Vithanage <wathsala.vithanage@arm.com>\n Weichun Chen <weichunx.chen@intel.com>\n Wei Dai <wei.dai@intel.com>\n Weifeng Li <liweifeng96@126.com>\ndiff --git a/lib/ring/rte_ring_c11_pvt.h b/lib/ring/rte_ring_c11_pvt.h\nindex f895950df4..63fe58ce9e 100644\n--- a/lib/ring/rte_ring_c11_pvt.h\n+++ b/lib/ring/rte_ring_c11_pvt.h\n@@ -16,6 +16,13 @@ __rte_ring_update_tail(struct rte_ring_headtail *ht, uint32_t old_val,\n \t\tuint32_t new_val, uint32_t single, uint32_t enqueue)\n {\n \tRTE_SET_USED(enqueue);\n+\t/*\n+\t * Updating of ht->tail cannot happen before elements are added to or\n+\t * removed from the ring, as it could result in data races between\n+\t * producer and consumer threads. Therefore we need a release\n+\t * barrier here.\n+\t */\n+\trte_atomic_thread_fence(__ATOMIC_RELEASE);\n \n \t/*\n \t * If there are other enqueues/dequeues in progress that preceded us,\n@@ -24,7 +31,7 @@ __rte_ring_update_tail(struct rte_ring_headtail *ht, uint32_t old_val,\n \tif (!single)\n \t\trte_wait_until_equal_32(&ht->tail, old_val, __ATOMIC_RELAXED);\n \n-\t__atomic_store_n(&ht->tail, new_val, __ATOMIC_RELEASE);\n+\t__atomic_store_n(&ht->tail, new_val, __ATOMIC_RELAXED);\n }\n \n /**\n@@ -66,14 +73,8 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,\n \t\t/* Reset n to the initial burst count */\n \t\tn = max;\n \n-\t\t/* Ensure the head is read before tail */\n-\t\t__atomic_thread_fence(__ATOMIC_ACQUIRE);\n-\n-\t\t/* load-acquire synchronize with store-release of ht->tail\n-\t\t * in update_tail.\n-\t\t */\n \t\tcons_tail = __atomic_load_n(&r->cons.tail,\n-\t\t\t\t\t__ATOMIC_ACQUIRE);\n+\t\t\t\t\t__ATOMIC_RELAXED);\n \n \t\t/* The subtraction is done between two unsigned 32bits value\n \t\t * (the result is always modulo 32 bits even if we have\n@@ -100,6 +101,11 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,\n \t\t\t\t\t0, __ATOMIC_RELAXED,\n \t\t\t\t\t__ATOMIC_RELAXED);\n \t} while (unlikely(success == 0));\n+\t/*\n+\t * Ensure that updates to the ring doesn't rise above\n+\t * load of the new_head in SP and MP cases.\n+\t */\n+\trte_atomic_thread_fence(__ATOMIC_ACQUIRE);\n \treturn n;\n }\n \n@@ -142,14 +148,8 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,\n \t\t/* Restore n as it may change every loop */\n \t\tn = max;\n \n-\t\t/* Ensure the head is read before tail */\n-\t\t__atomic_thread_fence(__ATOMIC_ACQUIRE);\n-\n-\t\t/* this load-acquire synchronize with store-release of ht->tail\n-\t\t * in update_tail.\n-\t\t */\n \t\tprod_tail = __atomic_load_n(&r->prod.tail,\n-\t\t\t\t\t__ATOMIC_ACQUIRE);\n+\t\t\t\t\t__ATOMIC_RELAXED);\n \n \t\t/* The subtraction is done between two unsigned 32bits value\n \t\t * (the result is always modulo 32 bits even if we have\n@@ -175,6 +175,11 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,\n \t\t\t\t\t\t\t0, __ATOMIC_RELAXED,\n \t\t\t\t\t\t\t__ATOMIC_RELAXED);\n \t} while (unlikely(success == 0));\n+\t/*\n+\t * Ensure that updates to the ring doesn't rise above\n+\t * load of the new_head in SP and MP cases.\n+\t */\n+\trte_atomic_thread_fence(__ATOMIC_ACQUIRE);\n \treturn n;\n }\n \n", "prefixes": [ "RFC" ] }