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GET /api/patches/128637/?format=api
{ "id": 128637, "url": "https://patches.dpdk.org/api/patches/128637/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230613165845.19109-5-viacheslavo@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230613165845.19109-5-viacheslavo@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230613165845.19109-5-viacheslavo@nvidia.com", "date": "2023-06-13T16:58:44", "name": "[v2,4/5] net/mlx5: add comprehensive send completion trace", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7ffd8a852100c4c257230df0d8d9282a6e92a559", "submitter": { "id": 1926, "url": "https://patches.dpdk.org/api/people/1926/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230613165845.19109-5-viacheslavo@nvidia.com/mbox/", "series": [ { "id": 28494, "url": "https://patches.dpdk.org/api/series/28494/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=28494", "date": "2023-06-13T16:58:42", "name": "net/mlx5: introduce Tx datapath tracing", "version": 2, "mbox": "https://patches.dpdk.org/series/28494/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/128637/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/128637/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CD10842CA7;\n\tTue, 13 Jun 2023 18:59:41 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CC26542BFE;\n\tTue, 13 Jun 2023 18:59:25 +0200 (CEST)", "from NAM04-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam04on2058.outbound.protection.outlook.com [40.107.101.58])\n by mails.dpdk.org (Postfix) with ESMTP id 1050A42D10\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "To": "<dev@dpdk.org>", "Subject": "[PATCH v2 4/5] net/mlx5: add comprehensive send completion trace", "Date": "Tue, 13 Jun 2023 19:58:44 +0300", "Message-ID": "<20230613165845.19109-5-viacheslavo@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20230613165845.19109-1-viacheslavo@nvidia.com>", "References": "<20230420100803.494-1-viacheslavo@nvidia.com>\n <20230613165845.19109-1-viacheslavo@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT103:EE_|CH0PR12MB5284:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4983cfeb-0a8b-4148-f78e-08db6c2f88a6", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 1COEwsR0rix8MPIYhlraFO8s5mQl4vdaQ6Jhi2SHUQa5P6uNsPlWIA/8vVUrD51SgXTzht0RhnskiFj0R9iGTnKI7r7kU191+2M/Wy12emhTwlTbeZ3GoRvXURX6NXOA+HK3FmLXxSM8OD2+vE3ZwerzGm43l535Iqa0Jzf4CeZ5dZuw0Xie21s/GdUutn5xVZ8HJ2VYMLK557BRBUHwMVPNJnjCJkCkJTNe+ZaQHec/SdslmNsl+PdNT0ajCktIL1z6RZROddfYLNMXo8u+Q7UMRNkAmwSJdqAVkEDfGtLLfJO+S/lj1MtQo17sVNjgRb3uHe51bQ/cqHHNX78VZd7hf7FOKGH1IpgFP52V1wjdA1XY2d78o56dIVCQ6jKBuhHcFDuiSJ3sUZwZU+WgAW6gI2/iswAQ+KMjjKiR3AEihDj/1miw/ezblmBi646rr9mDC49VC4uA2imrw1i1d4mgldAsKQY+FMeJaSOE/+M7sxsXNIBYTJwYSplxDUIhWSCQJlkN9v7XS7tOuugE5s2pSjXKqZw6MLrgbeyGWzRtjmJif+JcGQh8jTl/3YtvQPXq1aJ36z4S0JG+0awkJxqE6vBBD73kktBocWAuDGq4Ms9D8/HCEt8mqsphKBGn2bZbqh7Jf/mqzrcpFsaaP/NgppdUnEOCyQg10qVXsUKhZNjXLtUJ1CZTf3MYCZjcDlOoFmFiMDafdOvzsRa7xlHT3GJz/gjitZr+8KvYmC/I55ef2iuWYMge5mkVs0r5", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(376002)(346002)(136003)(396003)(39860400002)(451199021)(40470700004)(46966006)(36840700001)(40460700003)(336012)(83380400001)(40480700001)(36860700001)(426003)(55016003)(47076005)(356005)(70206006)(478600001)(70586007)(6916009)(1076003)(26005)(6666004)(2616005)(186003)(6286002)(16526019)(86362001)(7696005)(2906002)(8676002)(8936002)(5660300002)(7636003)(82740400003)(41300700001)(36756003)(316002)(82310400005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Jun 2023 16:59:21.3557 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4983cfeb-0a8b-4148-f78e-08db6c2f88a6", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT103.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH0PR12MB5284", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "There is the demand to trace the send completions of\nevery WQE if time scheduling is enabled.\n\nThe patch extends the size of completion queue and\nrequests completion on every issued WQE in the\nsend queue. As the result hardware provides CQE on\neach completed WQE and driver is able to fetch\ncompletion timestamp for dedicated operation.\n\nThe add code is under conditional compilation\nRTE_ENABLE_TRACE_FP flag and does not impact the\nrelease code.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_verbs.c | 8 +++-\n drivers/net/mlx5/mlx5_devx.c | 8 +++-\n drivers/net/mlx5/mlx5_tx.h | 63 +++++++++++++++++++++++++++--\n 3 files changed, 71 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c\nindex 7233c2c7fa..b54f3ccd9a 100644\n--- a/drivers/net/mlx5/linux/mlx5_verbs.c\n+++ b/drivers/net/mlx5/linux/mlx5_verbs.c\n@@ -968,8 +968,12 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\n-\tcqe_n = desc / MLX5_TX_COMP_THRESH +\n-\t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n+\tif (__rte_trace_point_fp_is_enabled() &&\n+\t txq_data->offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP)\n+\t\tcqe_n = UINT16_MAX / 2 - 1;\n+\telse\n+\t\tcqe_n = desc / MLX5_TX_COMP_THRESH +\n+\t\t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n \ttxq_obj->cq = mlx5_glue->create_cq(priv->sh->cdev->ctx, cqe_n,\n \t\t\t\t\t NULL, NULL, 0);\n \tif (txq_obj->cq == NULL) {\ndiff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c\nindex 4369d2557e..5082a7e178 100644\n--- a/drivers/net/mlx5/mlx5_devx.c\n+++ b/drivers/net/mlx5/mlx5_devx.c\n@@ -1465,8 +1465,12 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)\n \tMLX5_ASSERT(ppriv);\n \ttxq_obj->txq_ctrl = txq_ctrl;\n \ttxq_obj->dev = dev;\n-\tcqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +\n-\t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n+\tif (__rte_trace_point_fp_is_enabled() &&\n+\t txq_data->offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP)\n+\t\tcqe_n = UINT16_MAX / 2 - 1;\n+\telse\n+\t\tcqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +\n+\t\t\t1 + MLX5_TX_COMP_THRESH_INLINE_DIV;\n \tlog_desc_n = log2above(cqe_n);\n \tcqe_n = 1UL << log_desc_n;\n \tif (cqe_n > UINT16_MAX) {\ndiff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex 7f624de58e..9f29df280f 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -728,6 +728,54 @@ mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,\n \t}\n }\n \n+/**\n+ * Set completion request flag for all issued WQEs.\n+ * This routine is intended to be used with enabled fast path tracing\n+ * and send scheduling on time to provide the detailed report in trace\n+ * for send completions on every WQE.\n+ *\n+ * @param txq\n+ * Pointer to TX queue structure.\n+ * @param loc\n+ * Pointer to burst routine local context.\n+ * @param olx\n+ * Configured Tx offloads mask. It is fully defined at\n+ * compile time and may be used for optimization.\n+ */\n+static __rte_always_inline void\n+mlx5_tx_request_completion_trace(struct mlx5_txq_data *__rte_restrict txq,\n+\t\t\t\t struct mlx5_txq_local *__rte_restrict loc,\n+\t\t\t\t unsigned int olx)\n+{\n+\tuint16_t head = txq->elts_comp;\n+\n+\twhile (txq->wqe_comp != txq->wqe_ci) {\n+\t\tvolatile struct mlx5_wqe *wqe;\n+\t\tuint32_t wqe_n;\n+\n+\t\tMLX5_ASSERT(loc->wqe_last);\n+\t\twqe = txq->wqes + (txq->wqe_comp & txq->wqe_m);\n+\t\tif (wqe == loc->wqe_last) {\n+\t\t\thead = txq->elts_head;\n+\t\t\thead +=\tMLX5_TXOFF_CONFIG(INLINE) ?\n+\t\t\t\t0 : loc->pkts_sent - loc->pkts_copy;\n+\t\t\ttxq->elts_comp = head;\n+\t\t}\n+\t\t/* Completion request flag was set on cseg constructing. */\n+#ifdef RTE_LIBRTE_MLX5_DEBUG\n+\t\ttxq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |\n+\t\t\t (wqe->cseg.opcode >> 8) << 16;\n+#else\n+\t\ttxq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;\n+#endif\n+\t\t/* A CQE slot must always be available. */\n+\t\tMLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);\n+\t\t/* Advance to the next WQE in the queue. */\n+\t\twqe_n = rte_be_to_cpu_32(wqe->cseg.sq_ds) & 0x3F;\n+\t\ttxq->wqe_comp += RTE_ALIGN(wqe_n, 4) / 4;\n+\t}\n+}\n+\n /**\n * Build the Control Segment with specified opcode:\n * - MLX5_OPCODE_SEND\n@@ -754,7 +802,7 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,\n \t\t struct mlx5_wqe *__rte_restrict wqe,\n \t\t unsigned int ds,\n \t\t unsigned int opcode,\n-\t\t unsigned int olx __rte_unused)\n+\t\t unsigned int olx)\n {\n \tstruct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;\n \n@@ -763,8 +811,12 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,\n \t\topcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;\n \tcs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);\n \tcs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);\n-\tcs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<\n-\t\t\t MLX5_COMP_MODE_OFFSET);\n+\tif (MLX5_TXOFF_CONFIG(TXPP) && __rte_trace_point_fp_is_enabled())\n+\t\tcs->flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n+\t\t\t\t MLX5_COMP_MODE_OFFSET);\n+\telse\n+\t\tcs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<\n+\t\t\t\t MLX5_COMP_MODE_OFFSET);\n \tcs->misc = RTE_BE32(0);\n \tif (__rte_trace_point_fp_is_enabled() && !loc->pkts_sent)\n \t\trte_pmd_mlx5_trace_tx_entry(txq->port_id, txq->idx);\n@@ -3662,7 +3714,10 @@ mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,\n \tif (unlikely(loc.pkts_sent == loc.pkts_loop))\n \t\tgoto burst_exit;\n \t/* Request CQE generation if limits are reached. */\n-\tmlx5_tx_request_completion(txq, &loc, olx);\n+\tif (MLX5_TXOFF_CONFIG(TXPP) && __rte_trace_point_fp_is_enabled())\n+\t\tmlx5_tx_request_completion_trace(txq, &loc, olx);\n+\telse\n+\t\tmlx5_tx_request_completion(txq, &loc, olx);\n \t/*\n \t * Ring QP doorbell immediately after WQE building completion\n \t * to improve latencies. The pure software related data treatment\n", "prefixes": [ "v2", "4/5" ] }