Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/128201/?format=api
{ "id": 128201, "url": "https://patches.dpdk.org/api/patches/128201/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230606110710.4116732-3-dongzhou@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230606110710.4116732-3-dongzhou@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230606110710.4116732-3-dongzhou@nvidia.com", "date": "2023-06-06T11:07:10", "name": "[v1,2/2] net/mlx5/hws: add support for infiniband BTH match", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ec6b8aa7de389d6c44095f69ffdc409e88981b21", "submitter": { "id": 2011, "url": "https://patches.dpdk.org/api/people/2011/?format=api", "name": "Dong Zhou", "email": "dongzhou@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230606110710.4116732-3-dongzhou@nvidia.com/mbox/", "series": [ { "id": 28370, "url": "https://patches.dpdk.org/api/series/28370/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=28370", "date": "2023-06-06T11:07:08", "name": "mlx5 supports InfiniBand BTH item match", "version": 1, "mbox": "https://patches.dpdk.org/series/28370/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/128201/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/128201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B48C542C3E;\n\tTue, 6 Jun 2023 13:07:53 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 70B86410F2;\n\tTue, 6 Jun 2023 13:07:50 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2072.outbound.protection.outlook.com [40.107.94.72])\n by mails.dpdk.org (Postfix) with ESMTP id AE9B9410DD\n for <dev@dpdk.org>; Tue, 6 Jun 2023 13:07:49 +0200 (CEST)", "from DM5PR07CA0088.namprd07.prod.outlook.com (2603:10b6:4:ae::17) by\n DM4PR12MB8559.namprd12.prod.outlook.com (2603:10b6:8:17d::8) with\n Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6455.33; Tue, 6 Jun 2023 11:07:47 +0000", "from DM6NAM11FT024.eop-nam11.prod.protection.outlook.com\n (2603:10b6:4:ae:cafe::e6) by DM5PR07CA0088.outlook.office365.com\n (2603:10b6:4:ae::17) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.33 via Frontend\n Transport; Tue, 6 Jun 2023 11:07:47 +0000", "from mail.nvidia.com (216.228.117.160) by\n DM6NAM11FT024.mail.protection.outlook.com (10.13.172.159) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6455.35 via Frontend Transport; Tue, 6 Jun 2023 11:07:47 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 6 Jun 2023\n 04:07:31 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 6 Jun 2023\n 04:07:29 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=m8NEAMUq4r6J6SPkPF2MVjzNGwGJ5vxNmkIIs/oMj4IgIlq9ELynJPmX5pNc/67t4xgdWhx+IJDV91nQ2xgwSW8D9UP4Tg+/q/Qxe1qqaSQ4ZjKK/SrllZnDy8KBrv/FuHibc6lxkFyN1ZpasUpcs7PZCNRvYGkIRkbC5Wes+cMSK2lS9svdBKKHRWIwe5ACORtuDThY0w89NqWYTgt36mrSKIS1VLbRP2r+Ep4MXakb/cznvT/PpV/PcTFUk7RIZNysKX8n5coir8jaRwVrerzdU24l0h30HLG+zWVR5WUKgrIkdpVIgqY3PGuBA9bNSI8nNCpZNilKnDj3VHoWIg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=/cAhWcDzqtUXa/rGn0ddg9WxEobXTc7QHeax3Uo5XKE=;\n b=HVI717COMc5if19gOU6ZfpJrDEALnUKRsmy8hQT5S67xba0sq/JKMQtj9Ao6lkz5rsqtkTHzzAoPoLbHCosBFB8M922KTeylsN7cT7vp540hGX0iQk0XpV9sMT+GJztCKOj8y0A2pnHcx7Z8cZrMltczUbHejvG+WdIi2ocV1Xno3rD0fTWPJbkrTXsBtrVi+AZEebgfj/D/VoXxatDTHoUi/0VTPbbJ4/TrzTI0VWuu6V83+w8RnLsZQW1DjSdUSAeGZaK6XUrTF1t8BYskt5lpmTXA5Mtxqzk3iAln035ecSNy2kH2lQs7i54pM8Dzxf18+cds3CX7o8vQgNxhyA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=/cAhWcDzqtUXa/rGn0ddg9WxEobXTc7QHeax3Uo5XKE=;\n b=biO+YyE2mOZI7oC34fMFG+ptK+P5UqW0C5EIo3YYDntqxm+sePk3fa4CYaiyGXpKoquY1M0nHIZGfn9w3xUQubyVo7aDLkx6k68T3j/fKhlhDMB1QmhZpxDEXbmdBAwgAdGGXAY9V3sH294rHjlvlGHRNsI3Ftim84VjNZVWyDZ1kTKP5XqAp6i/O00fcaF5/UvpxreRVEF8GbNstSl7RL+TeMitIeckopqj5uHdRVLPvJDVHpGDUMKNmBmDb5AFR4xOPntydO6ttsU7JzZkI4ujPunzgJT5fOWdY9r55Mozr/A0DQOWJcgKb4xQD8m6Ve5TbgH4x19V8yJQR0z+jA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Dong Zhou <dongzhou@nvidia.com>", "To": "<orika@nvidia.com>, <valex@nvidia.com>, <viacheslavo@nvidia.com>,\n <thomas@monjalon.net>, Matan Azrad <matan@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v1 2/2] net/mlx5/hws: add support for infiniband BTH match", "Date": "Tue, 6 Jun 2023 14:07:10 +0300", "Message-ID": "<20230606110710.4116732-3-dongzhou@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230606110710.4116732-1-dongzhou@nvidia.com>", "References": "<20230601080001.3310444-1-dongzhou@nvidia.com>\n <20230606110710.4116732-1-dongzhou@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT024:EE_|DM4PR12MB8559:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3c7debc8-2407-4496-1874-08db667e42e7", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n k/BmfDc2JAPt6typWsN7Opi7lhahlZu9ao3BojtePsgT3hZwSVVUhD7yYSZQb80i8cf3hHucWvtKN8eP7sP8DYXzFVykNOaJ4940Jn9uhdBpOyGN/Ee1N7g1Wbc9bPCxE4Qz57mrbiL5GQ0D9qi7k3ar7xe+VXdEPrIhz4/IfiGohkNAdwMBvjp+p2YyBxEiX716U+snD8qWnV94hXvhOLPmrYTgIOb3T5NK06/h5++UPAK1sIrphAaBtSpkOCbxiC69EABC2mmk0gjq9DF7r9E8XVom58RN8xccFqpWerD1yjWgoggs8gxN2q6/tWDC9jZ7eIxkBq49tjuINkgApZ7AZmnG6cXHYjQboSWQw9j5C9+34wjLgQpM3KVa7qSRYL4vIOL/hivdyyMQcnQ6wdyi3dlDKqQJRO6tUHt/4YfBfRDYBnEMj8JYaqqlwaKjKf4ZDsI1iDzdYgWX2d36IioRd0TcrFhgiLyfJajf14Goqy0th3hmar0hy/k814g91BQ7agB6FzYYEQCvks1ZFIGocdbdJNDDC8dtTjNe0Yb7FOtml1AI4lM5woEjWbIFUBMyYk0DfidkBwhCalNZenH0PMakiErLCBRe1ytDuWSRIqdEmRnDainQd+ev31CL+Akiv7VnRUxfVoF3TP0GY/LsyChHV88Cc8Qa9CM/ePc3jErnZsTzgpf9A5iYq6792SJffLDKhF/G4jmRNq8Wk6t2AA9awuWPjA+EVsSncZUfBjGhqZx30ZcJN9Dqmiwn", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(39860400002)(376002)(136003)(346002)(396003)(451199021)(46966006)(40470700004)(36840700001)(86362001)(36756003)(356005)(7636003)(82310400005)(40460700003)(40480700001)(55016003)(6666004)(7696005)(54906003)(110136005)(478600001)(2906002)(82740400003)(26005)(1076003)(186003)(16526019)(2616005)(107886003)(316002)(41300700001)(5660300002)(4326008)(6636002)(70206006)(70586007)(6286002)(36860700001)(83380400001)(336012)(426003)(47076005)(8936002)(8676002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Jun 2023 11:07:47.5848 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3c7debc8-2407-4496-1874-08db667e42e7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT024.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB8559", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds support to match opcode and dst_qp fields in\ninfiniband BTH. Currently, only the RoCEv2 packet is supported,\nthe input BTH match item is defaulted to match one RoCEv2 packet.\n\nSigned-off-by: Dong Zhou <dongzhou@nvidia.com>\nAcked-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 76 ++++++++++++++++++++++++++-\n drivers/net/mlx5/hws/mlx5dr_definer.h | 2 +\n drivers/net/mlx5/mlx5_flow_hw.c | 1 +\n 3 files changed, 78 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex f92d3e8e1f..1a427c9b64 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -10,6 +10,7 @@\n #define ETH_TYPE_IPV6_VXLAN\t0x86DD\n #define ETH_VXLAN_DEFAULT_PORT\t4789\n #define IP_UDP_PORT_MPLS\t6635\n+#define UDP_ROCEV2_PORT\t4791\n #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)\n \n #define STE_NO_VLAN\t0x0\n@@ -171,7 +172,9 @@ struct mlx5dr_definer_conv_data {\n \tX(SET_BE16,\tgre_opt_checksum,\tv->checksum_rsvd.checksum,\trte_flow_item_gre_opt) \\\n \tX(SET,\t\tmeter_color,\t\trte_col_2_mlx5_col(v->color),\trte_flow_item_meter_color) \\\n \tX(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \\\n-\tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp)\n+\tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \\\n+\tX(SET,\t\tib_l4_udp_port,\t\tUDP_ROCEV2_PORT,\trte_flow_item_ib_bth) \\\n+\tX(SET,\t\tib_l4_opcode,\t\tv->hdr.opcode,\t\trte_flow_item_ib_bth)\n \n /* Item set function format */\n #define X(set_type, func_name, value, item_type) \\\n@@ -583,6 +586,16 @@ mlx5dr_definer_mpls_label_set(struct mlx5dr_definer_fc *fc,\n \tmemcpy(tag + fc->byte_off + sizeof(v->label_tc_s), &v->ttl, sizeof(v->ttl));\n }\n \n+static void\n+mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t const void *item_spec,\n+\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_ib_bth *v = item_spec;\n+\n+\tmemcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp));\n+}\n+\n static int\n mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd,\n \t\t\t struct rte_flow_item *item,\n@@ -2041,6 +2054,63 @@ mlx5dr_definer_conv_item_flex_parser(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t struct rte_flow_item *item,\n+\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_ib_bth *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\t/* In order to match on RoCEv2(layer4 ib), we must match\n+\t * on ip_protocol and l4_dport.\n+\t */\n+\tif (!cd->relaxed) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_udp_protocol_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type_bwc, inner);\n+\t\t}\n+\n+\t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ib_l4_udp_port_set;\n+\t\t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n+\t\t}\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->hdr.se || m->hdr.m || m->hdr.padcnt || m->hdr.tver ||\n+\t\tm->hdr.pkey || m->hdr.f || m->hdr.b || m->hdr.rsvd0 ||\n+\t\tm->hdr.a || m->hdr.rsvd1 || !is_mem_zero(m->hdr.psn, 3)) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (m->hdr.opcode) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_OPCODE];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ib_l4_opcode_set;\n+\t\tDR_CALC_SET_HDR(fc, ib_l4, opcode);\n+\t}\n+\n+\tif (!is_mem_zero(m->hdr.dst_qp, 3)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_IB_L4_QPN];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_ib_l4_qp_set;\n+\t\tDR_CALC_SET_HDR(fc, ib_l4, qp);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_match_template *mt,\n@@ -2182,6 +2252,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\titem_flags |= MLX5_FLOW_LAYER_MPLS;\n \t\t\tcd.mpls_idx++;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n+\t\t\tret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_ITEM_IB_BTH;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\trte_errno = ENOTSUP;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex 90ec4ce845..6b645f4cf0 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -134,6 +134,8 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS2_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS3_I,\n \tMLX5DR_DEFINER_FNAME_OKS2_MPLS4_I,\n+\tMLX5DR_DEFINER_FNAME_IB_L4_OPCODE,\n+\tMLX5DR_DEFINER_FNAME_IB_L4_QPN,\n \tMLX5DR_DEFINER_FNAME_MAX,\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 853c94af9c..f9e7f844ea 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -4969,6 +4969,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT:\n \t\tcase RTE_FLOW_ITEM_TYPE_ESP:\n \t\tcase RTE_FLOW_ITEM_TYPE_FLEX:\n+\t\tcase RTE_FLOW_ITEM_TYPE_IB_BTH:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n \t\t\t/*\n", "prefixes": [ "v1", "2/2" ] }