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GET /api/patches/127807/?format=api
{ "id": 127807, "url": "https://patches.dpdk.org/api/patches/127807/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230531184303.946971-1-akozyrev@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230531184303.946971-1-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230531184303.946971-1-akozyrev@nvidia.com", "date": "2023-05-31T18:43:03", "name": "net/mlx5: fix MPRQ stride size to accommodate the headroom", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c4aa1673c0d0b34a273f7a97668065a99cbc423c", "submitter": { "id": 1873, "url": "https://patches.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230531184303.946971-1-akozyrev@nvidia.com/mbox/", "series": [ { "id": 28283, "url": "https://patches.dpdk.org/api/series/28283/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=28283", "date": "2023-05-31T18:43:03", "name": "net/mlx5: fix MPRQ stride size to accommodate the headroom", "version": 1, "mbox": "https://patches.dpdk.org/series/28283/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/127807/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/127807/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 65CBE42BF8;\n\tWed, 31 May 2023 20:43:46 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 00C1140A89;\n\tWed, 31 May 2023 20:43:46 +0200 (CEST)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam04on2053.outbound.protection.outlook.com [40.107.100.53])\n by mails.dpdk.org (Postfix) with ESMTP id 4951F40A82;\n Wed, 31 May 2023 20:43:44 +0200 (CEST)", "from DM6PR17CA0022.namprd17.prod.outlook.com (2603:10b6:5:1b3::35)\n by PH8PR12MB7253.namprd12.prod.outlook.com (2603:10b6:510:226::16) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.22; 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helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<stable@dpdk.org>, <rasland@nvidia.com>, <viacheslavo@nvidia.com>,\n <matan@nvidia.com>, <michaelba@nvidia.com>", "Subject": "[PATCH] net/mlx5: fix MPRQ stride size to accommodate the headroom", "Date": "Wed, 31 May 2023 21:43:03 +0300", "Message-ID": "<20230531184303.946971-1-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT107:EE_|PH8PR12MB7253:EE_", "X-MS-Office365-Filtering-Correlation-Id": "91803b0d-a5b0-4f5a-f7b2-08db6206f4d2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n /3wfUgg/DFi2WQw/hYCuwOwcXhCLhRNc9pcmZzGRzAUFKaKAkbvjVyfPAHk5UdHTqhu/1asWf94NCGrWX5Su5KtoMxMFaBIGcwAvuTq4mTs00W1gApKmz0KdVvMbPoP7mdRoSN5Tqg9aR2ymaeVuvjXs5WKTlDDT2sH8iNCHCpopDIOnlzIPySVB5Tv7bEFL/OPAsL827UYTdpqxI7Jmpbw+AurK1VPEiPTBGXz9j9t5MlPxmZTuB46wK6bhJeHAFtOLROf2roW5PViHm5TSgL/zZk4WtuLDxWelS2mSljbeoeC4y5YchOlpkKTzJYUbhG9z+wP3STF2DOdMeigvmykkL57SmDOHhfIOrLrU0HnfZyg9KltkpxxtFGH+d5YpsUKMmds/1RoCBbgb/LL/e/sgkSV5W3713w7AZjTnysqbg3f+yOOHn7gAilfxy2PFWQ34eyeT/J+pf+uUC66P6KUMCsggus9kpENC3Xhmc9brDT1b0s42PHdGXcbV8aNJsoV0+IDkngwE3kd/IVltZPABgT4XUzn5vOYKtXPtgWfVqrJRudXxOEMs6M0eychRbbjauvboFZXx8m2iPCU2XWOs7/ATMQ+1ES2AavTmZsDbc4IuujjKWSOGJWekpi9+zU+F5lo62eb5eHjwt0+zZW6P11/GtD4wSzmDo1093vl35y4lr+g33NrHhJeVEI9zffK0wazQ7piAOdktQRGEgajYIKEmMdBEec9LDlv2tZ+sM3ejd/EYrvREytNFUyMV", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230028)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199021)(46966006)(36840700001)(40470700004)(82310400005)(316002)(356005)(7636003)(1076003)(186003)(16526019)(82740400003)(40480700001)(8676002)(8936002)(41300700001)(107886003)(40460700003)(6666004)(5660300002)(26005)(47076005)(36756003)(83380400001)(36860700001)(4326008)(2906002)(6916009)(70206006)(70586007)(54906003)(2616005)(86362001)(336012)(450100002)(478600001)(426003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 May 2023 18:43:41.8443 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 91803b0d-a5b0-4f5a-f7b2-08db6206f4d2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT107.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB7253", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The space for the headroom is reserved at the end of every MPRQ stride\nfor the next packet. The Rx burst logic is to copy any overlapping\npacket data if there is an overlap with this reserved headroom space.\nBut it is not possible if the headroom size is bigger than the whole\nstride. Adjust the stride size to make sure the stride size is greater\nthan the headroom size.\n\nFixes: 34776af600df (\"net/mlx5: fix MPRQ stride devargs adjustment\")\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 1 +\n drivers/net/mlx5/mlx5_rxq.c | 41 +++++++++++++++++++++++++------------\n 2 files changed, 29 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex a75fa1b7f0..592e4053c5 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2597,6 +2597,7 @@ mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist,\n \tconfig->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n \tconfig->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n \tconfig->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;\n+\tconfig->mprq.log_stride_size = MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE;\n \tconfig->log_hp_size = MLX5_ARG_UNSET;\n \tconfig->std_delay_drop = 0;\n \tconfig->hp_delay_drop = 0;\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex ad8fd13cbe..da31b9a106 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1604,23 +1604,38 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n \t} else {\n \t\t*actual_log_stride_num = config->mprq.log_stride_num;\n \t}\n-\tif (config->mprq.log_stride_size) {\n-\t\t/* Checks if chosen size of stride is in supported range. */\n-\t\tif (config->mprq.log_stride_size > log_max_stride_size ||\n-\t\t config->mprq.log_stride_size < log_min_stride_size) {\n-\t\t\t*actual_log_stride_size = log_def_stride_size;\n+\t/* Checks if chosen size of stride is in supported range. */\n+\tif (config->mprq.log_stride_size > log_max_stride_size ||\n+\t config->mprq.log_stride_size < log_min_stride_size) {\n+\t\t*actual_log_stride_size = log_def_stride_size;\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Port %u Rx queue %u size of a stride for Multi-Packet RQ is out of range, setting default value (%u)\",\n+\t\t\tdev->data->port_id, idx,\n+\t\t\tRTE_BIT32(log_def_stride_size));\n+\t} else {\n+\t\t*actual_log_stride_size = config->mprq.log_stride_size;\n+\t}\n+\t/* Make the stride fit the mbuf size by default. */\n+\tif (*actual_log_stride_size == MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE) {\n+\t\tif (min_mbuf_size <= RTE_BIT32(log_max_stride_size)) {\n \t\t\tDRV_LOG(WARNING,\n-\t\t\t\t\"Port %u Rx queue %u size of a stride for Multi-Packet RQ is out of range, setting default value (%u)\",\n-\t\t\t\tdev->data->port_id, idx,\n-\t\t\t\tRTE_BIT32(log_def_stride_size));\n+\t\t\t\t\"Port %u Rx queue %u size of a stride for Multi-Packet RQ is adjusted to match the mbuf size (%u)\",\n+\t\t\t\tdev->data->port_id, idx, min_mbuf_size);\n+\t\t\t*actual_log_stride_size = log2above(min_mbuf_size);\n \t\t} else {\n-\t\t\t*actual_log_stride_size = config->mprq.log_stride_size;\n+\t\t\tgoto unsupport;\n \t\t}\n-\t} else {\n-\t\tif (min_mbuf_size <= RTE_BIT32(log_max_stride_size))\n-\t\t\t*actual_log_stride_size = log2above(min_mbuf_size);\n-\t\telse\n+\t}\n+\t/* Make sure the stride size is greater than the headroom. */\n+\tif (RTE_BIT32(*actual_log_stride_size) < RTE_PKTMBUF_HEADROOM) {\n+\t\tif (RTE_BIT32(log_max_stride_size) > RTE_PKTMBUF_HEADROOM) {\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"Port %u Rx queue %u size of a stride for Multi-Packet RQ is adjusted to accomodate the headroom (%u)\",\n+\t\t\t\tdev->data->port_id, idx, RTE_PKTMBUF_HEADROOM);\n+\t\t\t*actual_log_stride_size = log2above(RTE_PKTMBUF_HEADROOM);\n+\t\t} else {\n \t\t\tgoto unsupport;\n+\t\t}\n \t}\n \tlog_stride_wqe_size = *actual_log_stride_num + *actual_log_stride_size;\n \t/* Check if WQE buffer size is supported by hardware. */\n", "prefixes": [] }