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GET /api/patches/126589/?format=api
{ "id": 126589, "url": "https://patches.dpdk.org/api/patches/126589/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-23-qiming.yang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-23-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-23-qiming.yang@intel.com", "date": "2023-04-27T06:19:53", "name": "[22/30] net/ice/base: return CGU PLL config function params", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ed95718c09c1eccaaeb4912d75402c3a88d62b93", "submitter": { "id": 522, "url": "https://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-23-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "https://patches.dpdk.org/api/series/27885/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "https://patches.dpdk.org/series/27885/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126589/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/126589/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D005542A08;\n\tThu, 27 Apr 2023 08:40:23 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1478842FEA;\n\tThu, 27 Apr 2023 08:38:27 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id B96E442FC8\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:24 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:24 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:22 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577504; x=1714113504;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=WPdX2SsrZtrAbwvgLYQvSEDZ9HaULQrivVSfqQ8+2JU=;\n b=jYubxelFjPoXA0uOiR/6z3aueD0zzehd3Hs8qd76Pe5SoW+3R8UKNYf+\n Jaf95oiIENsXQVT4GvivylX3ZaFqFfECZfvNCsizXaNS+XhIZ6XIlIVGk\n NE1ef3yaDoM9K9CcEft355vif7HSfHPLTDVG5965ZwC4lbpCYkJAUKF8+\n C1htZUf8zzqBOsHMSkqRS1GAE5uX6mD7GOOFEwS+jlG7bVn06+F00mSkp\n AzFHsPrQa4JatnoClrGYcD5BhIEBm+yqVd+DReIT0pyVxt4WRs52YCTtH\n g1HrBChNIxjLNgB6lQSah3VXpG7ySSVQqzrl4eiXLLQFvqVoZUkAySFeZ A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324381\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324381\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845863\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845863\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Karol Kolacinski <karol.kolacinski@intel.com>", "Subject": "[PATCH 22/30] net/ice/base: return CGU PLL config function params", "Date": "Thu, 27 Apr 2023 06:19:53 +0000", "Message-Id": "<20230427062001.478032-23-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Change params in ice_cfg_cgu_pll_e822 to pointers to return real values\nof frequency and clock source.\nRemove static from frequency and clock source conversion functions.\n\nSigned-off-by: Karol Kolacinski <karol.kolacinski@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 39 ++++++++++++++++++-------------\n drivers/net/ice/base/ice_ptp_hw.h | 4 ++--\n 2 files changed, 25 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex f27131efcc..cc6c1f3152 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -218,8 +218,8 @@ static const char *ice_clk_src_str(u8 clk_src)\n * time reference, enabling the PLL which drives the PTP hardware clock.\n */\n enum ice_status\n-ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n-\t\t enum ice_clk_src clk_src)\n+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,\n+\t\t enum ice_clk_src *clk_src)\n {\n \tunion tspll_ro_bwm_lf bwm_lf;\n \tunion nac_cgu_dword19 dw19;\n@@ -228,18 +228,18 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n \tunion nac_cgu_dword9 dw9;\n \tenum ice_status status;\n \n-\tif (clk_freq >= NUM_ICE_TIME_REF_FREQ) {\n-\t\tice_warn(hw, \"Invalid TIME_REF frequency %u\\n\", clk_freq);\n+\tif (*clk_freq >= NUM_ICE_TIME_REF_FREQ) {\n+\t\tice_warn(hw, \"Invalid TIME_REF frequency %u\\n\", *clk_freq);\n \t\treturn ICE_ERR_PARAM;\n \t}\n \n-\tif (clk_src >= NUM_ICE_CLK_SRC) {\n-\t\tice_warn(hw, \"Invalid clock source %u\\n\", clk_src);\n+\tif (*clk_src >= NUM_ICE_CLK_SRC) {\n+\t\tice_warn(hw, \"Invalid clock source %u\\n\", *clk_src);\n \t\treturn ICE_ERR_PARAM;\n \t}\n \n-\tif (clk_src == ICE_CLK_SRC_TCX0 &&\n-\t clk_freq != ICE_TIME_REF_FREQ_25_000) {\n+\tif (*clk_src == ICE_CLK_SRC_TCX0 &&\n+\t *clk_freq != ICE_TIME_REF_FREQ_25_000) {\n \t\tice_warn(hw, \"TCX0 only supports 25 MHz frequency\\n\");\n \t\treturn ICE_ERR_PARAM;\n \t}\n@@ -273,7 +273,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n \t}\n \n \t/* Set the frequency */\n-\tdw9.field.time_ref_freq_sel = clk_freq;\n+\tdw9.field.time_ref_freq_sel = *clk_freq;\n \tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);\n \tif (status)\n \t\treturn status;\n@@ -283,7 +283,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n \tif (status)\n \t\treturn status;\n \n-\tdw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;\n+\tdw19.field.tspll_fbdiv_intgr = e822_cgu_params[*clk_freq].feedback_div;\n \tdw19.field.tspll_ndivratio = 1;\n \n \tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);\n@@ -295,7 +295,7 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n \tif (status)\n \t\treturn status;\n \n-\tdw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;\n+\tdw22.field.time1588clk_div = e822_cgu_params[*clk_freq].post_pll_div;\n \tdw22.field.time1588clk_sel_div2 = 0;\n \n \tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);\n@@ -307,9 +307,9 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n \tif (status)\n \t\treturn status;\n \n-\tdw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;\n-\tdw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;\n-\tdw24.field.time_ref_sel = clk_src;\n+\tdw24.field.ref1588_ck_div = e822_cgu_params[*clk_freq].refclk_pre_div;\n+\tdw24.field.tspll_fbdiv_frac = e822_cgu_params[*clk_freq].frac_n_div;\n+\tdw24.field.time_ref_sel = *clk_src;\n \n \tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n \tif (status)\n@@ -341,6 +341,9 @@ ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n \t\t ice_clk_freq_str(dw9.field.time_ref_freq_sel),\n \t\t bwm_lf.field.plllock_true_lock_cri ? \"locked\" : \"unlocked\");\n \n+\t*clk_freq = (enum ice_time_ref_freq)dw9.field.time_ref_freq_sel;\n+\t*clk_src = (enum ice_clk_src)dw24.field.time_ref_sel;\n+\n \treturn ICE_SUCCESS;\n }\n \n@@ -354,6 +357,8 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)\n {\n \tstruct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;\n \tunion tspll_cntr_bist_settings cntr_bist;\n+\tenum ice_time_ref_freq time_ref_freq;\n+\tenum ice_clk_src clk_src;\n \tenum ice_status status;\n \n \tstatus = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,\n@@ -373,8 +378,9 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)\n \t/* Configure the CGU PLL using the parameters from the function\n \t * capabilities.\n \t */\n-\tstatus = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,\n-\t\t\t\t (enum ice_clk_src)ts_info->clk_src);\n+\ttime_ref_freq = (enum ice_time_ref_freq)ts_info->time_ref;\n+\tclk_src = (enum ice_clk_src)ts_info->clk_src;\n+\tstatus = ice_cfg_cgu_pll_e822(hw, &time_ref_freq, &clk_src);\n \tif (status)\n \t\treturn status;\n \n@@ -2024,6 +2030,7 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port)\n \tif (status)\n \t\treturn status;\n \n+\n \treturn ICE_SUCCESS;\n }\n \ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex f4d64ea02b..4d5d728e26 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -184,8 +184,8 @@ ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port,\n \t\t\t enum ice_ptp_tmr_cmd cmd, bool lock_sbq);\n void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);\n enum ice_status\n-ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n-\t\t enum ice_clk_src clk_src);\n+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq *clk_freq,\n+\t\t enum ice_clk_src *clk_src);\n \n /**\n * ice_e822_time_ref - Get the current TIME_REF from capabilities\n", "prefixes": [ "22/30" ] }