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GET /api/patches/126571/?format=api
{ "id": 126571, "url": "https://patches.dpdk.org/api/patches/126571/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-5-qiming.yang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-5-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-5-qiming.yang@intel.com", "date": "2023-04-27T06:19:35", "name": "[04/30] net/ice/base: update flow seg fields to declared bitmaps", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ca3d59a012eca0d3c67cadd8ceb55bcaaabeb69f", "submitter": { "id": 522, "url": "https://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-5-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "https://patches.dpdk.org/api/series/27885/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "https://patches.dpdk.org/series/27885/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126571/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/126571/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C735A42A08;\n\tThu, 27 Apr 2023 08:38:19 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 09D2C42D5E;\n\tThu, 27 Apr 2023 08:37:55 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id EC3DF42D2D\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:37:52 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:37:52 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:49 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577473; x=1714113473;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=gWentlx+9rzeM7saZOVSLmbcup++26Q6uwOVK0rP5aE=;\n b=XuCBpqA86Pw89qaNgQ/K1UGI5tJrmMeBb5chROGrhB73wESOq8Kx8ySe\n +S60M5LF+G7wBBDOYizN1xdrC6zbMix4QeA5NCCuwevGHAO9qX1unFBiO\n gxzJ4dx47fSWwIkZ2YzEuQMmntWu6OMyfnbUk58zoj94usoofmy94QLaY\n KVEkvHUTqQsnhr63S+sA6bZN5gZ4oMXDoEDtXrvCO8OwwaJACkHNdlOvH\n M3elux7LT9uaw6+Ent4pJt8mT1fDJrkwjsgK31tFeREhMOy6bU86CFQHw\n iLHhlKD6g3aKS7JCU13V/yZoSvo5gCjfUlSfTizIAzImyuLgRugSpCxId w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324269\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324269\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845673\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845673\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Ashish Shah <ashish.n.shah@intel.com>", "Subject": "[PATCH 04/30] net/ice/base: update flow seg fields to declared\n bitmaps", "Date": "Thu, 27 Apr 2023 06:19:35 +0000", "Message-Id": "<20230427062001.478032-5-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "ice_flow_seg_info fields match and range are being used with bit\noperations but not declared as bitmaps. This can cause issues when\ncasting values greater than 32. This change is to declare them as proper\nbitmaps so that the bitmap operations can function as intended.\n\nSigned-off-by: Ashish Shah <ashish.n.shah@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_flow.c | 74 +++++++++++++++++++++++----------\n drivers/net/ice/base/ice_flow.h | 6 ++-\n 2 files changed, 56 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex 5254ee27ed..8db394471c 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -1132,6 +1132,7 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)\n \t\t\tice_and_bitmap(params->ptypes, params->ptypes, src,\n \t\t\t\t ICE_FLOW_PTYPE_MAX);\n \t\t}\n+\n \t\tif ((hdrs & ICE_FLOW_SEG_HDR_IPV4) &&\n \t\t (hdrs & ICE_FLOW_SEG_HDR_IPV_OTHER)) {\n \t\t\tsrc = i ?\n@@ -1371,7 +1372,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw,\n */\n static enum ice_status\n ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n-\t\t u8 seg, enum ice_flow_field fld, u64 match)\n+\t\t u8 seg, enum ice_flow_field fld, ice_bitmap_t *match)\n {\n \tenum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX;\n \tu8 fv_words = (u8)hw->blk[params->blk].es.fvw;\n@@ -1420,7 +1421,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \t\t/* If the sibling field is also included, that field's\n \t\t * mask needs to be included.\n \t\t */\n-\t\tif (match & BIT(sib))\n+\t\tif (ice_is_bit_set(match, sib))\n \t\t\tsib_mask = ice_flds_info[sib].mask;\n \t\tbreak;\n \tcase ICE_FLOW_FIELD_IDX_IPV6_TTL:\n@@ -1451,7 +1452,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \t\t/* If the sibling field is also included, that field's\n \t\t * mask needs to be included.\n \t\t */\n-\t\tif (match & BIT(sib))\n+\t\tif (ice_is_bit_set(match, sib))\n \t\t\tsib_mask = ice_flds_info[sib].mask;\n \t\tbreak;\n \tcase ICE_FLOW_FIELD_IDX_IPV4_SA:\n@@ -1722,15 +1723,16 @@ ice_flow_create_xtrct_seq(struct ice_hw *hw,\n \t}\n \n \tfor (i = 0; i < params->prof->segs_cnt; i++) {\n-\t\tu64 match = params->prof->segs[i].match;\n+\t\tice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX);\n \t\tenum ice_flow_field j;\n \n-\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&match,\n-\t\t\t\t ICE_FLOW_FIELD_IDX_MAX) {\n+\t\tice_cp_bitmap(match, params->prof->segs[i].match,\n+\t\t\t ICE_FLOW_FIELD_IDX_MAX);\n+\t\tice_for_each_set_bit(j, match, ICE_FLOW_FIELD_IDX_MAX) {\n \t\t\tstatus = ice_flow_xtract_fld(hw, params, i, j, match);\n \t\t\tif (status)\n \t\t\t\treturn status;\n-\t\t\tice_clear_bit(j, (ice_bitmap_t *)&match);\n+\t\t\tice_clear_bit(j, match);\n \t\t}\n \n \t\t/* Process raw matching bytes */\n@@ -1789,7 +1791,7 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params)\n \t\tstruct ice_flow_seg_info *seg = ¶ms->prof->segs[i];\n \t\tu16 j;\n \n-\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n+\t\tice_for_each_set_bit(j, seg->match,\n \t\t\t\t (u16)ICE_FLOW_FIELD_IDX_MAX) {\n \t\t\tstruct ice_flow_fld_info *fld = &seg->fields[j];\n \n@@ -1932,7 +1934,10 @@ ice_flow_find_prof_conds(struct ice_hw *hw, enum ice_block blk,\n \t\t\tfor (i = 0; i < segs_cnt; i++)\n \t\t\t\tif (segs[i].hdrs != p->segs[i].hdrs ||\n \t\t\t\t ((conds & ICE_FLOW_FIND_PROF_CHK_FLDS) &&\n-\t\t\t\t segs[i].match != p->segs[i].match))\n+\t\t\t\t (ice_cmp_bitmap(segs[i].match,\n+\t\t\t\t\t\t p->segs[i].match,\n+\t\t\t\t\t\t ICE_FLOW_FIELD_IDX_MAX) ==\n+\t\t\t\t false)))\n \t\t\t\t\tbreak;\n \n \t\t\t/* A match is found if all segments are matched */\n@@ -2432,7 +2437,7 @@ ice_flow_acl_set_xtrct_seq(struct ice_hw *hw, struct ice_flow_prof *prof)\n \t\t\tstruct ice_flow_seg_info *seg = &prof->segs[i];\n \t\t\tu16 j;\n \n-\t\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n+\t\t\tice_for_each_set_bit(j, seg->match,\n \t\t\t\t\t ICE_FLOW_FIELD_IDX_MAX) {\n \t\t\t\tinfo = &seg->fields[j];\n \n@@ -2601,7 +2606,8 @@ ice_flow_set_hw_prof(struct ice_hw *hw, u16 dest_vsi_handle,\n \t\t\tidx = i;\n \t\tparams->es[idx].prot_id = prof->fv[i].proto_id;\n \t\tparams->es[idx].off = prof->fv[i].offset;\n-\t\tparams->mask[idx] = CPU_TO_BE16(prof->fv[i].msk);\n+\t\tparams->mask[idx] = (((prof->fv[i].msk) << 8) & 0xff00) |\n+\t\t\t\t (((prof->fv[i].msk) >> 8) & 0x00ff);\n \t}\n \n \tswitch (prof->flags) {\n@@ -3002,7 +3008,7 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof,\n \t\tstruct ice_flow_seg_info *seg = &prof->segs[i];\n \t\tu16 j;\n \n-\t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n+\t\tice_for_each_set_bit(j, seg->match,\n \t\t\t\t (u16)ICE_FLOW_FIELD_IDX_MAX) {\n \t\t\tstruct ice_flow_fld_info *info = &seg->fields[j];\n \n@@ -3534,7 +3540,7 @@ enum ice_status ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk,\n \tif (entry_h == ICE_FLOW_ENTRY_HANDLE_INVAL)\n \t\treturn ICE_ERR_PARAM;\n \n-\tentry = ICE_FLOW_ENTRY_PTR((intptr_t)entry_h);\n+\tentry = ICE_FLOW_ENTRY_PTR(entry_h);\n \n \t/* Retain the pointer to the flow profile as the entry will be freed */\n \tprof = entry->prof;\n@@ -3576,11 +3582,9 @@ ice_flow_set_fld_ext(struct ice_flow_seg_info *seg, enum ice_flow_field fld,\n \t\t enum ice_flow_fld_match_type field_type, u16 val_loc,\n \t\t u16 mask_loc, u16 last_loc)\n {\n-\tu64 bit = BIT_ULL(fld);\n-\n-\tseg->match |= bit;\n+\tice_set_bit(fld, seg->match);\n \tif (field_type == ICE_FLOW_FLD_TYPE_RANGE)\n-\t\tseg->range |= bit;\n+\t\tice_set_bit(fld, seg->range);\n \n \tseg->fields[fld].type = field_type;\n \tseg->fields[fld].src.val = val_loc;\n@@ -3741,7 +3745,7 @@ enum ice_status ice_flow_rem_vsi_prof(struct ice_hw *hw, enum ice_block blk, u16\n }\n \n #define ICE_FLOW_RSS_SEG_HDR_L2_MASKS \\\n-(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_ETH_NON_IP | ICE_FLOW_SEG_HDR_VLAN)\n+(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)\n \n #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \\\n \t(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)\n@@ -3856,6 +3860,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)\n \tconst enum ice_block blk = ICE_BLK_RSS;\n \tstruct ice_flow_prof *p, *t;\n \tenum ice_status status = ICE_SUCCESS;\n+\tu16 vsig;\n \n \tif (!ice_is_vsi_valid(hw, vsi_handle))\n \t\treturn ICE_ERR_PARAM;\n@@ -3865,7 +3870,16 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)\n \n \tice_acquire_lock(&hw->rss_locks);\n \tLIST_FOR_EACH_ENTRY_SAFE(p, t, &hw->fl_profs[blk], ice_flow_prof,\n-\t\t\t\t l_entry)\n+\t\t\t\t l_entry) {\n+\t\tint ret;\n+\n+\t\t/* check if vsig is already removed */\n+\t\tret = ice_vsig_find_vsi(hw, blk,\n+\t\t\t\t\tice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\t&vsig);\n+\t\tif (!ret && !vsig)\n+\t\t\tbreak;\n+\n \t\tif (ice_is_bit_set(p->vsis, vsi_handle)) {\n \t\t\tstatus = ice_flow_disassoc_prof(hw, blk, p, vsi_handle);\n \t\t\tif (status)\n@@ -3877,6 +3891,7 @@ enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle)\n \t\t\t\t\tbreak;\n \t\t\t}\n \t\t}\n+\t}\n \tice_release_lock(&hw->rss_locks);\n \n \treturn status;\n@@ -3918,6 +3933,14 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)\n {\n \tenum ice_rss_cfg_hdr_type hdr_type;\n \tstruct ice_rss_cfg *r, *tmp;\n+\tu64 seg_match = 0;\n+\tu16 i;\n+\n+\t/* convert match bitmap to u64 for hash field comparison */\n+\tice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match,\n+\t\t\t ICE_FLOW_FIELD_IDX_MAX) {\n+\t\tseg_match |= 1ULL << i;\n+\t}\n \n \t/* Search for RSS hash fields associated to the VSI that match the\n \t * hash configurations associated to the flow profile. If found\n@@ -3926,7 +3949,7 @@ ice_rem_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)\n \thdr_type = ice_get_rss_hdr_type(prof);\n \tLIST_FOR_EACH_ENTRY_SAFE(r, tmp, &hw->rss_list_head,\n \t\t\t\t ice_rss_cfg, l_entry)\n-\t\tif (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match &&\n+\t\tif (r->hash.hash_flds == seg_match &&\n \t\t r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs &&\n \t\t r->hash.hdr_type == hdr_type) {\n \t\t\tice_clear_bit(vsi_handle, r->vsis);\n@@ -3951,11 +3974,18 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)\n {\n \tenum ice_rss_cfg_hdr_type hdr_type;\n \tstruct ice_rss_cfg *r, *rss_cfg;\n+\tu64 seg_match = 0;\n+\tu16 i;\n+\n+\tice_for_each_set_bit(i, prof->segs[prof->segs_cnt - 1].match,\n+\t\t\t ICE_FLOW_FIELD_IDX_MAX) {\n+\t\tseg_match |= 1ULL << i;\n+\t}\n \n \thdr_type = ice_get_rss_hdr_type(prof);\n \tLIST_FOR_EACH_ENTRY(r, &hw->rss_list_head,\n \t\t\t ice_rss_cfg, l_entry)\n-\t\tif (r->hash.hash_flds == prof->segs[prof->segs_cnt - 1].match &&\n+\t\tif (r->hash.hash_flds == seg_match &&\n \t\t r->hash.addl_hdrs == prof->segs[prof->segs_cnt - 1].hdrs &&\n \t\t r->hash.hdr_type == hdr_type) {\n \t\t\tice_set_bit(vsi_handle, r->vsis);\n@@ -3966,7 +3996,7 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)\n \tif (!rss_cfg)\n \t\treturn ICE_ERR_NO_MEMORY;\n \n-\trss_cfg->hash.hash_flds = prof->segs[prof->segs_cnt - 1].match;\n+\trss_cfg->hash.hash_flds = seg_match;\n \trss_cfg->hash.addl_hdrs = prof->segs[prof->segs_cnt - 1].hdrs;\n \trss_cfg->hash.hdr_type = hdr_type;\n \trss_cfg->hash.symm = prof->cfg.symm;\ndiff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h\nindex 57e8e1f1df..1415f5ba87 100644\n--- a/drivers/net/ice/base/ice_flow.h\n+++ b/drivers/net/ice/base/ice_flow.h\n@@ -452,8 +452,10 @@ struct ice_flow_seg_fld_raw {\n \n struct ice_flow_seg_info {\n \tu32 hdrs;\t/* Bitmask indicating protocol headers present */\n-\tu64 match;\t/* Bitmask indicating header fields to be matched */\n-\tu64 range;\t/* Bitmask indicating header fields matched as ranges */\n+\t/* Bitmask indicating header fields to be matched */\n+\tice_declare_bitmap(match, ICE_FLOW_FIELD_IDX_MAX);\n+\t/* Bitmask indicating header fields matched as ranges */\n+\tice_declare_bitmap(range, ICE_FLOW_FIELD_IDX_MAX);\n \n \tstruct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];\n \n", "prefixes": [ "04/30" ] }