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GET /api/patches/126569/?format=api
{ "id": 126569, "url": "https://patches.dpdk.org/api/patches/126569/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-3-qiming.yang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-3-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-3-qiming.yang@intel.com", "date": "2023-04-27T06:19:33", "name": "[02/30] net/ice/base: add flex array safe allocations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8a0ba8b125ae3668d6775a8fcc50a04e2320ffff", "submitter": { "id": 522, "url": "https://patches.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230427062001.478032-3-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "https://patches.dpdk.org/api/series/27885/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "https://patches.dpdk.org/series/27885/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126569/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/126569/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AC88042A08;\n\tThu, 27 Apr 2023 08:38:02 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9BE4242D48;\n\tThu, 27 Apr 2023 08:37:52 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id E47F942D3A\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:37:48 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:37:48 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:37:45 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577469; x=1714113469;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=UA3AY1VrHGPdAMeuMmAGzERZiNlzMyX/ZysNiCfssjY=;\n b=k2kKQ6xR2eKKfQL/d/m3sxLSEF7XKpt99kG/SX4yEmixVJ0d6v3iO4qS\n FA7IrEGY5QFZzV4cYE/hNI0LI21G51Z4Cn8y1QVIXcKtXR3AQOg7iwFGp\n D4qwWy5qJ+DwzQgALz8UxBOXTnwVmcvphaEgOKlkZyNJw7ltw2MGr8Aef\n ZOtBHoNesxS4CQXpj74Kiav9C2FENCYAcos337aBnibADewCFCGrJKkr8\n pHxk863G0Kk8VZ0IByKC+9JqAJ+p3ZdE8cSoEk6BGBit2y4uiTUoDi7AO\n FTSpyDdlL656EevcQK+9m4FyOv481Myb6wdfcguAPtHp0c4+aDw1hmbPh Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324255\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324255\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845659\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845659\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Jesse Brandeburg <jesse.brandeburg@intel.com>", "Subject": "[PATCH 02/30] net/ice/base: add flex array safe allocations", "Date": "Thu, 27 Apr 2023 06:19:33 +0000", "Message-Id": "<20230427062001.478032-3-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The Linux Kernel is now requiring flex array safe allocations from\ndrivers and the way that we used overlaid union structures was confusing\nor worse, breaking Klocwork as well as failing upstream builds that were\nchecking -Warray-bounds.\nAnd refactor structure size macros. The driver used several macros\nto compute size of flexible arrays. These macros are just as well\nconverted to plain code that does struct_size.\n\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 57 +++---\n drivers/net/ice/base/ice_switch.c | 265 +++++++++++++-------------\n drivers/net/ice/base/ice_switch.h | 12 --\n 3 files changed, 165 insertions(+), 169 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 65cba9ab37..69e528a8c9 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -813,12 +813,30 @@ struct ice_aqc_sw_rules {\n \t__le32 addr_low;\n };\n \n+/* Add switch rule response:\n+ * Content of return buffer is same as the input buffer. The status field and\n+ * LUT index are updated as part of the response\n+ */\n+struct ice_aqc_sw_rules_elem_hdr {\n+\t__le16 type; /* Switch rule type, one of T_... */\n+#define ICE_AQC_SW_RULES_T_LKUP_RX\t\t0x0\n+#define ICE_AQC_SW_RULES_T_LKUP_TX\t\t0x1\n+#define ICE_AQC_SW_RULES_T_LG_ACT\t\t0x2\n+#define ICE_AQC_SW_RULES_T_VSI_LIST_SET\t\t0x3\n+#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR\t0x4\n+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET\t0x5\n+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR\t0x6\n+\t__le16 status;\n+};\n+\n /* Add/Update/Get/Remove lookup Rx/Tx command/response entry\n * This structures describes the lookup rules and associated actions. \"index\"\n * is returned as part of a response to a successful Add command, and can be\n * used to identify the rule for Update/Get/Remove commands.\n */\n struct ice_sw_rule_lkup_rx_tx {\n+\tstruct ice_aqc_sw_rules_elem_hdr hdr;\n+\n \t__le16 recipe_id;\n #define ICE_SW_RECIPE_LOGICAL_PORT_FWD\t\t10\n \t/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */\n@@ -866,6 +884,8 @@ struct ice_sw_rule_lkup_rx_tx {\n #define ICE_SINGLE_ACT_PTR\t\t0x2\n #define ICE_SINGLE_ACT_PTR_VAL_S\t4\n #define ICE_SINGLE_ACT_PTR_VAL_M\t(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)\n+\t/* Bit 17 should be set if pointed action includes a FWD cmd */\n+#define ICE_SINGLE_ACT_PTR_HAS_FWD\tBIT(17)\n \t/* Bit 18 should be set to 1 */\n #define ICE_SINGLE_ACT_PTR_BIT\t\tBIT(18)\n \n@@ -895,14 +915,17 @@ struct ice_sw_rule_lkup_rx_tx {\n \t * lookup-type\n \t */\n \t__le16 hdr_len;\n-\tu8 hdr[STRUCT_HACK_VAR_LEN];\n+\tu8 hdr_data[STRUCT_HACK_VAR_LEN];\n };\n \n+#pragma pack(1)\n /* Add/Update/Remove large action command/response entry\n * \"index\" is returned as part of a response to a successful Add command, and\n * can be used to identify the action for Update/Get/Remove commands.\n */\n struct ice_sw_rule_lg_act {\n+\tstruct ice_aqc_sw_rules_elem_hdr hdr;\n+\n \t__le16 index; /* Index in large action table */\n \t__le16 size;\n \t/* Max number of large actions */\n@@ -957,16 +980,21 @@ struct ice_sw_rule_lg_act {\n #define ICE_LG_ACT_STAT_COUNT_M\t\t(0x7F << ICE_LG_ACT_STAT_COUNT_S)\n \t__le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */\n };\n+#pragma pack()\n \n+#pragma pack(1)\n /* Add/Update/Remove VSI list command/response entry\n * \"index\" is returned as part of a response to a successful Add command, and\n * can be used to identify the VSI list for Update/Get/Remove commands.\n */\n struct ice_sw_rule_vsi_list {\n+\tstruct ice_aqc_sw_rules_elem_hdr hdr;\n+\n \t__le16 index; /* Index of VSI/Prune list */\n \t__le16 number_vsi;\n \t__le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */\n };\n+#pragma pack()\n \n #pragma pack(1)\n /* Query VSI list command/response entry */\n@@ -976,31 +1004,6 @@ struct ice_sw_rule_vsi_list_query {\n };\n #pragma pack()\n \n-#pragma pack(1)\n-/* Add switch rule response:\n- * Content of return buffer is same as the input buffer. The status field and\n- * LUT index are updated as part of the response\n- */\n-struct ice_aqc_sw_rules_elem {\n-\t__le16 type; /* Switch rule type, one of T_... */\n-#define ICE_AQC_SW_RULES_T_LKUP_RX\t\t0x0\n-#define ICE_AQC_SW_RULES_T_LKUP_TX\t\t0x1\n-#define ICE_AQC_SW_RULES_T_LG_ACT\t\t0x2\n-#define ICE_AQC_SW_RULES_T_VSI_LIST_SET\t\t0x3\n-#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR\t0x4\n-#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET\t0x5\n-#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR\t0x6\n-\t__le16 status;\n-\tunion {\n-\t\tstruct ice_sw_rule_lkup_rx_tx lkup_tx_rx;\n-\t\tstruct ice_sw_rule_lg_act lg_act;\n-\t\tstruct ice_sw_rule_vsi_list vsi_list;\n-\t\tstruct ice_sw_rule_vsi_list_query vsi_list_query;\n-\t} pdata;\n-};\n-\n-#pragma pack()\n-\n /* PFC Ignore (direct 0x0301)\n * The command and response use the same descriptor structure\n */\n@@ -2771,7 +2774,7 @@ struct ice_aqc_move_txqs_data {\n };\n \n /* Download Package (indirect 0x0C40) */\n-/* Also used for Update Package (indirect 0x0C42 and 0x0C41) */\n+/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */\n struct ice_aqc_download_pkg {\n \tu8 flags;\n #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF\t0x01\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex cd6237136e..31fec80735 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -19,7 +19,7 @@\n #define ICE_MPLS_ETHER_ID\t\t0x8847\n #define ICE_ETH_P_8021Q\t\t\t0x8100\n \n-/* Dummy ethernet header needed in the ice_aqc_sw_rules_elem\n+/* Dummy ethernet header needed in the ice_sw_rule_*\n * struct to configure any switch filter rules.\n * {DA (6 bytes), SA(6 bytes),\n * Ether type (2 bytes for header without VLAN tag) OR\n@@ -3744,7 +3744,8 @@ static void ice_fill_sw_info(struct ice_hw *hw, struct ice_fltr_info *fi)\n */\n static void\n ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,\n-\t\t struct ice_aqc_sw_rules_elem *s_rule, enum ice_adminq_opc opc)\n+\t\t struct ice_sw_rule_lkup_rx_tx *s_rule,\n+\t\t enum ice_adminq_opc opc)\n {\n \tu16 vlan_id = ICE_MAX_VLAN_ID + 1;\n \tu16 vlan_tpid = ICE_ETH_P_8021Q;\n@@ -3756,15 +3757,14 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,\n \tu8 q_rgn;\n \n \tif (opc == ice_aqc_opc_remove_sw_rules) {\n-\t\ts_rule->pdata.lkup_tx_rx.act = 0;\n-\t\ts_rule->pdata.lkup_tx_rx.index =\n-\t\t\tCPU_TO_LE16(f_info->fltr_rule_id);\n-\t\ts_rule->pdata.lkup_tx_rx.hdr_len = 0;\n+\t\ts_rule->act = 0;\n+\t\ts_rule->index = CPU_TO_LE16(f_info->fltr_rule_id);\n+\t\ts_rule->hdr_len = 0;\n \t\treturn;\n \t}\n \n \teth_hdr_sz = sizeof(dummy_eth_header);\n-\teth_hdr = s_rule->pdata.lkup_tx_rx.hdr;\n+\teth_hdr = s_rule->hdr_data;\n \n \t/* initialize the ether header with a dummy header */\n \tice_memcpy(eth_hdr, dummy_eth_header, eth_hdr_sz, ICE_NONDMA_TO_NONDMA);\n@@ -3849,14 +3849,14 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,\n \t\tbreak;\n \t}\n \n-\ts_rule->type = (f_info->flag & ICE_FLTR_RX) ?\n+\ts_rule->hdr.type = (f_info->flag & ICE_FLTR_RX) ?\n \t\tCPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX) :\n \t\tCPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX);\n \n \t/* Recipe set depending on lookup type */\n-\ts_rule->pdata.lkup_tx_rx.recipe_id = CPU_TO_LE16(f_info->lkup_type);\n-\ts_rule->pdata.lkup_tx_rx.src = CPU_TO_LE16(f_info->src);\n-\ts_rule->pdata.lkup_tx_rx.act = CPU_TO_LE32(act);\n+\ts_rule->recipe_id = CPU_TO_LE16(f_info->lkup_type);\n+\ts_rule->src = CPU_TO_LE16(f_info->src);\n+\ts_rule->act = CPU_TO_LE32(act);\n \n \tif (daddr)\n \t\tice_memcpy(eth_hdr + ICE_ETH_DA_OFFSET, daddr, ETH_ALEN,\n@@ -3871,7 +3871,7 @@ ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,\n \n \t/* Create the switch rule with the final dummy Ethernet header */\n \tif (opc != ice_aqc_opc_update_sw_rules)\n-\t\ts_rule->pdata.lkup_tx_rx.hdr_len = CPU_TO_LE16(eth_hdr_sz);\n+\t\ts_rule->hdr_len = CPU_TO_LE16(eth_hdr_sz);\n }\n \n /**\n@@ -3888,7 +3888,8 @@ static enum ice_status\n ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t\t u16 sw_marker, u16 l_id)\n {\n-\tstruct ice_aqc_sw_rules_elem *lg_act, *rx_tx;\n+\tstruct ice_sw_rule_lkup_rx_tx *rx_tx;\n+\tstruct ice_sw_rule_lg_act *lg_act;\n \t/* For software marker we need 3 large actions\n \t * 1. FWD action: FWD TO VSI or VSI LIST\n \t * 2. GENERIC VALUE action to hold the profile ID\n@@ -3909,18 +3910,19 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t * 1. Large Action\n \t * 2. Look up Tx Rx\n \t */\n-\tlg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_lg_acts);\n-\trules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE;\n-\tlg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size);\n+\tlg_act_size = (u16)ice_struct_size(lg_act, act, num_lg_acts);\n+\trules_size = lg_act_size +\n+\t\t ice_struct_size(rx_tx, hdr_data, DUMMY_ETH_HDR_LEN);\n+\tlg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size);\n \tif (!lg_act)\n \t\treturn ICE_ERR_NO_MEMORY;\n \n-\trx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size);\n+\trx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act + lg_act_size);\n \n \t/* Fill in the first switch rule i.e. large action */\n-\tlg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n-\tlg_act->pdata.lg_act.index = CPU_TO_LE16(l_id);\n-\tlg_act->pdata.lg_act.size = CPU_TO_LE16(num_lg_acts);\n+\tlg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n+\tlg_act->index = CPU_TO_LE16(l_id);\n+\tlg_act->size = CPU_TO_LE16(num_lg_acts);\n \n \t/* First action VSI forwarding or VSI list forwarding depending on how\n \t * many VSIs\n@@ -3932,13 +3934,13 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \tact |= (id << ICE_LG_ACT_VSI_LIST_ID_S) & ICE_LG_ACT_VSI_LIST_ID_M;\n \tif (m_ent->vsi_count > 1)\n \t\tact |= ICE_LG_ACT_VSI_LIST;\n-\tlg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act);\n+\tlg_act->act[0] = CPU_TO_LE32(act);\n \n \t/* Second action descriptor type */\n \tact = ICE_LG_ACT_GENERIC;\n \n \tact |= (1 << ICE_LG_ACT_GENERIC_VALUE_S) & ICE_LG_ACT_GENERIC_VALUE_M;\n-\tlg_act->pdata.lg_act.act[1] = CPU_TO_LE32(act);\n+\tlg_act->act[1] = CPU_TO_LE32(act);\n \n \tact = (ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX <<\n \t ICE_LG_ACT_GENERIC_OFFSET_S) & ICE_LG_ACT_GENERIC_OFFSET_M;\n@@ -3948,24 +3950,22 @@ ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \tact |= (sw_marker << ICE_LG_ACT_GENERIC_VALUE_S) &\n \t\tICE_LG_ACT_GENERIC_VALUE_M;\n \n-\tlg_act->pdata.lg_act.act[2] = CPU_TO_LE32(act);\n+\tlg_act->act[2] = CPU_TO_LE32(act);\n \n \t/* call the fill switch rule to fill the lookup Tx Rx structure */\n \tice_fill_sw_rule(hw, &m_ent->fltr_info, rx_tx,\n \t\t\t ice_aqc_opc_update_sw_rules);\n \n \t/* Update the action to point to the large action ID */\n-\trx_tx->pdata.lkup_tx_rx.act =\n-\t\tCPU_TO_LE32(ICE_SINGLE_ACT_PTR |\n-\t\t\t ((l_id << ICE_SINGLE_ACT_PTR_VAL_S) &\n-\t\t\t ICE_SINGLE_ACT_PTR_VAL_M));\n+\trx_tx->act = CPU_TO_LE32(ICE_SINGLE_ACT_PTR |\n+\t\t\t\t ((l_id << ICE_SINGLE_ACT_PTR_VAL_S) &\n+\t\t\t\t ICE_SINGLE_ACT_PTR_VAL_M));\n \n \t/* Use the filter rule ID of the previously created rule with single\n \t * act. Once the update happens, hardware will treat this as large\n \t * action\n \t */\n-\trx_tx->pdata.lkup_tx_rx.index =\n-\t\tCPU_TO_LE16(m_ent->fltr_info.fltr_rule_id);\n+\trx_tx->index = CPU_TO_LE16(m_ent->fltr_info.fltr_rule_id);\n \n \tstatus = ice_aq_sw_rules(hw, lg_act, rules_size, 2,\n \t\t\t\t ice_aqc_opc_update_sw_rules, NULL);\n@@ -3989,8 +3989,8 @@ static enum ice_status\n ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t\t u16 counter_id, u16 l_id)\n {\n-\tstruct ice_aqc_sw_rules_elem *lg_act;\n-\tstruct ice_aqc_sw_rules_elem *rx_tx;\n+\tstruct ice_sw_rule_lkup_rx_tx *rx_tx;\n+\tstruct ice_sw_rule_lg_act *lg_act;\n \tenum ice_status status;\n \t/* 2 actions will be added while adding a large action counter */\n \tconst int num_acts = 2;\n@@ -4008,18 +4008,20 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t * 1. Large Action\n \t * 2. Look up Tx Rx\n \t */\n-\tlg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_acts);\n-\trules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE;\n-\tlg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size);\n+\tlg_act_size = (u16)ice_struct_size(lg_act, act, num_acts);\n+\trules_size = lg_act_size +\n+\t\t ice_struct_size(rx_tx, hdr_data, DUMMY_ETH_HDR_LEN);\n+\tlg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size);\n \tif (!lg_act)\n \t\treturn ICE_ERR_NO_MEMORY;\n \n-\trx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size);\n+\trx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act +\n+\t\t\t\t\t\t lg_act_size);\n \n \t/* Fill in the first switch rule i.e. large action */\n-\tlg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n-\tlg_act->pdata.lg_act.index = CPU_TO_LE16(l_id);\n-\tlg_act->pdata.lg_act.size = CPU_TO_LE16(num_acts);\n+\tlg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n+\tlg_act->index = CPU_TO_LE16(l_id);\n+\tlg_act->size = CPU_TO_LE16(num_acts);\n \n \t/* First action VSI forwarding or VSI list forwarding depending on how\n \t * many VSIs\n@@ -4032,13 +4034,13 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t\tICE_LG_ACT_VSI_LIST_ID_M;\n \tif (m_ent->vsi_count > 1)\n \t\tact |= ICE_LG_ACT_VSI_LIST;\n-\tlg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act);\n+\tlg_act->act[0] = CPU_TO_LE32(act);\n \n \t/* Second action counter ID */\n \tact = ICE_LG_ACT_STAT_COUNT;\n \tact |= (counter_id << ICE_LG_ACT_STAT_COUNT_S) &\n \t\tICE_LG_ACT_STAT_COUNT_M;\n-\tlg_act->pdata.lg_act.act[1] = CPU_TO_LE32(act);\n+\tlg_act->act[1] = CPU_TO_LE32(act);\n \n \t/* call the fill switch rule to fill the lookup Tx Rx structure */\n \tice_fill_sw_rule(hw, &m_ent->fltr_info, rx_tx,\n@@ -4046,14 +4048,14 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \n \tact = ICE_SINGLE_ACT_PTR;\n \tact |= (l_id << ICE_SINGLE_ACT_PTR_VAL_S) & ICE_SINGLE_ACT_PTR_VAL_M;\n-\trx_tx->pdata.lkup_tx_rx.act = CPU_TO_LE32(act);\n+\trx_tx->act = CPU_TO_LE32(act);\n \n \t/* Use the filter rule ID of the previously created rule with single\n \t * act. Once the update happens, hardware will treat this as large\n \t * action\n \t */\n \tf_rule_id = m_ent->fltr_info.fltr_rule_id;\n-\trx_tx->pdata.lkup_tx_rx.index = CPU_TO_LE16(f_rule_id);\n+\trx_tx->index = CPU_TO_LE16(f_rule_id);\n \n \tstatus = ice_aq_sw_rules(hw, lg_act, rules_size, 2,\n \t\t\t\t ice_aqc_opc_update_sw_rules, NULL);\n@@ -4115,7 +4117,7 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n \t\t\t u16 vsi_list_id, bool remove, enum ice_adminq_opc opc,\n \t\t\t enum ice_sw_lkup_type lkup_type)\n {\n-\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tstruct ice_sw_rule_vsi_list *s_rule;\n \tenum ice_status status;\n \tu16 s_rule_size;\n \tu16 rule_type;\n@@ -4140,8 +4142,8 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n \telse\n \t\treturn ICE_ERR_PARAM;\n \n-\ts_rule_size = (u16)ICE_SW_RULE_VSI_LIST_SIZE(num_vsi);\n-\ts_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size);\n+\ts_rule_size = (u16)ice_struct_size(s_rule, vsi, num_vsi);\n+\ts_rule = (struct ice_sw_rule_vsi_list *)ice_malloc(hw, s_rule_size);\n \tif (!s_rule)\n \t\treturn ICE_ERR_NO_MEMORY;\n \tfor (i = 0; i < num_vsi; i++) {\n@@ -4150,13 +4152,13 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n \t\t\tgoto exit;\n \t\t}\n \t\t/* AQ call requires hw_vsi_id(s) */\n-\t\ts_rule->pdata.vsi_list.vsi[i] =\n+\t\ts_rule->vsi[i] =\n \t\t\tCPU_TO_LE16(ice_get_hw_vsi_num(hw, vsi_handle_arr[i]));\n \t}\n \n-\ts_rule->type = CPU_TO_LE16(rule_type);\n-\ts_rule->pdata.vsi_list.number_vsi = CPU_TO_LE16(num_vsi);\n-\ts_rule->pdata.vsi_list.index = CPU_TO_LE16(vsi_list_id);\n+\ts_rule->hdr.type = CPU_TO_LE16(rule_type);\n+\ts_rule->number_vsi = CPU_TO_LE16(num_vsi);\n+\ts_rule->index = CPU_TO_LE16(vsi_list_id);\n \n \tstatus = ice_aq_sw_rules(hw, s_rule, s_rule_size, 1, opc, NULL);\n \n@@ -4205,11 +4207,12 @@ ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list,\n \t\t\tstruct ice_fltr_list_entry *f_entry)\n {\n \tstruct ice_fltr_mgmt_list_entry *fm_entry;\n-\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tstruct ice_sw_rule_lkup_rx_tx *s_rule;\n \tenum ice_status status;\n \n-\ts_rule = (struct ice_aqc_sw_rules_elem *)\n-\t\tice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE);\n+\ts_rule = (struct ice_sw_rule_lkup_rx_tx *)\n+\t\tice_malloc(hw, ice_struct_size(s_rule, hdr_data,\n+\t\t\t\t\t DUMMY_ETH_HDR_LEN));\n \tif (!s_rule)\n \t\treturn ICE_ERR_NO_MEMORY;\n \tfm_entry = (struct ice_fltr_mgmt_list_entry *)\n@@ -4230,17 +4233,17 @@ ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list,\n \tice_fill_sw_rule(hw, &fm_entry->fltr_info, s_rule,\n \t\t\t ice_aqc_opc_add_sw_rules);\n \n-\tstatus = ice_aq_sw_rules(hw, s_rule, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE, 1,\n-\t\t\t\t ice_aqc_opc_add_sw_rules, NULL);\n+\tstatus = ice_aq_sw_rules(hw, s_rule,\n+\t\t\t\t ice_struct_size(s_rule, hdr_data,\n+\t\t\t\t\t\t DUMMY_ETH_HDR_LEN),\n+\t\t\t\t 1, ice_aqc_opc_add_sw_rules, NULL);\n \tif (status) {\n \t\tice_free(hw, fm_entry);\n \t\tgoto ice_create_pkt_fwd_rule_exit;\n \t}\n \n-\tf_entry->fltr_info.fltr_rule_id =\n-\t\tLE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index);\n-\tfm_entry->fltr_info.fltr_rule_id =\n-\t\tLE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index);\n+\tf_entry->fltr_info.fltr_rule_id = LE16_TO_CPU(s_rule->index);\n+\tfm_entry->fltr_info.fltr_rule_id = LE16_TO_CPU(s_rule->index);\n \n \t/* The book keeping entries will get removed when base driver\n \t * calls remove filter AQ command\n@@ -4263,21 +4266,24 @@ ice_create_pkt_fwd_rule(struct ice_hw *hw, struct ice_sw_recipe *recp_list,\n static enum ice_status\n ice_update_pkt_fwd_rule(struct ice_hw *hw, struct ice_fltr_info *f_info)\n {\n-\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tstruct ice_sw_rule_lkup_rx_tx *s_rule;\n \tenum ice_status status;\n \n-\ts_rule = (struct ice_aqc_sw_rules_elem *)\n-\t\tice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE);\n+\ts_rule = (struct ice_sw_rule_lkup_rx_tx *)\n+\t\tice_malloc(hw, ice_struct_size(s_rule, hdr_data,\n+\t\t\t\t\t DUMMY_ETH_HDR_LEN));\n \tif (!s_rule)\n \t\treturn ICE_ERR_NO_MEMORY;\n \n \tice_fill_sw_rule(hw, f_info, s_rule, ice_aqc_opc_update_sw_rules);\n \n-\ts_rule->pdata.lkup_tx_rx.index = CPU_TO_LE16(f_info->fltr_rule_id);\n+\ts_rule->index = CPU_TO_LE16(f_info->fltr_rule_id);\n \n \t/* Update switch rule with new rule set to forward VSI list */\n-\tstatus = ice_aq_sw_rules(hw, s_rule, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE, 1,\n-\t\t\t\t ice_aqc_opc_update_sw_rules, NULL);\n+\tstatus = ice_aq_sw_rules(hw, s_rule,\n+\t\t\t\t ice_struct_size(s_rule, hdr_data,\n+\t\t\t\t\t\t DUMMY_ETH_HDR_LEN),\n+\t\t\t\t 1, ice_aqc_opc_update_sw_rules, NULL);\n \n \tice_free(hw, s_rule);\n \treturn status;\n@@ -4742,10 +4748,10 @@ ice_remove_rule_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list,\n \n \tif (remove_rule) {\n \t\t/* Remove the lookup rule */\n-\t\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\t\tstruct ice_sw_rule_lkup_rx_tx *s_rule;\n \n-\t\ts_rule = (struct ice_aqc_sw_rules_elem *)\n-\t\t\tice_malloc(hw, ICE_SW_RULE_RX_TX_NO_HDR_SIZE);\n+\t\ts_rule = (struct ice_sw_rule_lkup_rx_tx *)\n+\t\t\tice_malloc(hw, ice_struct_size(s_rule, hdr_data, 0));\n \t\tif (!s_rule) {\n \t\t\tstatus = ICE_ERR_NO_MEMORY;\n \t\t\tgoto exit;\n@@ -4755,8 +4761,8 @@ ice_remove_rule_internal(struct ice_hw *hw, struct ice_sw_recipe *recp_list,\n \t\t\t\t ice_aqc_opc_remove_sw_rules);\n \n \t\tstatus = ice_aq_sw_rules(hw, s_rule,\n-\t\t\t\t\t ICE_SW_RULE_RX_TX_NO_HDR_SIZE, 1,\n-\t\t\t\t\t ice_aqc_opc_remove_sw_rules, NULL);\n+\t\t\t\t\t ice_struct_size(s_rule, hdr_data, 0),\n+\t\t\t\t\t 1, ice_aqc_opc_remove_sw_rules, NULL);\n \n \t\t/* Remove a book keeping from the list */\n \t\tice_free(hw, s_rule);\n@@ -4872,7 +4878,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \t\t struct ice_switch_info *sw, u8 lport)\n {\n \tstruct ice_sw_recipe *recp_list = &sw->recp_list[ICE_SW_LKUP_MAC];\n-\tstruct ice_aqc_sw_rules_elem *s_rule, *r_iter;\n+\tstruct ice_sw_rule_lkup_rx_tx *s_rule, *r_iter;\n \tstruct ice_fltr_list_entry *m_list_itr;\n \tstruct LIST_HEAD_TYPE *rule_head;\n \tu16 total_elem_left, s_rule_size;\n@@ -4933,8 +4939,8 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \t}\n \n \t/* Allocate switch rule buffer for the bulk update for unicast */\n-\ts_rule_size = ICE_SW_RULE_RX_TX_ETH_HDR_SIZE;\n-\ts_rule = (struct ice_aqc_sw_rules_elem *)\n+\ts_rule_size = ice_struct_size(s_rule, hdr_data, DUMMY_ETH_HDR_LEN);\n+\ts_rule = (struct ice_sw_rule_lkup_rx_tx *)\n \t\tice_calloc(hw, num_unicast, s_rule_size);\n \tif (!s_rule) {\n \t\tstatus = ICE_ERR_NO_MEMORY;\n@@ -4950,7 +4956,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \t\tif (IS_UNICAST_ETHER_ADDR(mac_addr)) {\n \t\t\tice_fill_sw_rule(hw, &m_list_itr->fltr_info, r_iter,\n \t\t\t\t\t ice_aqc_opc_add_sw_rules);\n-\t\t\tr_iter = (struct ice_aqc_sw_rules_elem *)\n+\t\t\tr_iter = (struct ice_sw_rule_lkup_rx_tx *)\n \t\t\t\t((u8 *)r_iter + s_rule_size);\n \t\t}\n \t}\n@@ -4960,7 +4966,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \t/* Call AQ switch rule in AQ_MAX chunk */\n \tfor (total_elem_left = num_unicast; total_elem_left > 0;\n \t total_elem_left -= elem_sent) {\n-\t\tstruct ice_aqc_sw_rules_elem *entry = r_iter;\n+\t\tstruct ice_sw_rule_lkup_rx_tx *entry = r_iter;\n \n \t\telem_sent = MIN_T(u8, total_elem_left,\n \t\t\t\t (ICE_AQ_MAX_BUF_LEN / s_rule_size));\n@@ -4969,7 +4975,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \t\t\t\t\t NULL);\n \t\tif (status)\n \t\t\tgoto ice_add_mac_exit;\n-\t\tr_iter = (struct ice_aqc_sw_rules_elem *)\n+\t\tr_iter = (struct ice_sw_rule_lkup_rx_tx *)\n \t\t\t((u8 *)r_iter + (elem_sent * s_rule_size));\n \t}\n \n@@ -4983,7 +4989,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \n \t\tif (IS_UNICAST_ETHER_ADDR(mac_addr)) {\n \t\t\tf_info->fltr_rule_id =\n-\t\t\t\tLE16_TO_CPU(r_iter->pdata.lkup_tx_rx.index);\n+\t\t\t\tLE16_TO_CPU(r_iter->index);\n \t\t\tf_info->fltr_act = ICE_FWD_TO_VSI;\n \t\t\t/* Create an entry to track this MAC address */\n \t\t\tfm_entry = (struct ice_fltr_mgmt_list_entry *)\n@@ -4999,7 +5005,7 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list,\n \t\t\t */\n \n \t\t\tLIST_ADD(&fm_entry->list_entry, rule_head);\n-\t\t\tr_iter = (struct ice_aqc_sw_rules_elem *)\n+\t\t\tr_iter = (struct ice_sw_rule_lkup_rx_tx *)\n \t\t\t\t((u8 *)r_iter + s_rule_size);\n \t\t}\n \t}\n@@ -8521,7 +8527,7 @@ ice_find_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n */\n static enum ice_status\n ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n-\t\t\t struct ice_aqc_sw_rules_elem *s_rule,\n+\t\t\t struct ice_sw_rule_lkup_rx_tx *s_rule,\n \t\t\t const u8 *dummy_pkt, u16 pkt_len,\n \t\t\t const struct ice_dummy_pkt_offsets *offsets)\n {\n@@ -8531,7 +8537,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n \t/* Start with a packet with a pre-defined/dummy content. Then, fill\n \t * in the header values to be looked up or matched.\n \t */\n-\tpkt = s_rule->pdata.lkup_tx_rx.hdr;\n+\tpkt = s_rule->hdr_data;\n \n \tice_memcpy(pkt, dummy_pkt, pkt_len, ICE_NONDMA_TO_NONDMA);\n \n@@ -8636,7 +8642,7 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem *lkups, u16 lkups_cnt,\n \t\t\t\t\t ((u16 *)&lkups[i].m_u)[j]);\n \t}\n \n-\ts_rule->pdata.lkup_tx_rx.hdr_len = CPU_TO_LE16(pkt_len);\n+\ts_rule->hdr_len = CPU_TO_LE16(pkt_len);\n \n \treturn ICE_SUCCESS;\n }\n@@ -8922,15 +8928,15 @@ ice_set_lg_action_entry(u8 act_type, union lg_act_entry *lg_entry)\n * Fill a large action to hold software marker and link the lookup rule\n * with an action pointing to this larger action\n */\n-static struct ice_aqc_sw_rules_elem *\n+static struct ice_sw_rule_lg_act *\n ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id,\n \t\t\t u16 lkup_rule_sz, u16 lg_act_size, u16 num_lg_acts,\n-\t\t\t struct ice_aqc_sw_rules_elem *s_rule)\n+\t\t\t struct ice_sw_rule_lkup_rx_tx *s_rule)\n {\n-\tstruct ice_aqc_sw_rules_elem *rx_tx, *lg_act;\n+\tstruct ice_sw_rule_lkup_rx_tx *rx_tx;\n \tconst u16 offset_generic_md_word_0 = 0;\n \tconst u16 offset_generic_md_word_1 = 1;\n-\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_sw_rule_lg_act *lg_act;\n \tunion lg_act_entry lg_e_lo;\n \tunion lg_act_entry lg_e_hi;\n \tconst u8 priority = 0x3;\n@@ -8939,19 +8945,19 @@ ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id,\n \n \t/* For software marker we need 2 large actions for 32 bit mark id */\n \trules_size = lg_act_size + lkup_rule_sz;\n-\tlg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size);\n+\tlg_act = (struct ice_sw_rule_lg_act *)ice_malloc(hw, rules_size);\n \tif (!lg_act)\n \t\treturn NULL;\n \n-\trx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size);\n+\trx_tx = (struct ice_sw_rule_lkup_rx_tx *)((u8 *)lg_act + lg_act_size);\n \n \tice_memcpy(rx_tx, s_rule, lkup_rule_sz, ICE_NONDMA_TO_NONDMA);\n \tice_free(hw, s_rule);\n \ts_rule = NULL;\n \n-\tlg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n-\tlg_act->pdata.lg_act.index = CPU_TO_LE16(l_id);\n-\tlg_act->pdata.lg_act.size = CPU_TO_LE16(num_lg_acts);\n+\tlg_act->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n+\tlg_act->index = CPU_TO_LE16(l_id);\n+\tlg_act->size = CPU_TO_LE16(num_lg_acts);\n \n \t/* GENERIC VALUE action to hold the software marker ID low 16 bits */\n \t/* and set in meta data index 4 by default. */\n@@ -8959,7 +8965,7 @@ ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id,\n \tlg_e_lo.generic_act.offset = offset_generic_md_word_0;\n \tlg_e_lo.generic_act.priority = priority;\n \tact = ice_set_lg_action_entry(ICE_LG_ACT_GENERIC, &lg_e_lo);\n-\tlg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act);\n+\tlg_act->act[0] = CPU_TO_LE32(act);\n \n \tif (num_lg_acts == 1)\n \t\treturn lg_act;\n@@ -8971,7 +8977,7 @@ ice_fill_sw_marker_lg_act(struct ice_hw *hw, u32 sw_marker, u16 l_id,\n \tlg_e_hi.generic_act.offset = offset_generic_md_word_1;\n \tlg_e_hi.generic_act.priority = priority;\n \tact = ice_set_lg_action_entry(ICE_LG_ACT_GENERIC, &lg_e_hi);\n-\tlg_act->pdata.lg_act.act[1] = CPU_TO_LE32(act);\n+\tlg_act->act[1] = CPU_TO_LE32(act);\n \n \treturn lg_act;\n }\n@@ -9000,11 +9006,12 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t\t struct ice_rule_query_data *added_entry)\n {\n \tstruct ice_adv_fltr_mgmt_list_entry *m_entry, *adv_fltr = NULL;\n-\tu16 lg_act_size, lg_act_id = ICE_INVAL_LG_ACT_INDEX;\n+\tu16 lg_act_sz, lg_act_id = ICE_INVAL_LG_ACT_INDEX;\n \tu16 rid = 0, i, pkt_len, rule_buf_sz, vsi_handle;\n \tconst struct ice_dummy_pkt_offsets *pkt_offsets;\n-\tstruct ice_aqc_sw_rules_elem *s_rule = NULL;\n-\tstruct ice_aqc_sw_rules_elem *rx_tx;\n+\tstruct ice_sw_rule_lg_act *lg_rule = NULL;\n+\tstruct ice_sw_rule_lkup_rx_tx *s_rule = NULL;\n+\tstruct ice_sw_rule_lkup_rx_tx *rx_tx;\n \tstruct LIST_HEAD_TYPE *rule_head;\n \tstruct ice_switch_info *sw;\n \tu16 nb_lg_acts_mark = 1;\n@@ -9093,8 +9100,8 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t\t}\n \t\treturn status;\n \t}\n-\trule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE + pkt_len;\n-\ts_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rule_buf_sz);\n+\trule_buf_sz = ice_struct_size(s_rule, hdr_data, 0) + pkt_len;\n+\ts_rule = (struct ice_sw_rule_lkup_rx_tx *)ice_malloc(hw, rule_buf_sz);\n \tif (!s_rule)\n \t\treturn ICE_ERR_NO_MEMORY;\n \tif (!rinfo->flags_info.act_valid)\n@@ -9145,24 +9152,23 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t\tgoto err_ice_add_adv_rule;\n \t}\n \n-\t/* set the rule LOOKUP type based on caller specified 'RX'\n+\t/* Set the rule LOOKUP type based on caller specified 'Rx'\n \t * instead of hardcoding it to be either LOOKUP_TX/RX\n \t *\n-\t * for 'RX' set the source to be the port number\n-\t * for 'TX' set the source to be the source HW VSI number (determined\n+\t * for 'Rx' set the source to be the port number\n+\t * for 'Tx' set the source to be the source HW VSI number (determined\n \t * by caller)\n \t */\n \tif (rinfo->rx) {\n-\t\ts_rule->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX);\n-\t\ts_rule->pdata.lkup_tx_rx.src =\n-\t\t\tCPU_TO_LE16(hw->port_info->lport);\n+\t\ts_rule->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX);\n+\t\ts_rule->src = CPU_TO_LE16(hw->port_info->lport);\n \t} else {\n-\t\ts_rule->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX);\n-\t\ts_rule->pdata.lkup_tx_rx.src = CPU_TO_LE16(rinfo->sw_act.src);\n+\t\ts_rule->hdr.type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX);\n+\t\ts_rule->src = CPU_TO_LE16(rinfo->sw_act.src);\n \t}\n \n-\ts_rule->pdata.lkup_tx_rx.recipe_id = CPU_TO_LE16(rid);\n-\ts_rule->pdata.lkup_tx_rx.act = CPU_TO_LE32(act);\n+\ts_rule->recipe_id = CPU_TO_LE16(rid);\n+\ts_rule->act = CPU_TO_LE32(act);\n \n \tstatus = ice_fill_adv_dummy_packet(lkups, lkups_cnt, s_rule, pkt,\n \t\t\t\t\t pkt_len, pkt_offsets);\n@@ -9172,7 +9178,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \tif (rinfo->tun_type != ICE_NON_TUN &&\n \t rinfo->tun_type != ICE_SW_TUN_AND_NON_TUN) {\n \t\tstatus = ice_fill_adv_packet_tun(hw, rinfo->tun_type,\n-\t\t\t\t\t\t s_rule->pdata.lkup_tx_rx.hdr,\n+\t\t\t\t\t\t s_rule->hdr_data,\n \t\t\t\t\t\t pkt_offsets);\n \t\tif (status)\n \t\t\tgoto err_ice_add_adv_rule;\n@@ -9180,18 +9186,19 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \n \trx_tx = s_rule;\n \tif (rinfo->sw_act.fltr_act == ICE_SET_MARK) {\n-\t\tlg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(nb_lg_acts_mark);\n-\t\ts_rule = ice_fill_sw_marker_lg_act(hw, rinfo->sw_act.markid,\n-\t\t\t\t\t\t lg_act_id, rule_buf_sz,\n-\t\t\t\t\t\t lg_act_size, nb_lg_acts_mark,\n-\t\t\t\t\t\t s_rule);\n-\t\tif (!s_rule)\n+\t\tlg_act_sz = (u16)ice_struct_size(lg_rule, act, nb_lg_acts_mark);\n+\t\tlg_rule = ice_fill_sw_marker_lg_act(hw, rinfo->sw_act.markid,\n+\t\t\t\t\t\t lg_act_id, rule_buf_sz,\n+\t\t\t\t\t\t lg_act_sz, nb_lg_acts_mark,\n+\t\t\t\t\t\t s_rule);\n+\t\tif (!lg_rule)\n \t\t\tgoto err_ice_add_adv_rule;\n \n-\t\trule_buf_sz += lg_act_size;\n+\t\ts_rule = (struct ice_sw_rule_lkup_rx_tx *)lg_rule;\n+\t\trule_buf_sz += lg_act_sz;\n \t\tnum_rules += 1;\n-\t\trx_tx = (struct ice_aqc_sw_rules_elem *)\n-\t\t\t((u8 *)s_rule + lg_act_size);\n+\t\trx_tx = (struct ice_sw_rule_lkup_rx_tx *)\n+\t\t\t((u8 *)s_rule + lg_act_sz);\n \t}\n \n \tstatus = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule,\n@@ -9221,7 +9228,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \tadv_fltr->lkups_cnt = lkups_cnt;\n \tadv_fltr->rule_info = *rinfo;\n \tadv_fltr->rule_info.fltr_rule_id =\n-\t\tLE16_TO_CPU(rx_tx->pdata.lkup_tx_rx.index);\n+\t\tLE16_TO_CPU(rx_tx->index);\n \tadv_fltr->rule_info.lg_id = LE16_TO_CPU(lg_act_id);\n \tsw = hw->switch_info;\n \tsw->recp_list[rid].adv_rule = true;\n@@ -9363,9 +9370,9 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n {\n \tstruct ice_adv_fltr_mgmt_list_entry *list_elem;\n \tstruct ice_prot_lkup_ext lkup_exts;\n+\tbool remove_rule = false;\n \tstruct ice_lock *rule_lock; /* Lock to protect filter rule list */\n \tenum ice_status status = ICE_SUCCESS;\n-\tbool remove_rule = false;\n \tu16 i, rid, vsi_handle;\n \n \tice_memset(&lkup_exts, 0, sizeof(lkup_exts), ICE_NONDMA_MEM);\n@@ -9416,23 +9423,21 @@ ice_rem_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \t}\n \tice_release_lock(rule_lock);\n \tif (remove_rule) {\n-\t\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\t\tstruct ice_sw_rule_lkup_rx_tx *s_rule;\n \t\tu16 rule_buf_sz;\n \n \t\tif (rinfo->sw_act.fltr_act == ICE_SET_MARK)\n \t\t\tice_free_sw_marker_lg(hw, list_elem->rule_info.lg_id,\n \t\t\t\t\t rinfo->sw_act.markid);\n-\t\trule_buf_sz = ICE_SW_RULE_RX_TX_NO_HDR_SIZE;\n-\t\ts_rule = (struct ice_aqc_sw_rules_elem *)\n+\t\trule_buf_sz = ice_struct_size(s_rule, hdr_data, 0);\n+\t\ts_rule = (struct ice_sw_rule_lkup_rx_tx *)\n \t\t\tice_malloc(hw, rule_buf_sz);\n \t\tif (!s_rule)\n \t\t\treturn ICE_ERR_NO_MEMORY;\n-\t\ts_rule->pdata.lkup_tx_rx.act = 0;\n-\t\ts_rule->pdata.lkup_tx_rx.index =\n-\t\t\tCPU_TO_LE16(list_elem->rule_info.fltr_rule_id);\n-\t\ts_rule->pdata.lkup_tx_rx.hdr_len = 0;\n-\t\tstatus = ice_aq_sw_rules(hw, (struct ice_aqc_sw_rules *)s_rule,\n-\t\t\t\t\t rule_buf_sz, 1,\n+\t\ts_rule->act = 0;\n+\t\ts_rule->index = CPU_TO_LE16(list_elem->rule_info.fltr_rule_id);\n+\t\ts_rule->hdr_len = 0;\n+\t\tstatus = ice_aq_sw_rules(hw, s_rule, rule_buf_sz, 1,\n \t\t\t\t\t ice_aqc_opc_remove_sw_rules, NULL);\n \t\tif (status == ICE_SUCCESS || status == ICE_ERR_DOES_NOT_EXIST) {\n \t\t\tstruct ice_switch_info *sw = hw->switch_info;\n@@ -9488,20 +9493,20 @@ ice_rem_adv_rule_by_id(struct ice_hw *hw,\n \n /**\n * ice_rem_adv_rule_for_vsi - removes existing advanced switch rules for a\n- * given VSI handle\n+ * given VSI handle\n * @hw: pointer to the hardware structure\n * @vsi_handle: VSI handle for which we are supposed to remove all the rules.\n *\n * This function is used to remove all the rules for a given VSI and as soon\n * as removing a rule fails, it will return immediately with the error code,\n- * else it will return ICE_SUCCESS\n+ * else it will return success.\n */\n enum ice_status ice_rem_adv_rule_for_vsi(struct ice_hw *hw, u16 vsi_handle)\n {\n \tstruct ice_adv_fltr_mgmt_list_entry *list_itr, *tmp_entry;\n \tstruct ice_vsi_list_map_info *map_info;\n-\tstruct LIST_HEAD_TYPE *list_head;\n \tstruct ice_adv_rule_info rinfo;\n+\tstruct LIST_HEAD_TYPE *list_head;\n \tstruct ice_switch_info *sw;\n \tenum ice_status status;\n \tu8 rid;\ndiff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h\nindex 7a12619459..c55ef19a8c 100644\n--- a/drivers/net/ice/base/ice_switch.h\n+++ b/drivers/net/ice/base/ice_switch.h\n@@ -71,18 +71,6 @@\n #define ICE_PROFID_IPV6_PFCP_SESSION\t82\n \n #define DUMMY_ETH_HDR_LEN\t\t16\n-#define ICE_SW_RULE_RX_TX_ETH_HDR_SIZE \\\n-\t(offsetof(struct ice_aqc_sw_rules_elem, pdata.lkup_tx_rx.hdr) + \\\n-\t (DUMMY_ETH_HDR_LEN * \\\n-\t sizeof(((struct ice_sw_rule_lkup_rx_tx *)0)->hdr[0])))\n-#define ICE_SW_RULE_RX_TX_NO_HDR_SIZE \\\n-\t(offsetof(struct ice_aqc_sw_rules_elem, pdata.lkup_tx_rx.hdr))\n-#define ICE_SW_RULE_LG_ACT_SIZE(n) \\\n-\t(offsetof(struct ice_aqc_sw_rules_elem, pdata.lg_act.act) + \\\n-\t ((n) * sizeof(((struct ice_sw_rule_lg_act *)0)->act[0])))\n-#define ICE_SW_RULE_VSI_LIST_SIZE(n) \\\n-\t(offsetof(struct ice_aqc_sw_rules_elem, pdata.vsi_list.vsi) + \\\n-\t ((n) * sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi[0])))\n \n /* Worst case buffer length for ice_aqc_opc_get_res_alloc */\n #define ICE_MAX_RES_TYPES 0x80\n", "prefixes": [ "02/30" ] }