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GET /api/patches/126348/?format=api
{ "id": 126348, "url": "https://patches.dpdk.org/api/patches/126348/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230421065048.106899-5-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230421065048.106899-5-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230421065048.106899-5-beilei.xing@intel.com", "date": "2023-04-21T06:50:42", "name": "[04/10] net/cpfl: add haipin queue group during vpotr init", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9bc81935580c63ef31d9589ee6ef63d8f7741a6a", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230421065048.106899-5-beilei.xing@intel.com/mbox/", "series": [ { "id": 27810, "url": "https://patches.dpdk.org/api/series/27810/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27810", "date": "2023-04-21T06:50:38", "name": "add hairpin queue support", "version": 1, "mbox": "https://patches.dpdk.org/series/27810/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/126348/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/126348/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 836CC429A9;\n\tFri, 21 Apr 2023 09:14:22 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 27B0242D2C;\n\tFri, 21 Apr 2023 09:14:00 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id 3E76742D29\n for <dev@dpdk.org>; Fri, 21 Apr 2023 09:13:58 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Apr 2023 00:13:57 -0700", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by orsmga008.jf.intel.com with ESMTP; 21 Apr 2023 00:13:56 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682061238; x=1713597238;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=H24FaLJF++6WE73hgUI4dHlg31lRf4gwNyeJOhTcvrM=;\n b=ZK5nKtfgYdxmK2T2gHMbGS7kvGwHUduD1xh+GRTsImKvkbrhgr1RzOn9\n d+b8xpw1zKu7cfC9G4Weg76po9iLKyp2jzPXsVd0LBMDw8b0IjKMXwf/H\n XDC0bYKPGVYCiv9+v6M06YBzJ+Qvp5b0bx9ZM944HIfakPm6SfPOw+5dc\n hvwb1xcJ5RTxqTiuul0rx7Lyig/VAxBXEHBO402NCop3ro4n99qPH3tn0\n W2QO11UV7VoJIr6CMjGes0qL7wf/HlKNr7D4UfhalQVeKBajY4RHkzbyA\n qu3kjwtGBjDQdXw8PAQ3997jAzBtnWC4Ncmdg1UcqRFXIlw+4TgRmU8D3 w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10686\"; a=\"326260057\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"326260057\"", "E=McAfee;i=\"6600,9927,10686\"; a=\"722669112\"", "E=Sophos;i=\"5.99,214,1677571200\"; d=\"scan'208\";a=\"722669112\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com", "Cc": "dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH 04/10] net/cpfl: add haipin queue group during vpotr init", "Date": "Fri, 21 Apr 2023 06:50:42 +0000", "Message-Id": "<20230421065048.106899-5-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20230421065048.106899-1-beilei.xing@intel.com>", "References": "<20230421065048.106899-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nThis patch adds haipin queue group during vpotr init.\n\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 125 +++++++++++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_ethdev.h | 17 +++++\n drivers/net/cpfl/cpfl_rxtx.h | 4 ++\n 3 files changed, 146 insertions(+)", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 114fc18f5f..ad5ddebd3a 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -856,6 +856,20 @@ cpfl_dev_stop(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n+static int\n+cpfl_p2p_queue_grps_del(struct idpf_vport *vport)\n+{\n+\tstruct virtchnl2_queue_group_id qg_ids[CPFL_P2P_NB_QUEUE_GRPS] = {0};\n+\tint ret = 0;\n+\n+\tqg_ids[0].queue_group_id = CPFL_P2P_QUEUE_GRP_ID;\n+\tqg_ids[0].queue_group_type = VIRTCHNL2_QUEUE_GROUP_P2P;\n+\tret = idpf_vc_queue_grps_del(vport, CPFL_P2P_NB_QUEUE_GRPS, qg_ids);\n+\tif (ret)\n+\t\tPMD_DRV_LOG(ERR, \"Failed to delete p2p queue groups\");\n+\treturn ret;\n+}\n+\n static int\n cpfl_dev_close(struct rte_eth_dev *dev)\n {\n@@ -864,6 +878,9 @@ cpfl_dev_close(struct rte_eth_dev *dev)\n \tstruct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter);\n \n \tcpfl_dev_stop(dev);\n+\n+\tcpfl_p2p_queue_grps_del(vport);\n+\n \tidpf_vport_deinit(vport);\n \n \tadapter->cur_vports &= ~RTE_BIT32(vport->devarg_id);\n@@ -1350,6 +1367,96 @@ cpfl_vport_idx_alloc(struct cpfl_adapter_ext *adapter)\n \treturn vport_idx;\n }\n \n+static int\n+cpfl_p2p_q_grps_add(struct idpf_vport *vport,\n+\t\t struct virtchnl2_add_queue_groups *p2p_queue_grps_info,\n+\t\t uint8_t *p2p_q_vc_out_info)\n+{\n+\tint ret;\n+\n+\tp2p_queue_grps_info->vport_id = vport->vport_id;\n+\tp2p_queue_grps_info->qg_info.num_queue_groups = CPFL_P2P_NB_QUEUE_GRPS;\n+\tp2p_queue_grps_info->qg_info.groups[0].num_rx_q = CPFL_MAX_P2P_NB_QUEUES;\n+\tp2p_queue_grps_info->qg_info.groups[0].num_rx_bufq = CPFL_P2P_NB_RX_BUFQ;\n+\tp2p_queue_grps_info->qg_info.groups[0].num_tx_q = CPFL_MAX_P2P_NB_QUEUES;\n+\tp2p_queue_grps_info->qg_info.groups[0].num_tx_complq = CPFL_P2P_NB_TX_COMPLQ;\n+\tp2p_queue_grps_info->qg_info.groups[0].qg_id.queue_group_id = CPFL_P2P_QUEUE_GRP_ID;\n+\tp2p_queue_grps_info->qg_info.groups[0].qg_id.queue_group_type = VIRTCHNL2_QUEUE_GROUP_P2P;\n+\tp2p_queue_grps_info->qg_info.groups[0].rx_q_grp_info.rss_lut_size = 0;\n+\tp2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.tx_tc = 0;\n+\tp2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.priority = 0;\n+\tp2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.is_sp = 0;\n+\tp2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.pir_weight = 0;\n+\n+\tret = idpf_vc_queue_grps_add(vport, p2p_queue_grps_info, p2p_q_vc_out_info);\n+\tif (ret != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to add p2p queue groups.\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+cpfl_p2p_queue_info_init(struct cpfl_vport *cpfl_vport,\n+\t\t\t struct virtchnl2_add_queue_groups *p2p_q_vc_out_info)\n+{\n+\tstruct p2p_queue_chunks_info *p2p_q_chunks_info = &cpfl_vport->p2p_q_chunks_info;\n+\tstruct virtchnl2_queue_reg_chunks *vc_chunks_out;\n+\tint i, type;\n+\n+\tif (p2p_q_vc_out_info->qg_info.groups[0].qg_id.queue_group_type !=\n+\t VIRTCHNL2_QUEUE_GROUP_P2P) {\n+\t\tPMD_DRV_LOG(ERR, \"Add queue group response mismatch.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tvc_chunks_out = &p2p_q_vc_out_info->qg_info.groups[0].chunks;\n+\n+\tfor (i = 0; i < vc_chunks_out->num_chunks; i++) {\n+\t\ttype = vc_chunks_out->chunks[i].type;\n+\t\tswitch (type) {\n+\t\tcase VIRTCHNL2_QUEUE_TYPE_TX:\n+\t\t\tp2p_q_chunks_info->tx_start_qid =\n+\t\t\t\tvc_chunks_out->chunks[i].start_queue_id;\n+\t\t\tp2p_q_chunks_info->tx_qtail_start =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_start;\n+\t\t\tp2p_q_chunks_info->tx_qtail_spacing =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_spacing;\n+\t\t\tbreak;\n+\t\tcase VIRTCHNL2_QUEUE_TYPE_RX:\n+\t\t\tp2p_q_chunks_info->rx_start_qid =\n+\t\t\t\tvc_chunks_out->chunks[i].start_queue_id;\n+\t\t\tp2p_q_chunks_info->rx_qtail_start =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_start;\n+\t\t\tp2p_q_chunks_info->rx_qtail_spacing =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_spacing;\n+\t\t\tbreak;\n+\t\tcase VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION:\n+\t\t\tp2p_q_chunks_info->tx_compl_start_qid =\n+\t\t\t\tvc_chunks_out->chunks[i].start_queue_id;\n+\t\t\tp2p_q_chunks_info->tx_compl_qtail_start =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_start;\n+\t\t\tp2p_q_chunks_info->tx_compl_qtail_spacing =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_spacing;\n+\t\t\tbreak;\n+\t\tcase VIRTCHNL2_QUEUE_TYPE_RX_BUFFER:\n+\t\t\tp2p_q_chunks_info->rx_buf_start_qid =\n+\t\t\t\tvc_chunks_out->chunks[i].start_queue_id;\n+\t\t\tp2p_q_chunks_info->rx_buf_qtail_start =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_start;\n+\t\t\tp2p_q_chunks_info->rx_buf_qtail_spacing =\n+\t\t\t\tvc_chunks_out->chunks[i].qtail_reg_spacing;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tPMD_DRV_LOG(ERR, \"Unsupported queue type\");\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params)\n {\n@@ -1359,6 +1466,8 @@ cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params)\n \tstruct cpfl_adapter_ext *adapter = param->adapter;\n \t/* for sending create vport virtchnl msg prepare */\n \tstruct virtchnl2_create_vport create_vport_info;\n+\tstruct virtchnl2_add_queue_groups p2p_queue_grps_info;\n+\tuint8_t p2p_q_vc_out_info[IDPF_DFLT_MBX_BUF_SIZE] = {0};\n \tint ret = 0;\n \n \tdev->dev_ops = &cpfl_eth_dev_ops;\n@@ -1380,6 +1489,19 @@ cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params)\n \t\tgoto err;\n \t}\n \n+\tmemset(&p2p_queue_grps_info, 0, sizeof(p2p_queue_grps_info));\n+\tret = cpfl_p2p_q_grps_add(vport, &p2p_queue_grps_info, p2p_q_vc_out_info);\n+\tif (ret != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to add p2p queue group.\");\n+\t\tgoto err_q_grps_add;\n+\t}\n+\tret = cpfl_p2p_queue_info_init(cpfl_vport,\n+\t\t\t\t (struct virtchnl2_add_queue_groups *)p2p_q_vc_out_info);\n+\tif (ret != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init p2p queue info.\");\n+\t\tgoto err_p2p_qinfo_init;\n+\t}\n+\n \tadapter->vports[param->idx] = cpfl_vport;\n \tadapter->cur_vports |= RTE_BIT32(param->devarg_id);\n \tadapter->cur_vport_nb++;\n@@ -1397,6 +1519,9 @@ cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params)\n \treturn 0;\n \n err_mac_addrs:\n+err_p2p_qinfo_init:\n+\tcpfl_p2p_queue_grps_del(vport);\n+err_q_grps_add:\n \tadapter->vports[param->idx] = NULL; /* reset */\n \tidpf_vport_deinit(vport);\n \tadapter->cur_vports &= ~RTE_BIT32(param->devarg_id);\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h\nindex 81fe9ac4c3..5e2e7a1bfb 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.h\n+++ b/drivers/net/cpfl/cpfl_ethdev.h\n@@ -69,8 +69,25 @@ struct cpfl_devargs {\n \tuint16_t req_vport_nb;\n };\n \n+struct p2p_queue_chunks_info {\n+\tuint32_t tx_start_qid;\n+\tuint32_t rx_start_qid;\n+\tuint32_t tx_compl_start_qid;\n+\tuint32_t rx_buf_start_qid;\n+\n+\tuint64_t tx_qtail_start;\n+\tuint32_t tx_qtail_spacing;\n+\tuint64_t rx_qtail_start;\n+\tuint32_t rx_qtail_spacing;\n+\tuint64_t tx_compl_qtail_start;\n+\tuint32_t tx_compl_qtail_spacing;\n+\tuint64_t rx_buf_qtail_start;\n+\tuint32_t rx_buf_qtail_spacing;\n+};\n+\n struct cpfl_vport {\n \tstruct idpf_vport base;\n+\tstruct p2p_queue_chunks_info p2p_q_chunks_info;\n };\n \n struct cpfl_adapter_ext {\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nindex b2b3537d10..3a87a1f4b3 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.h\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -17,6 +17,10 @@\n #define CPFL_MAX_HAIRPINQ_TX_2_RX\t1\n #define CPFL_MAX_HAIRPINQ_NB_DESC\t1024\n #define CPFL_MAX_P2P_NB_QUEUES\t\t16\n+#define CPFL_P2P_NB_RX_BUFQ\t\t1\n+#define CPFL_P2P_NB_TX_COMPLQ\t\t1\n+#define CPFL_P2P_NB_QUEUE_GRPS\t\t1\n+#define CPFL_P2P_QUEUE_GRP_ID\t\t1\n /* Base address of the HW descriptor ring should be 128B aligned. */\n #define CPFL_RING_BASE_ALIGN\t128\n \n", "prefixes": [ "04/10" ] }