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GET /api/patches/125985/?format=api
{ "id": 125985, "url": "https://patches.dpdk.org/api/patches/125985/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230413061650.796940-6-junfeng.guo@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230413061650.796940-6-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230413061650.796940-6-junfeng.guo@intel.com", "date": "2023-04-13T06:16:45", "name": "[05/10] net/gve: support basic Tx data path for DQO", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b30cb22b360b6c5bf75d4d4e8e6f3a943be3a666", "submitter": { "id": 1785, "url": "https://patches.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230413061650.796940-6-junfeng.guo@intel.com/mbox/", "series": [ { "id": 27687, "url": "https://patches.dpdk.org/api/series/27687/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27687", "date": "2023-04-13T06:16:40", "name": "gve PMD enhancement", "version": 1, "mbox": "https://patches.dpdk.org/series/27687/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/125985/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/125985/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 52F7B4292F;\n\tThu, 13 Apr 2023 08:17:41 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E380942C24;\n\tThu, 13 Apr 2023 08:17:25 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 0AC8C42D10\n for <dev@dpdk.org>; Thu, 13 Apr 2023 08:17:24 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Apr 2023 23:17:24 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by fmsmga007.fm.intel.com with ESMTP; 12 Apr 2023 23:17:21 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1681366645; x=1712902645;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=iG5YKTsgb0A5CVyco8WDn7iyjyrferfL8aiE05n6b8w=;\n b=B0Y9FDgia4cvxaJd75zXjQoo7Q6qHIZskLq+MYcPLVB929VUgfpsYYiP\n wiVR2L1voFKAIAu7K0HscDrnomm+Dy8CZxUN4PfC4PA6bT120vVkfesTW\n uJLuSFNh40x6w4Awxp0rMVheOHIN49cJuckITfuv8r5AFIqr0OeUOzc+b\n wvAZnHsh1H1sbcUaJ+c0GSsx+e4h3avajrCpmZ+c7VthblAl1Sri2caMm\n IqAe/O0/vgMxTgWXHywUiiIhZiXc90ncyD6sudvQUKawzMTNLKQwqDpKg\n cDQpLXDYvl6DyIlQt9vynnUV+y3y9BE1E9kkVtq/IB5yEk1MYGEyKrkOv g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10678\"; a=\"341595364\"", "E=Sophos;i=\"5.98,339,1673942400\"; d=\"scan'208\";a=\"341595364\"", "E=McAfee;i=\"6600,9927,10678\"; a=\"691824279\"", "E=Sophos;i=\"5.98,339,1673942400\"; d=\"scan'208\";a=\"691824279\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, Junfeng Guo <junfeng.guo@intel.com>,\n Rushil Gupta <rushilg@google.com>, Joshua Washington <joshwash@google.com>,\n Jeroen de Borst <jeroendb@google.com>", "Subject": "[PATCH 05/10] net/gve: support basic Tx data path for DQO", "Date": "Thu, 13 Apr 2023 14:16:45 +0800", "Message-Id": "<20230413061650.796940-6-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230413061650.796940-1-junfeng.guo@intel.com>", "References": "<20230413061650.796940-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add basic Tx data path support for DQO.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Joshua Washington <joshwash@google.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.c | 1 +\n drivers/net/gve/gve_ethdev.h | 4 +\n drivers/net/gve/gve_tx_dqo.c | 141 +++++++++++++++++++++++++++++++++++\n 3 files changed, 146 insertions(+)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 340315a1a3..37bd8da12d 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -878,6 +878,7 @@ gve_dev_init(struct rte_eth_dev *eth_dev)\n \t\teth_dev->tx_pkt_burst = gve_tx_burst;\n \t} else {\n \t\teth_dev->dev_ops = &gve_eth_dev_ops_dqo;\n+\t\teth_dev->tx_pkt_burst = gve_tx_burst_dqo;\n \t}\n \n \teth_dev->data->mac_addrs = &priv->dev_addr;\ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex c8e1dd1435..1b8f511668 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -147,6 +147,7 @@ struct gve_tx_queue {\n \tuint8_t cur_gen_bit;\n \tuint32_t last_desc_cleaned;\n \tvoid **txqs;\n+\tuint16_t re_cnt;\n \n \t/* Only valid for DQO_RDA queue format */\n \tstruct gve_tx_queue *complq;\n@@ -390,4 +391,7 @@ gve_stop_tx_queues_dqo(struct rte_eth_dev *dev);\n void\n gve_stop_rx_queues_dqo(struct rte_eth_dev *dev);\n \n+uint16_t\n+gve_tx_burst_dqo(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n+\n #endif /* _GVE_ETHDEV_H_ */\ndiff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c\nindex ea6d5ff85e..2ea38a8f8e 100644\n--- a/drivers/net/gve/gve_tx_dqo.c\n+++ b/drivers/net/gve/gve_tx_dqo.c\n@@ -6,6 +6,147 @@\n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n \n+static inline void\n+gve_tx_clean_dqo(struct gve_tx_queue *txq)\n+{\n+\tstruct gve_tx_compl_desc *compl_ring;\n+\tstruct gve_tx_compl_desc *compl_desc;\n+\tstruct gve_tx_queue *aim_txq;\n+\tuint16_t nb_desc_clean;\n+\tstruct rte_mbuf *txe;\n+\tuint16_t compl_tag;\n+\tuint16_t next;\n+\n+\tnext = txq->complq_tail;\n+\tcompl_ring = txq->compl_ring;\n+\tcompl_desc = &compl_ring[next];\n+\n+\tif (compl_desc->generation != txq->cur_gen_bit)\n+\t\treturn;\n+\n+\tcompl_tag = rte_le_to_cpu_16(compl_desc->completion_tag);\n+\n+\taim_txq = txq->txqs[compl_desc->id];\n+\n+\tswitch (compl_desc->type) {\n+\tcase GVE_COMPL_TYPE_DQO_DESC:\n+\t\t/* need to clean Descs from last_cleaned to compl_tag */\n+\t\tif (aim_txq->last_desc_cleaned > compl_tag)\n+\t\t\tnb_desc_clean = aim_txq->nb_tx_desc - aim_txq->last_desc_cleaned +\n+\t\t\t\t\tcompl_tag;\n+\t\telse\n+\t\t\tnb_desc_clean = compl_tag - aim_txq->last_desc_cleaned;\n+\t\taim_txq->nb_free += nb_desc_clean;\n+\t\taim_txq->last_desc_cleaned = compl_tag;\n+\t\tbreak;\n+\tcase GVE_COMPL_TYPE_DQO_REINJECTION:\n+\t\tPMD_DRV_LOG(DEBUG, \"GVE_COMPL_TYPE_DQO_REINJECTION !!!\");\n+\t\t/* FALLTHROUGH */\n+\tcase GVE_COMPL_TYPE_DQO_PKT:\n+\t\ttxe = aim_txq->sw_ring[compl_tag];\n+\t\tif (txe != NULL) {\n+\t\t\trte_pktmbuf_free_seg(txe);\n+\t\t\ttxe = NULL;\n+\t\t}\n+\t\tbreak;\n+\tcase GVE_COMPL_TYPE_DQO_MISS:\n+\t\trte_delay_us_sleep(1);\n+\t\tPMD_DRV_LOG(DEBUG, \"GVE_COMPL_TYPE_DQO_MISS ignored !!!\");\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"unknown completion type.\");\n+\t\treturn;\n+\t}\n+\n+\tnext++;\n+\tif (next == txq->nb_tx_desc * DQO_TX_MULTIPLIER) {\n+\t\tnext = 0;\n+\t\ttxq->cur_gen_bit ^= 1;\n+\t}\n+\n+\ttxq->complq_tail = next;\n+}\n+\n+uint16_t\n+gve_tx_burst_dqo(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct gve_tx_queue *txq = tx_queue;\n+\tvolatile union gve_tx_desc_dqo *txr;\n+\tvolatile union gve_tx_desc_dqo *txd;\n+\tstruct rte_mbuf **sw_ring;\n+\tstruct rte_mbuf *tx_pkt;\n+\tuint16_t mask, sw_mask;\n+\tuint16_t nb_to_clean;\n+\tuint16_t nb_tx = 0;\n+\tuint16_t nb_used;\n+\tuint16_t tx_id;\n+\tuint16_t sw_id;\n+\n+\tsw_ring = txq->sw_ring;\n+\ttxr = txq->tx_ring;\n+\n+\tmask = txq->nb_tx_desc - 1;\n+\tsw_mask = txq->sw_size - 1;\n+\ttx_id = txq->tx_tail;\n+\tsw_id = txq->sw_tail;\n+\n+\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n+\t\ttx_pkt = tx_pkts[nb_tx];\n+\n+\t\tif (txq->nb_free <= txq->free_thresh) {\n+\t\t\tnb_to_clean = DQO_TX_MULTIPLIER * txq->rs_thresh;\n+\t\t\twhile (nb_to_clean--)\n+\t\t\t\tgve_tx_clean_dqo(txq);\n+\t\t}\n+\n+\t\tif (txq->nb_free < tx_pkt->nb_segs)\n+\t\t\tbreak;\n+\n+\t\tnb_used = tx_pkt->nb_segs;\n+\n+\t\tdo {\n+\t\t\ttxd = &txr[tx_id];\n+\n+\t\t\tsw_ring[sw_id] = tx_pkt;\n+\n+\t\t\t/* fill Tx descriptor */\n+\t\t\ttxd->pkt.buf_addr = rte_cpu_to_le_64(rte_mbuf_data_iova(tx_pkt));\n+\t\t\ttxd->pkt.dtype = GVE_TX_PKT_DESC_DTYPE_DQO;\n+\t\t\ttxd->pkt.compl_tag = rte_cpu_to_le_16(sw_id);\n+\t\t\ttxd->pkt.buf_size = RTE_MIN(tx_pkt->data_len, GVE_TX_MAX_BUF_SIZE_DQO);\n+\n+\t\t\t/* size of desc_ring and sw_ring could be different */\n+\t\t\ttx_id = (tx_id + 1) & mask;\n+\t\t\tsw_id = (sw_id + 1) & sw_mask;\n+\n+\t\t\ttx_pkt = tx_pkt->next;\n+\t\t} while (tx_pkt);\n+\n+\t\t/* fill the last descriptor with End of Packet (EOP) bit */\n+\t\ttxd->pkt.end_of_packet = 1;\n+\n+\t\ttxq->nb_free -= nb_used;\n+\t\ttxq->nb_used += nb_used;\n+\t}\n+\n+\t/* update the tail pointer if any packets were processed */\n+\tif (nb_tx > 0) {\n+\t\t/* Request a descriptor completion on the last descriptor */\n+\t\ttxq->re_cnt += nb_tx;\n+\t\tif (txq->re_cnt >= GVE_TX_MIN_RE_INTERVAL) {\n+\t\t\ttxd = &txr[(tx_id - 1) & mask];\n+\t\t\ttxd->pkt.report_event = true;\n+\t\t\ttxq->re_cnt = 0;\n+\t\t}\n+\n+\t\trte_write32(tx_id, txq->qtx_tail);\n+\t\ttxq->tx_tail = tx_id;\n+\t\ttxq->sw_tail = sw_id;\n+\t}\n+\n+\treturn nb_tx;\n+}\n+\n static inline void\n gve_release_txq_mbufs_dqo(struct gve_tx_queue *txq)\n {\n", "prefixes": [ "05/10" ] }