Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/124976/?format=api
{ "id": 124976, "url": "https://patches.dpdk.org/api/patches/124976/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230310082015.20200-25-syalavarthi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230310082015.20200-25-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230310082015.20200-25-syalavarthi@marvell.com", "date": "2023-03-10T08:20:00", "name": "[v6,24/39] ml/cnxk: enable support to dump device debug info", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "882f4318946ba57220f12544108d57477b4fbb37", "submitter": { "id": 2480, "url": "https://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230310082015.20200-25-syalavarthi@marvell.com/mbox/", "series": [ { "id": 27325, "url": "https://patches.dpdk.org/api/series/27325/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27325", "date": "2023-03-10T08:19:36", "name": "Implementation of ML CNXK driver", "version": 6, "mbox": "https://patches.dpdk.org/series/27325/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/124976/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/124976/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 93EC541DD0;\n\tFri, 10 Mar 2023 09:23:36 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0F36A42F92;\n\tFri, 10 Mar 2023 09:21:04 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id F11E742C24\n for <dev@dpdk.org>; Fri, 10 Mar 2023 09:20:32 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 32A7uIdG021875 for <dev@dpdk.org>; Fri, 10 Mar 2023 00:20:32 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p80k782tf-15\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 10 Mar 2023 00:20:32 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Fri, 10 Mar 2023 00:20:23 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Fri, 10 Mar 2023 00:20:23 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 4A1FF5C68E4;\n Fri, 10 Mar 2023 00:20:22 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=GCAJXzyKByo3IyFwqK2tSSbRxaSwe6D9QYTHFXHzsXE=;\n b=XLuwbZMXJ3gIeIXc/EU3IB4L1/PEFAFAj6khT3Qi2QJpYNezxkTQS0/RiXYdeajCUYC3\n +RLXlyF3cY30/x1GHpdOU0CESmCoSCTWhyNEsszZJArILsY1G/QlcBg1eRPcJncbypsW\n PN6llQG0eJLq5uiN2Hgy7c5HQJin6sKVy6tRy9uLdTEbaT+VcdvtQxctapFMBnT7n0ml\n UO4xnJLM9IJ18foGbZe1qzMHqM2arI9/pHW79q4+5pq1at44JJTmesrf7gDQk2vO+Fjg\n 8fRqoGJ2s6OP1SEWJF8NObAFvKOpEQbtTRTP1razjZ/66YU/u8cMuKV8LTPF28weozOT dA==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>, <ptakkar@marvell.com>, <pshukla@marvell.com>", "Subject": "[PATCH v6 24/39] ml/cnxk: enable support to dump device debug info", "Date": "Fri, 10 Mar 2023 00:20:00 -0800", "Message-ID": "<20230310082015.20200-25-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230310082015.20200-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230310082015.20200-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "DISPlb7n5OKAIGmfVh4mI2nCYRgUJSrz", "X-Proofpoint-ORIG-GUID": "DISPlb7n5OKAIGmfVh4mI2nCYRgUJSrz", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-03-10_02,2023-03-09_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added support to dump device debug information. Debug info on\ncn10k device includes model state info, OCM usage info, firmware\ndebug and exception buffer.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_ocm.c | 51 +++++++++\n drivers/ml/cnxk/cn10k_ml_ocm.h | 1 +\n drivers/ml/cnxk/cn10k_ml_ops.c | 189 +++++++++++++++++++++++++++++++++\n 3 files changed, 241 insertions(+)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c\nindex c3e4de3e9c..0b04fcc2da 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.c\n@@ -458,3 +458,54 @@ cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, uint16_t model_id)\n \t\t}\n \t}\n }\n+\n+static void\n+cn10k_ml_ocm_pagemask_to_str(struct cn10k_ml_ocm_tile_info *tile_info, uint16_t nwords, char *str)\n+{\n+\tchar *p = str;\n+\tint word;\n+\n+\t/* add prefix 0x */\n+\t*p++ = '0';\n+\t*p++ = 'x';\n+\n+\t/* build one word at a time */\n+\tfor (word = nwords - 1; word >= 0; word--) {\n+\t\tsprintf(p, \"%02X\", tile_info->ocm_mask[word]);\n+\t\tp += 2;\n+\t}\n+\n+\t/* terminate */\n+\t*p++ = 0;\n+}\n+\n+void\n+cn10k_ml_ocm_print(struct rte_ml_dev *dev, FILE *fp)\n+{\n+\tchar str[ML_CN10K_OCM_NUMPAGES / 4 + 2]; /* nibbles + prefix '0x' */\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_ocm *ocm;\n+\tuint8_t tile_id;\n+\tuint8_t word_id;\n+\tint wb_pages;\n+\n+\tmldev = dev->data->dev_private;\n+\tocm = &mldev->ocm;\n+\n+\tfprintf(fp, \"OCM State:\\n\");\n+\tfor (tile_id = 0; tile_id < ocm->num_tiles; tile_id++) {\n+\t\tcn10k_ml_ocm_pagemask_to_str(&ocm->tile_ocm_info[tile_id], ocm->mask_words, str);\n+\n+\t\twb_pages = 0 - ocm->tile_ocm_info[tile_id].scratch_pages;\n+\t\tfor (word_id = 0; word_id < ML_CN10K_OCM_MASKWORDS; word_id++)\n+\t\t\twb_pages +=\n+\t\t\t\t__builtin_popcount(ocm->tile_ocm_info[tile_id].ocm_mask[word_id]);\n+\n+\t\tfprintf(fp,\n+\t\t\t\"tile = %2u, scratch_pages = %4u,\"\n+\t\t\t\" wb_pages = %4d, last_wb_page = %4d,\"\n+\t\t\t\" pagemask = %s\\n\",\n+\t\t\ttile_id, ocm->tile_ocm_info[tile_id].scratch_pages, wb_pages,\n+\t\t\tocm->tile_ocm_info[tile_id].last_wb_page, str);\n+\t}\n+}\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h\nindex 32c9b17afc..0c7172a671 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.h\n@@ -83,5 +83,6 @@ int cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16\n void cn10k_ml_ocm_reserve_pages(struct rte_ml_dev *dev, uint16_t model_id, uint64_t tilemask,\n \t\t\t\tint wb_page_start, uint16_t wb_pages, uint16_t scratch_pages);\n void cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, uint16_t model_id);\n+void cn10k_ml_ocm_print(struct rte_ml_dev *dev, FILE *fp);\n \n #endif /* _CN10K_ML_OCM_H_ */\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 231c9b340b..2d7d760536 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -14,10 +14,25 @@\n /* ML model macros */\n #define CN10K_ML_MODEL_MEMZONE_NAME \"ml_cn10k_model_mz\"\n \n+/* Debug print width */\n+#define STR_LEN\t 12\n+#define FIELD_LEN 16\n+#define LINE_LEN 90\n+\n /* ML Job descriptor flags */\n #define ML_FLAGS_POLL_COMPL BIT(0)\n #define ML_FLAGS_SSO_COMPL BIT(1)\n \n+static void\n+print_line(FILE *fp, int len)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < len; i++)\n+\t\tfprintf(fp, \"-\");\n+\tfprintf(fp, \"\\n\");\n+}\n+\n static void\n qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n {\n@@ -116,6 +131,102 @@ cn10k_ml_qp_create(const struct rte_ml_dev *dev, uint16_t qp_id, uint32_t nb_des\n \treturn NULL;\n }\n \n+static void\n+cn10k_ml_model_print(struct rte_ml_dev *dev, uint16_t model_id, FILE *fp)\n+{\n+\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_ocm *ocm;\n+\tchar str[STR_LEN];\n+\tuint8_t i;\n+\n+\tmldev = dev->data->dev_private;\n+\tocm = &mldev->ocm;\n+\tmodel = dev->data->models[model_id];\n+\n+\t/* Print debug info */\n+\tprint_line(fp, LINE_LEN);\n+\tfprintf(fp, \" Model Information (%s)\\n\", model->metadata.model.name);\n+\tprint_line(fp, LINE_LEN);\n+\tfprintf(fp, \"%*s : %s\\n\", FIELD_LEN, \"name\", model->metadata.model.name);\n+\tfprintf(fp, \"%*s : %u.%u.%u.%u\\n\", FIELD_LEN, \"version\", model->metadata.model.version[0],\n+\t\tmodel->metadata.model.version[1], model->metadata.model.version[2],\n+\t\tmodel->metadata.model.version[3]);\n+\tif (strlen(model->name) != 0)\n+\t\tfprintf(fp, \"%*s : %s\\n\", FIELD_LEN, \"debug_name\", model->name);\n+\tfprintf(fp, \"%*s : 0x%016lx\\n\", FIELD_LEN, \"model\", PLT_U64_CAST(model));\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"model_id\", model->model_id);\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"batch_size\", model->metadata.model.batch_size);\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"num_layers\", model->metadata.model.num_layers);\n+\n+\t/* Print model state */\n+\tif (model->state == ML_CN10K_MODEL_STATE_LOADED)\n+\t\tfprintf(fp, \"%*s : %s\\n\", FIELD_LEN, \"state\", \"loaded\");\n+\tif (model->state == ML_CN10K_MODEL_STATE_JOB_ACTIVE)\n+\t\tfprintf(fp, \"%*s : %s\\n\", FIELD_LEN, \"state\", \"job_active\");\n+\tif (model->state == ML_CN10K_MODEL_STATE_STARTED)\n+\t\tfprintf(fp, \"%*s : %s\\n\", FIELD_LEN, \"state\", \"started\");\n+\n+\t/* Print OCM status */\n+\tfprintf(fp, \"%*s : %\" PRIu64 \" bytes\\n\", FIELD_LEN, \"wb_size\",\n+\t\tmodel->metadata.model.ocm_wb_range_end - model->metadata.model.ocm_wb_range_start +\n+\t\t\t1);\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"wb_pages\", model->model_mem_map.wb_pages);\n+\tfprintf(fp, \"%*s : %\" PRIu64 \" bytes\\n\", FIELD_LEN, \"scratch_size\",\n+\t\tocm->size_per_tile - model->metadata.model.ocm_tmp_range_floor);\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"scratch_pages\", model->model_mem_map.scratch_pages);\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"num_tiles\",\n+\t\tmodel->metadata.model.tile_end - model->metadata.model.tile_start + 1);\n+\n+\tif (model->state == ML_CN10K_MODEL_STATE_STARTED) {\n+\t\tfprintf(fp, \"%*s : 0x%0*\" PRIx64 \"\\n\", FIELD_LEN, \"tilemask\",\n+\t\t\tML_CN10K_OCM_NUMTILES / 4, model->model_mem_map.tilemask);\n+\t\tfprintf(fp, \"%*s : 0x%x\\n\", FIELD_LEN, \"ocm_wb_start\",\n+\t\t\tmodel->model_mem_map.wb_page_start * ML_CN10K_OCM_PAGESIZE);\n+\t}\n+\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"num_inputs\", model->metadata.model.num_input);\n+\tfprintf(fp, \"%*s : %u\\n\", FIELD_LEN, \"num_outputs\", model->metadata.model.num_output);\n+\tfprintf(fp, \"\\n\");\n+\n+\tprint_line(fp, LINE_LEN);\n+\tfprintf(fp, \"%8s %16s %12s %18s %12s %14s\\n\", \"input\", \"input_name\", \"input_type\",\n+\t\t\"model_input_type\", \"quantize\", \"format\");\n+\tprint_line(fp, LINE_LEN);\n+\tfor (i = 0; i < model->metadata.model.num_input; i++) {\n+\t\tfprintf(fp, \"%8u \", i);\n+\t\tfprintf(fp, \"%*s \", 16, model->metadata.input[i].input_name);\n+\t\trte_ml_io_type_to_str(model->metadata.input[i].input_type, str, STR_LEN);\n+\t\tfprintf(fp, \"%*s \", 12, str);\n+\t\trte_ml_io_type_to_str(model->metadata.input[i].model_input_type, str, STR_LEN);\n+\t\tfprintf(fp, \"%*s \", 18, str);\n+\t\tfprintf(fp, \"%*s\", 12, (model->metadata.input[i].quantize == 1 ? \"Yes\" : \"No\"));\n+\t\trte_ml_io_format_to_str(model->metadata.input[i].shape.format, str, STR_LEN);\n+\t\tfprintf(fp, \"%*s\", 16, str);\n+\t\tfprintf(fp, \"\\n\");\n+\t}\n+\tfprintf(fp, \"\\n\");\n+\n+\tprint_line(fp, LINE_LEN);\n+\tfprintf(fp, \"%8s %16s %12s %18s %12s\\n\", \"output\", \"output_name\", \"output_type\",\n+\t\t\"model_output_type\", \"dequantize\");\n+\tprint_line(fp, LINE_LEN);\n+\tfor (i = 0; i < model->metadata.model.num_output; i++) {\n+\t\tfprintf(fp, \"%8u \", i);\n+\t\tfprintf(fp, \"%*s \", 16, model->metadata.output[i].output_name);\n+\t\trte_ml_io_type_to_str(model->metadata.output[i].output_type, str, STR_LEN);\n+\t\tfprintf(fp, \"%*s \", 12, str);\n+\t\trte_ml_io_type_to_str(model->metadata.output[i].model_output_type, str, STR_LEN);\n+\t\tfprintf(fp, \"%*s \", 18, str);\n+\t\tfprintf(fp, \"%*s\", 12, (model->metadata.output[i].dequantize == 1 ? \"Yes\" : \"No\"));\n+\t\tfprintf(fp, \"\\n\");\n+\t}\n+\tfprintf(fp, \"\\n\");\n+\tprint_line(fp, LINE_LEN);\n+\tfprintf(fp, \"\\n\");\n+}\n+\n static void\n cn10k_ml_prep_sp_job_descriptor(struct cn10k_ml_dev *mldev, struct cn10k_ml_model *model,\n \t\t\t\tstruct cn10k_ml_req *req, enum cn10k_ml_job_type job_type)\n@@ -498,6 +609,83 @@ cn10k_ml_dev_queue_pair_setup(struct rte_ml_dev *dev, uint16_t queue_pair_id,\n \treturn 0;\n }\n \n+static int\n+cn10k_ml_dev_dump(struct rte_ml_dev *dev, FILE *fp)\n+{\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_fw *fw;\n+\n+\tuint32_t head_loc;\n+\tuint32_t tail_loc;\n+\tuint16_t model_id;\n+\tuint32_t bufsize;\n+\tchar *head_ptr;\n+\tint core_id;\n+\n+\tif (roc_env_is_asim())\n+\t\treturn 0;\n+\n+\tmldev = dev->data->dev_private;\n+\tfw = &mldev->fw;\n+\n+\t/* Dump model info */\n+\tfor (model_id = 0; model_id < dev->data->nb_models; model_id++) {\n+\t\tmodel = dev->data->models[model_id];\n+\t\tif (model != NULL) {\n+\t\t\tcn10k_ml_model_print(dev, model_id, fp);\n+\t\t\tfprintf(fp, \"\\n\");\n+\t\t}\n+\t}\n+\n+\t/* Dump OCM state */\n+\tcn10k_ml_ocm_print(dev, fp);\n+\n+\t/* Dump debug buffer */\n+\tfor (core_id = 0; core_id <= 1; core_id++) {\n+\t\tbufsize = fw->req->jd.fw_load.debug.debug_buffer_size;\n+\t\tif (core_id == 0) {\n+\t\t\thead_loc = roc_ml_reg_read64(&mldev->roc, ML_SCRATCH_DBG_BUFFER_HEAD_C0);\n+\t\t\ttail_loc = roc_ml_reg_read64(&mldev->roc, ML_SCRATCH_DBG_BUFFER_TAIL_C0);\n+\t\t\thead_ptr = PLT_PTR_CAST(fw->req->jd.fw_load.debug.core0_debug_ptr);\n+\t\t\thead_ptr = roc_ml_addr_mlip2ap(&mldev->roc, head_ptr);\n+\t\t} else {\n+\t\t\thead_loc = roc_ml_reg_read64(&mldev->roc, ML_SCRATCH_DBG_BUFFER_HEAD_C1);\n+\t\t\ttail_loc = roc_ml_reg_read64(&mldev->roc, ML_SCRATCH_DBG_BUFFER_TAIL_C1);\n+\t\t\thead_ptr = PLT_PTR_CAST(fw->req->jd.fw_load.debug.core1_debug_ptr);\n+\t\t\thead_ptr = roc_ml_addr_mlip2ap(&mldev->roc, head_ptr);\n+\t\t}\n+\t\tif (head_loc < tail_loc) {\n+\t\t\tfprintf(fp, \"%.*s\\n\", tail_loc - head_loc, &head_ptr[head_loc]);\n+\t\t} else if (head_loc >= tail_loc + 1) {\n+\t\t\tfprintf(fp, \"%.*s\\n\", bufsize - tail_loc, &head_ptr[head_loc]);\n+\t\t\tfprintf(fp, \"%.*s\\n\", tail_loc, &head_ptr[0]);\n+\t\t}\n+\t}\n+\n+\t/* Dump exception info */\n+\tfor (core_id = 0; core_id <= 1; core_id++) {\n+\t\tbufsize = fw->req->jd.fw_load.debug.exception_state_size;\n+\t\tif ((core_id == 0) &&\n+\t\t (roc_ml_reg_read64(&mldev->roc, ML_SCRATCH_EXCEPTION_SP_C0) != 0)) {\n+\t\t\thead_ptr = PLT_PTR_CAST(fw->req->jd.fw_load.debug.core0_exception_buffer);\n+\t\t\tfprintf(fp, \"ML_SCRATCH_EXCEPTION_SP_C0 = 0x%016lx\",\n+\t\t\t\troc_ml_reg_read64(&mldev->roc, ML_SCRATCH_EXCEPTION_SP_C0));\n+\t\t\thead_ptr = roc_ml_addr_mlip2ap(&mldev->roc, head_ptr);\n+\t\t\tfprintf(fp, \"%.*s\", bufsize, head_ptr);\n+\t\t} else if ((core_id == 1) &&\n+\t\t\t (roc_ml_reg_read64(&mldev->roc, ML_SCRATCH_EXCEPTION_SP_C1) != 0)) {\n+\t\t\thead_ptr = PLT_PTR_CAST(fw->req->jd.fw_load.debug.core1_exception_buffer);\n+\t\t\tfprintf(fp, \"ML_SCRATCH_EXCEPTION_SP_C1 = 0x%016lx\",\n+\t\t\t\troc_ml_reg_read64(&mldev->roc, ML_SCRATCH_EXCEPTION_SP_C1));\n+\t\t\thead_ptr = roc_ml_addr_mlip2ap(&mldev->roc, head_ptr);\n+\t\t\tfprintf(fp, \"%.*s\", bufsize, head_ptr);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n int\n cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params, uint16_t *model_id)\n {\n@@ -1139,6 +1327,7 @@ struct rte_ml_dev_ops cn10k_ml_ops = {\n \t.dev_close = cn10k_ml_dev_close,\n \t.dev_start = cn10k_ml_dev_start,\n \t.dev_stop = cn10k_ml_dev_stop,\n+\t.dev_dump = cn10k_ml_dev_dump,\n \n \t/* Queue-pair handling ops */\n \t.dev_queue_pair_setup = cn10k_ml_dev_queue_pair_setup,\n", "prefixes": [ "v6", "24/39" ] }