Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/124972/?format=api
{ "id": 124972, "url": "https://patches.dpdk.org/api/patches/124972/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230310082015.20200-39-syalavarthi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230310082015.20200-39-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230310082015.20200-39-syalavarthi@marvell.com", "date": "2023-03-10T08:20:14", "name": "[v6,38/39] ml/cnxk: add user guide for marvell cnxk ml driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3756bee49e0b8b1b308378f076922bd7dd1f8b88", "submitter": { "id": 2480, "url": "https://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230310082015.20200-39-syalavarthi@marvell.com/mbox/", "series": [ { "id": 27325, "url": "https://patches.dpdk.org/api/series/27325/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=27325", "date": "2023-03-10T08:19:36", "name": "Implementation of ML CNXK driver", "version": 6, "mbox": "https://patches.dpdk.org/series/27325/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/124972/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/124972/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0E2D341D3D;\n\tFri, 10 Mar 2023 09:23:15 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A401442DBA;\n\tFri, 10 Mar 2023 09:20:59 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 81C1142C24\n for <dev@dpdk.org>; Fri, 10 Mar 2023 09:20:31 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 32A7aV1M009730; Fri, 10 Mar 2023 00:20:30 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3p7n7dj0a4-17\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Fri, 10 Mar 2023 00:20:30 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Fri, 10 Mar 2023 00:20:25 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Fri, 10 Mar 2023 00:20:25 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id AD8523F7098;\n Fri, 10 Mar 2023 00:20:24 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=QXP5s9lMw0HalDEJt6ny2e60FqPucBaYSMAZa11xPuE=;\n b=NKgDgVBbJqSkbh3Yd3hOCg9GH4AWy3Pdtqgi9aDYH7fyw2nnxr+9q/pNmkVwRd7+gDXV\n cqggBZzcYuilZuECu1JEC0y50LXxO5yxyPPWlab+23mV6L3k97ZbB9Q55Mwhqc7rMU6H\n 2C39YkiBd5KkglMg4e7pLQ5F9PmOBvz/DiRDOGRkC9UqEluXk+FBePTFmwuek93ZImuz\n +fR4MHF2g/pd2ljISVA9l2MA1A3q+90lmYecKCm1w5K7cevv/JMkLP3X7UoB5hQskrkP\n WRM2m6weKc9SFL+NnG1zX+zfFuLPbhCjnDqqewEcNEHnehGMFzDs0w+wnd4OKX4V5+EN 1w==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Thomas Monjalon <thomas@monjalon.net>, Srikanth Yalavarthi\n <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>, <ptakkar@marvell.com>, <pshukla@marvell.com>", "Subject": "[PATCH v6 38/39] ml/cnxk: add user guide for marvell cnxk ml driver", "Date": "Fri, 10 Mar 2023 00:20:14 -0800", "Message-ID": "<20230310082015.20200-39-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230310082015.20200-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230310082015.20200-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "JwHtI9B2uDTWPou51w0WcSJ5LXlMGvhC", "X-Proofpoint-ORIG-GUID": "JwHtI9B2uDTWPou51w0WcSJ5LXlMGvhC", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-03-10_02,2023-03-09_01,2023-02-09_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added user guide for Marvell cnxk ML driver for Marvell Octeon\ncnxk Soc family. Added details about device initialization,\ndebug options and runtime device args supported by the driver.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n MAINTAINERS | 1 +\n doc/guides/index.rst | 1 +\n doc/guides/mldevs/cnxk.rst | 238 ++++++++++++++++++++++++++++++++++++\n doc/guides/mldevs/index.rst | 14 +++\n 4 files changed, 254 insertions(+)\n create mode 100644 doc/guides/mldevs/cnxk.rst\n create mode 100644 doc/guides/mldevs/index.rst", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 8f695516c7..ae6c4decbe 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1450,6 +1450,7 @@ M: Srikanth Yalavarthi <syalavarthi@marvell.com>\n F: drivers/common/cnxk/hw/ml.h\n F: drivers/common/cnxk/roc_ml*\n F: drivers/ml/cnxk/\n+F: doc/guides/mldevs/cnxk.rst\n \n \n Packet processing\ndiff --git a/doc/guides/index.rst b/doc/guides/index.rst\nindex 5eb5bd9c9a..0bd729530a 100644\n--- a/doc/guides/index.rst\n+++ b/doc/guides/index.rst\n@@ -26,6 +26,7 @@ DPDK documentation\n eventdevs/index\n rawdevs/index\n mempool/index\n+ mldevs/index\n platform/index\n contributing/index\n rel_notes/index\ndiff --git a/doc/guides/mldevs/cnxk.rst b/doc/guides/mldevs/cnxk.rst\nnew file mode 100644\nindex 0000000000..da40336299\n--- /dev/null\n+++ b/doc/guides/mldevs/cnxk.rst\n@@ -0,0 +1,238 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright (c) 2022 Marvell.\n+\n+Marvell cnxk Machine Learning Poll Mode Driver\n+==============================================\n+\n+The cnxk ML poll mode driver provides support for offloading Machine\n+Learning inference operations to Machine Learning accelerator units\n+on the **Marvell OCTEON cnxk** SoC family.\n+\n+The cnxk ML PMD code is organized into multiple files with all file names\n+starting with cn10k, providing support for CN106XX and CN106XXS.\n+\n+More information about OCTEON cnxk SoCs may be obtained from `<https://www.marvell.com>`_\n+\n+Supported OCTEON cnxk SoCs\n+--------------------------\n+\n+- CN106XX\n+- CN106XXS\n+\n+Features\n+--------\n+\n+The OCTEON cnxk ML PMD provides support for the following set of operations:\n+\n+Slow-path device and ML model handling:\n+\n+* ``Device probing, configuration and close``\n+* ``Device start / stop``\n+* ``Model loading and unloading``\n+* ``Model start / stop``\n+* ``Data quantization and dequantization``\n+\n+Fast-path Inference:\n+\n+* ``Inference execution``\n+* ``Error handling``\n+\n+\n+Installation\n+------------\n+\n+The OCTEON cnxk ML PMD may be compiled natively on an OCTEON cnxk platform\n+or cross-compiled on an x86 platform.\n+\n+Refer to :doc:`../platform/cnxk` for instructions to build your DPDK\n+application.\n+\n+\n+Initialization\n+--------------\n+\n+``CN10K Initialization``\n+\n+List the ML PF devices available on cn10k platform:\n+\n+.. code-block:: console\n+\n+ lspci -d:a092\n+\n+``a092`` is the ML device PF id. You should see output similar to:\n+\n+.. code-block:: console\n+\n+ 0000:00:10.0 System peripheral: Cavium, Inc. Device a092\n+\n+Bind the ML PF device to the vfio_pci driver:\n+\n+.. code-block:: console\n+\n+ cd <dpdk directory>\n+ ./usertools/dpdk-devbind.py -u 0000:00:10.0\n+ ./usertools/dpdk-devbind.py -b vfio-pci 0000:00:10.0\n+\n+Runtime Config Options\n+----------------------\n+\n+- ``Firmware file path`` (default ``/lib/firmware/mlip-fw.bin``)\n+\n+ Path to the firmware binary to be loaded during device configuration.\n+ The ``fw_path`` ``devargs`` parameter can be used by the user to load\n+ ML firmware from a custom path.\n+\n+ For example::\n+\n+ -a 0000:00:10.0,fw_path=\"/home/user/ml_fw.bin\"\n+\n+ With the above configuration, driver loads the firmware from the path\n+ \"/home/user/ml_fw.bin\".\n+\n+- ``Enable DPE warnings`` (default ``1``)\n+\n+ ML firmware can be configured during load to handle the DPE errors reported\n+ by ML inference engine. When enabled, firmware would mask the DPE non-fatal\n+ hardware errors as warnings. The parameter ``enable_dpe_warnings`` ``devargs``\n+ is used fo this configuration.\n+\n+ For example::\n+\n+ -a 0000:00:10.0,enable_dpe_warnings=0\n+\n+ With the above configuration, DPE non-fatal errors reported by HW are\n+ considered as errors.\n+\n+\n+- ``Model data caching`` (default ``1``)\n+\n+ Enable caching model data on ML ACC cores. Enabling this option executes a\n+ dummy inference request in synchronous mode during model start stage. Caching\n+ of model data improves the inferencing throughput / latency for the model.\n+ The parameter ``cache_model_data`` ``devargs`` is used to enable data caching.\n+\n+ For example::\n+\n+ -a 0000:00:10.0,cache_model_data=0\n+\n+ With the above configuration, model data caching is disabled.\n+\n+\n+- ``OCM allocation mode`` (default ``lowest``)\n+\n+ Option to specify the method to be used while allocating OCM memory for a\n+ model during model start. Two modes are supported by the driver. The\n+ parameter ``ocm_alloc_mode`` ``devargs`` is used to select the OCM\n+ allocation mode.\n+\n+ ``lowest`` - Allocate OCM for the model from first available free slot. Search\n+ for the free slot is done starting from the lowest tile ID and lowest page ID.\n+ ``largest`` - Allocate OCM for the model from the slot with largest amount of\n+ free space.\n+\n+ For example::\n+\n+ -a 0000:00:10.0,ocm_alloc_mode=lowest\n+\n+ With the above configuration, OCM allocation fo the model would be done from\n+ the first available free slot / from the lowest possible tile ID.\n+\n+\n+- ``Enable hardware queue lock`` (default ``0``)\n+\n+ Option to select the job request enqueue function to used to queue the requests\n+ to hardware queue. The parameter ``hw_queue_lock`` ``devargs`` is used to select\n+ the enqueue function.\n+\n+ ``0`` - Disable (default), use lock free version of hardware enqueue function\n+ for job queuing in enqueue burst operation. To avoid race condition in request\n+ queuing to hardware, disabling hw_queue_lock restricts the number of queue-pairs\n+ supported by cnxk driver to 1.\n+ ``1`` - Enable, use spin-lock version of hardware enqueue function for job queuing.\n+ Enabling spinlock version would disable restrictions on the number of queue-pairs\n+ that can be supported by the driver.\n+\n+ For example::\n+\n+ -a 0000:00:10.0,hw_queue_lock=1\n+\n+ With the above configuration, spinlock version of hardware enqueue function is used\n+ in the fast path enqueue burst operation.\n+\n+\n+- ``Polling memory location`` (default ``ddr``)\n+\n+ ML cnxk driver provides the option to select the memory location to be used\n+ for polling to check the inference request completion. Driver supports using\n+ the either DDR address space (``ddr``) or ML registers (``register``) as\n+ polling locations. The parameter ``poll_mem`` ``devargs`` is used to specify\n+ the poll location.\n+\n+ For example::\n+\n+ -a 0000:00:10.0,poll_mem=\"register\"\n+\n+ With the above configuration, ML cnxk driver is configured to use ML registers\n+ for polling in fastpath requests.\n+\n+\n+Debugging Options\n+-----------------\n+\n+.. _table_octeon_cnxk_ml_debug_options:\n+\n+.. table:: OCTEON cnxk ML PMD debug options\n+\n+ +---+------------+-------------------------------------------------------+\n+ | # | Component | EAL log command |\n+ +===+============+=======================================================+\n+ | 1 | ML | --log-level='pmd\\.ml\\.cnxk,8' |\n+ +---+------------+-------------------------------------------------------+\n+\n+\n+Extended stats\n+--------------\n+\n+Marvell cnxk ML PMD supports reporting the inference latencies through extended\n+stats. The PMD supports the below list of 6 extended stats types per each model.\n+Total number of extended stats would be equal to 6 x number of models loaded.\n+\n+.. _table_octeon_cnxk_ml_xstats_names:\n+\n+.. table:: OCTEON cnxk ML PMD xstats names\n+\n+ +---+---------------------+----------------------------------------------+\n+ | # | Type | Description |\n+ +===+=====================+==============================================+\n+ | 1 | Avg-HW-Latency | Average hardware latency |\n+ +---+---------------------+----------------------------------------------+\n+ | 2 | Min-HW-Latency | Minimum hardware latency |\n+ +---+---------------------+----------------------------------------------+\n+ | 3 | Max-HW-Latency | Maximum hardware latency |\n+ +---+---------------------+----------------------------------------------+\n+ | 4 | Avg-HW-Latency | Average firmware latency |\n+ +---+---------------------+----------------------------------------------+\n+ | 5 | Avg-HW-Latency | Minimum firmware latency |\n+ +---+---------------------+----------------------------------------------+\n+ | 6 | Avg-HW-Latency | Maximum firmware latency |\n+ +---+---------------------+----------------------------------------------+\n+\n+Latency values reported by the PMD through xstats can have units, either in\n+cycles or nano seconds. The units of the latency is determined during DPDK\n+initialization and would depend on the availability of SCLK. Latencies are\n+reported in nao seconds when the SCLK is available and in cycles otherwise.\n+Application needs to initialize at least one RVU for the clock to be available.\n+\n+xstats names are dynamically generated by the PMD and would have the format\n+\"Model-<model_id>-Type-<units>\".\n+\n+For example::\n+ Model-1-Avg-FW-Latency-ns\n+\n+The above xstat name would report average firmware latency in nano seconds for\n+model with model ID 1.\n+\n+Number of xstats made available by the PMD change dynamically. The number would\n+increase with loading a model and would decrease with unloading a model.\n+Application needs to update the xstats map after a model is either loaded or\n+unloaded.\ndiff --git a/doc/guides/mldevs/index.rst b/doc/guides/mldevs/index.rst\nnew file mode 100644\nindex 0000000000..f201e54175\n--- /dev/null\n+++ b/doc/guides/mldevs/index.rst\n@@ -0,0 +1,14 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright (c) 2022 Marvell.\n+\n+Machine Learning Device Driver\n+==============================\n+\n+The following are a list of ML device PMDs, which can be used from an\n+application through the ML device API.\n+\n+.. toctree::\n+ :maxdepth: 2\n+ :numbered:\n+\n+ cnxk\n", "prefixes": [ "v6", "38/39" ] }