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GET /api/patches/123737/?format=api
{ "id": 123737, "url": "https://patches.dpdk.org/api/patches/123737/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230213021956.2953088-2-mingxia.liu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230213021956.2953088-2-mingxia.liu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230213021956.2953088-2-mingxia.liu@intel.com", "date": "2023-02-13T02:19:36", "name": "[v6,01/21] net/cpfl: support device initialization", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "16f37e808a68a47239d950bbaa7a9092ea024ce0", "submitter": { "id": 2514, "url": "https://patches.dpdk.org/api/people/2514/?format=api", "name": "Liu, Mingxia", "email": "mingxia.liu@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230213021956.2953088-2-mingxia.liu@intel.com/mbox/", "series": [ { "id": 26969, "url": "https://patches.dpdk.org/api/series/26969/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26969", "date": "2023-02-13T02:19:35", "name": "add support for cpfl PMD in DPDK", "version": 6, "mbox": "https://patches.dpdk.org/series/26969/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/123737/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/123737/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0499941C7F;\n\tMon, 13 Feb 2023 04:17:32 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 527DC41151;\n\tMon, 13 Feb 2023 04:17:27 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 91E4A40A81\n for <dev@dpdk.org>; Mon, 13 Feb 2023 04:17:23 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Feb 2023 19:17:23 -0800", "from dpdk-mingxial-01.sh.intel.com ([10.67.119.167])\n by fmsmga002.fm.intel.com with ESMTP; 12 Feb 2023 19:17:21 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1676258243; x=1707794243;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=q+5r01iNR/xzSzhjABz8D4gtKt7y416gRXRWHYOQOjc=;\n b=GQexbfW0MTOl07l0Zh8hQEI1x43uda9C1amj5CFMmVTYFfHRsNswN1zv\n sdJRxiQ021pePbEEwjpBRU0xl35q22nNcEvPCSvKYsufEbiZMge2cLm3G\n /PGh6XFLbW4eizk+f4LpSsib7cVAiq7a92jeQtT3LPV1ub63E43J3l5+Z\n y7LaE2j2aCaFqtYL3RFyGiJC+8meIoQq7XGOuxGw9WShUlbJeI3FL46qf\n 1AWSpE5gXP7eUKfX/13Nw53xpjt8ZfodvWfRCEo9/dx882eeiITk2JbXf\n vTJEj+qbjfEZRFxcUmUZk6Wm4y7VgqC1/Pa6ZpNSAeBkia5TIo1iM6OPh A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10619\"; a=\"328504007\"", "E=Sophos;i=\"5.97,291,1669104000\"; d=\"scan'208\";a=\"328504007\"", "E=McAfee;i=\"6500,9779,10619\"; a=\"777657880\"", "E=Sophos;i=\"5.97,291,1669104000\"; d=\"scan'208\";a=\"777657880\"" ], "X-ExtLoop1": "1", "From": "Mingxia Liu <mingxia.liu@intel.com>", "To": "dev@dpdk.org,\n\tbeilei.xing@intel.com,\n\tyuying.zhang@intel.com", "Cc": "Mingxia Liu <mingxia.liu@intel.com>", "Subject": "[PATCH v6 01/21] net/cpfl: support device initialization", "Date": "Mon, 13 Feb 2023 02:19:36 +0000", "Message-Id": "<20230213021956.2953088-2-mingxia.liu@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230213021956.2953088-1-mingxia.liu@intel.com>", "References": "<20230209084541.2712723-1-mingxia.liu@intel.com>\n <20230213021956.2953088-1-mingxia.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Support device init and add the following dev ops:\n - dev_configure\n - dev_close\n - dev_infos_get\n - link_update\n - dev_supported_ptypes_get\n\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\n---\n MAINTAINERS | 8 +\n doc/guides/nics/cpfl.rst | 66 +++\n doc/guides/nics/features/cpfl.ini | 12 +\n doc/guides/rel_notes/release_23_03.rst | 6 +\n drivers/net/cpfl/cpfl_ethdev.c | 768 +++++++++++++++++++++++++\n drivers/net/cpfl/cpfl_ethdev.h | 78 +++\n drivers/net/cpfl/cpfl_logs.h | 32 ++\n drivers/net/cpfl/cpfl_rxtx.c | 244 ++++++++\n drivers/net/cpfl/cpfl_rxtx.h | 25 +\n drivers/net/cpfl/meson.build | 14 +\n drivers/net/meson.build | 1 +\n 11 files changed, 1254 insertions(+)\n create mode 100644 doc/guides/nics/cpfl.rst\n create mode 100644 doc/guides/nics/features/cpfl.ini\n create mode 100644 drivers/net/cpfl/cpfl_ethdev.c\n create mode 100644 drivers/net/cpfl/cpfl_ethdev.h\n create mode 100644 drivers/net/cpfl/cpfl_logs.h\n create mode 100644 drivers/net/cpfl/cpfl_rxtx.c\n create mode 100644 drivers/net/cpfl/cpfl_rxtx.h\n create mode 100644 drivers/net/cpfl/meson.build", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 9a0f416d2e..af80edaf6e 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -783,6 +783,14 @@ F: drivers/common/idpf/\n F: doc/guides/nics/idpf.rst\n F: doc/guides/nics/features/idpf.ini\n \n+Intel cpfl\n+M: Yuying Zhang <yuying.zhang@intel.com>\n+M: Beilei Xing <beilei.xing@intel.com>\n+T: git://dpdk.org/next/dpdk-next-net-intel\n+F: drivers/net/cpfl/\n+F: doc/guides/nics/cpfl.rst\n+F: doc/guides/nics/features/cpfl.ini\n+\n Intel igc\n M: Junfeng Guo <junfeng.guo@intel.com>\n M: Simei Su <simei.su@intel.com>\ndiff --git a/doc/guides/nics/cpfl.rst b/doc/guides/nics/cpfl.rst\nnew file mode 100644\nindex 0000000000..7c5aff0789\n--- /dev/null\n+++ b/doc/guides/nics/cpfl.rst\n@@ -0,0 +1,66 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2022 Intel Corporation.\n+\n+.. include:: <isonum.txt>\n+\n+CPFL Poll Mode Driver\n+=====================\n+\n+The [*EXPERIMENTAL*] cpfl PMD (**librte_net_cpfl**) provides poll mode driver support\n+for Intel\\ |reg| Infrastructure Processing Unit (Intel\\ |reg| IPU) E2100.\n+\n+\n+Linux Prerequisites\n+-------------------\n+\n+Follow the DPDK :doc:`../linux_gsg/index` to setup the basic DPDK environment.\n+\n+To get better performance on Intel platforms,\n+please follow the :doc:`../linux_gsg/nic_perf_intel_platform`.\n+\n+\n+Pre-Installation Configuration\n+------------------------------\n+\n+Runtime Config Options\n+~~~~~~~~~~~~~~~~~~~~~~\n+\n+- ``vport`` (default ``0``)\n+\n+ The PMD supports creation of multiple vports for one PCI device,\n+ each vport corresponds to a single ethdev.\n+ The user can specify the vports with specific ID to be created, for example::\n+\n+ -a ca:00.0,vport=[0,2,3]\n+\n+ Then the PMD will create 3 vports (ethdevs) for device ``ca:00.0``.\n+\n+ If the parameter is not provided, the vport 0 will be created by default.\n+\n+- ``rx_single`` (default ``0``)\n+\n+ There are two queue modes supported by Intel\\ |reg| IPU Ethernet E2100 Series,\n+ single queue mode and split queue mode for Rx queue.\n+ User can choose Rx queue mode, example::\n+\n+ -a ca:00.0,rx_single=1\n+\n+ Then the PMD will configure Rx queue with single queue mode.\n+ Otherwise, split queue mode is chosen by default.\n+\n+- ``tx_single`` (default ``0``)\n+\n+ There are two queue modes supported by Intel\\ |reg| IPU Ethernet E2100 Series,\n+ single queue mode and split queue mode for Tx queue.\n+ User can choose Tx queue mode, example::\n+\n+ -a ca:00.0,tx_single=1\n+\n+ Then the PMD will configure Tx queue with single queue mode.\n+ Otherwise, split queue mode is chosen by default.\n+\n+\n+Driver compilation and testing\n+------------------------------\n+\n+Refer to the document :doc:`build_and_test` for details.\n\\ No newline at end of file\ndiff --git a/doc/guides/nics/features/cpfl.ini b/doc/guides/nics/features/cpfl.ini\nnew file mode 100644\nindex 0000000000..a2d1ca9e15\n--- /dev/null\n+++ b/doc/guides/nics/features/cpfl.ini\n@@ -0,0 +1,12 @@\n+;\n+; Supported features of the 'cpfl' network poll mode driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+; A feature with \"P\" indicates only be supported when non-vector path\n+; is selected.\n+;\n+[Features]\n+Linux = Y\n+x86-32 = Y\n+x86-64 = Y\ndiff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst\nindex 07914170a7..b0b23d1a44 100644\n--- a/doc/guides/rel_notes/release_23_03.rst\n+++ b/doc/guides/rel_notes/release_23_03.rst\n@@ -88,6 +88,12 @@ New Features\n * Added timesync API support.\n * Added packet pacing(launch time offloading) support.\n \n+* **Added Intel cpfl driver.**\n+\n+ Added the new ``cpfl`` net driver\n+ for Intel\\ |reg| Infrastructure Processing Unit (Intel\\ |reg| IPU) E2100.\n+ See the :doc:`../nics/cpfl` NIC guide for more details on this new driver.\n+\n Removed Items\n -------------\n \ndiff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nnew file mode 100644\nindex 0000000000..fe0061133c\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -0,0 +1,768 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#include <rte_atomic.h>\n+#include <rte_eal.h>\n+#include <rte_ether.h>\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+#include <rte_dev.h>\n+#include <errno.h>\n+#include <rte_alarm.h>\n+\n+#include \"cpfl_ethdev.h\"\n+\n+#define CPFL_TX_SINGLE_Q\t\"tx_single\"\n+#define CPFL_RX_SINGLE_Q\t\"rx_single\"\n+#define CPFL_VPORT\t\t\"vport\"\n+\n+rte_spinlock_t cpfl_adapter_lock;\n+/* A list for all adapters, one adapter matches one PCI device */\n+struct cpfl_adapter_list cpfl_adapter_list;\n+bool cpfl_adapter_list_init;\n+\n+static const char * const cpfl_valid_args[] = {\n+\tCPFL_TX_SINGLE_Q,\n+\tCPFL_RX_SINGLE_Q,\n+\tCPFL_VPORT,\n+\tNULL\n+};\n+\n+static int\n+cpfl_dev_link_update(struct rte_eth_dev *dev,\n+\t\t __rte_unused int wait_to_complete)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct rte_eth_link new_link;\n+\n+\tmemset(&new_link, 0, sizeof(new_link));\n+\n+\tswitch (vport->link_speed) {\n+\tcase RTE_ETH_SPEED_NUM_10M:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_10M;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_100M:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_100M;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_1G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_1G;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_10G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_10G;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_20G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_20G;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_25G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_25G;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_40G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_40G;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_50G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_50G;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_100G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_100G;\n+\t\tbreak;\n+\tcase RTE_ETH_SPEED_NUM_200G:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_200G;\n+\t\tbreak;\n+\tdefault:\n+\t\tnew_link.link_speed = RTE_ETH_SPEED_NUM_NONE;\n+\t}\n+\n+\tnew_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;\n+\tnew_link.link_status = vport->link_up ? RTE_ETH_LINK_UP :\n+\t\tRTE_ETH_LINK_DOWN;\n+\tnew_link.link_autoneg = (dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED) ?\n+\t\t\t\t RTE_ETH_LINK_FIXED : RTE_ETH_LINK_AUTONEG;\n+\n+\treturn rte_eth_linkstatus_set(dev, &new_link);\n+}\n+\n+static int\n+cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\n+\tdev_info->max_rx_queues = adapter->caps.max_rx_q;\n+\tdev_info->max_tx_queues = adapter->caps.max_tx_q;\n+\tdev_info->min_rx_bufsize = CPFL_MIN_BUF_SIZE;\n+\tdev_info->max_rx_pktlen = vport->max_mtu + CPFL_ETH_OVERHEAD;\n+\n+\tdev_info->max_mtu = vport->max_mtu;\n+\tdev_info->min_mtu = RTE_ETHER_MIN_MTU;\n+\n+\treturn 0;\n+}\n+\n+static const uint32_t *\n+cpfl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)\n+{\n+\tstatic const uint32_t ptypes[] = {\n+\t\tRTE_PTYPE_L2_ETHER,\n+\t\tRTE_PTYPE_L3_IPV4_EXT_UNKNOWN,\n+\t\tRTE_PTYPE_L3_IPV6_EXT_UNKNOWN,\n+\t\tRTE_PTYPE_L4_FRAG,\n+\t\tRTE_PTYPE_L4_UDP,\n+\t\tRTE_PTYPE_L4_TCP,\n+\t\tRTE_PTYPE_L4_SCTP,\n+\t\tRTE_PTYPE_L4_ICMP,\n+\t\tRTE_PTYPE_UNKNOWN\n+\t};\n+\n+\treturn ptypes;\n+}\n+\n+static int\n+cpfl_dev_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_conf *conf = &dev->data->dev_conf;\n+\n+\tif (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {\n+\t\tPMD_INIT_LOG(ERR, \"Setting link speed is not supported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (conf->txmode.mq_mode != RTE_ETH_MQ_TX_NONE) {\n+\t\tPMD_INIT_LOG(ERR, \"Multi-queue TX mode %d is not supported\",\n+\t\t\t conf->txmode.mq_mode);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (conf->lpbk_mode != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Loopback operation mode %d is not supported\",\n+\t\t\t conf->lpbk_mode);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (conf->dcb_capability_en != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Priority Flow Control(PFC) if not supported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (conf->intr_conf.lsc != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"LSC interrupt is not supported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (conf->intr_conf.rxq != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"RXQ interrupt is not supported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tif (conf->intr_conf.rmv != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"RMV interrupt is not supported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_dev_close(struct rte_eth_dev *dev)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter);\n+\n+\tidpf_vport_deinit(vport);\n+\n+\tadapter->cur_vports &= ~RTE_BIT32(vport->devarg_id);\n+\tadapter->cur_vport_nb--;\n+\tdev->data->dev_private = NULL;\n+\tadapter->vports[vport->sw_idx] = NULL;\n+\trte_free(vport);\n+\n+\treturn 0;\n+}\n+\n+static int\n+insert_value(struct cpfl_devargs *devargs, uint16_t id)\n+{\n+\tuint16_t i;\n+\n+\t/* ignore duplicate */\n+\tfor (i = 0; i < devargs->req_vport_nb; i++) {\n+\t\tif (devargs->req_vports[i] == id)\n+\t\t\treturn 0;\n+\t}\n+\n+\tif (devargs->req_vport_nb >= RTE_DIM(devargs->req_vports)) {\n+\t\tPMD_INIT_LOG(ERR, \"Total vport number can't be > %d\",\n+\t\t\t CPFL_MAX_VPORT_NUM);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdevargs->req_vports[devargs->req_vport_nb] = id;\n+\tdevargs->req_vport_nb++;\n+\n+\treturn 0;\n+}\n+\n+static const char *\n+parse_range(const char *value, struct cpfl_devargs *devargs)\n+{\n+\tuint16_t lo, hi, i;\n+\tint n = 0;\n+\tint result;\n+\tconst char *pos = value;\n+\n+\tresult = sscanf(value, \"%hu%n-%hu%n\", &lo, &n, &hi, &n);\n+\tif (result == 1) {\n+\t\tif (lo >= CPFL_MAX_VPORT_NUM)\n+\t\t\treturn NULL;\n+\t\tif (insert_value(devargs, lo) != 0)\n+\t\t\treturn NULL;\n+\t} else if (result == 2) {\n+\t\tif (lo > hi || hi >= CPFL_MAX_VPORT_NUM)\n+\t\t\treturn NULL;\n+\t\tfor (i = lo; i <= hi; i++) {\n+\t\t\tif (insert_value(devargs, i) != 0)\n+\t\t\t\treturn NULL;\n+\t\t}\n+\t} else {\n+\t\treturn NULL;\n+\t}\n+\n+\treturn pos + n;\n+}\n+\n+static int\n+parse_vport(const char *key, const char *value, void *args)\n+{\n+\tstruct cpfl_devargs *devargs = args;\n+\tconst char *pos = value;\n+\n+\tdevargs->req_vport_nb = 0;\n+\n+\tif (*pos == '[')\n+\t\tpos++;\n+\n+\twhile (1) {\n+\t\tpos = parse_range(pos, devargs);\n+\t\tif (pos == NULL) {\n+\t\t\tPMD_INIT_LOG(ERR, \"invalid value:\\\"%s\\\" for key:\\\"%s\\\", \",\n+\t\t\t\t value, key);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (*pos != ',')\n+\t\t\tbreak;\n+\t\tpos++;\n+\t}\n+\n+\tif (*value == '[' && *pos != ']') {\n+\t\tPMD_INIT_LOG(ERR, \"invalid value:\\\"%s\\\" for key:\\\"%s\\\", \",\n+\t\t\t value, key);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_bool(const char *key, const char *value, void *args)\n+{\n+\tint *i = args;\n+\tchar *end;\n+\tint num;\n+\n+\terrno = 0;\n+\n+\tnum = strtoul(value, &end, 10);\n+\n+\tif (errno == ERANGE || (num != 0 && num != 1)) {\n+\t\tPMD_INIT_LOG(ERR, \"invalid value:\\\"%s\\\" for key:\\\"%s\\\", value must be 0 or 1\",\n+\t\t\tvalue, key);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*i = num;\n+\treturn 0;\n+}\n+\n+static int\n+cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter,\n+\t\t struct cpfl_devargs *cpfl_args)\n+{\n+\tstruct rte_devargs *devargs = pci_dev->device.devargs;\n+\tstruct rte_kvargs *kvlist;\n+\tint i, ret;\n+\n+\tcpfl_args->req_vport_nb = 0;\n+\n+\tif (devargs == NULL)\n+\t\treturn 0;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, cpfl_valid_args);\n+\tif (kvlist == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"invalid kvargs key\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* check parsed devargs */\n+\tif (adapter->cur_vport_nb + cpfl_args->req_vport_nb >\n+\t CPFL_MAX_VPORT_NUM) {\n+\t\tPMD_INIT_LOG(ERR, \"Total vport number can't be > %d\",\n+\t\t\t CPFL_MAX_VPORT_NUM);\n+\t\tret = -EINVAL;\n+\t\tgoto bail;\n+\t}\n+\n+\tfor (i = 0; i < cpfl_args->req_vport_nb; i++) {\n+\t\tif (adapter->cur_vports & RTE_BIT32(cpfl_args->req_vports[i])) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Vport %d has been created\",\n+\t\t\t\t cpfl_args->req_vports[i]);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto bail;\n+\t\t}\n+\t}\n+\n+\tret = rte_kvargs_process(kvlist, CPFL_VPORT, &parse_vport,\n+\t\t\t\t cpfl_args);\n+\tif (ret != 0)\n+\t\tgoto bail;\n+\n+\tret = rte_kvargs_process(kvlist, CPFL_TX_SINGLE_Q, &parse_bool,\n+\t\t\t\t &adapter->base.txq_model);\n+\tif (ret != 0)\n+\t\tgoto bail;\n+\n+\tret = rte_kvargs_process(kvlist, CPFL_RX_SINGLE_Q, &parse_bool,\n+\t\t\t\t &adapter->base.rxq_model);\n+\tif (ret != 0)\n+\t\tgoto bail;\n+\n+bail:\n+\trte_kvargs_free(kvlist);\n+\treturn ret;\n+}\n+\n+static struct idpf_vport *\n+cpfl_find_vport(struct cpfl_adapter_ext *adapter, uint32_t vport_id)\n+{\n+\tstruct idpf_vport *vport = NULL;\n+\tint i;\n+\n+\tfor (i = 0; i < adapter->cur_vport_nb; i++) {\n+\t\tvport = adapter->vports[i];\n+\t\tif (vport->vport_id != vport_id)\n+\t\t\tcontinue;\n+\t\telse\n+\t\t\treturn vport;\n+\t}\n+\n+\treturn vport;\n+}\n+\n+static void\n+cpfl_handle_event_msg(struct idpf_vport *vport, uint8_t *msg, uint16_t msglen)\n+{\n+\tstruct virtchnl2_event *vc_event = (struct virtchnl2_event *)msg;\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)vport->dev;\n+\n+\tif (msglen < sizeof(struct virtchnl2_event)) {\n+\t\tPMD_DRV_LOG(ERR, \"Error event\");\n+\t\treturn;\n+\t}\n+\n+\tswitch (vc_event->event) {\n+\tcase VIRTCHNL2_EVENT_LINK_CHANGE:\n+\t\tPMD_DRV_LOG(DEBUG, \"VIRTCHNL2_EVENT_LINK_CHANGE\");\n+\t\tvport->link_up = !!(vc_event->link_status);\n+\t\tvport->link_speed = vc_event->link_speed;\n+\t\tcpfl_dev_link_update(dev, 0);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \" unknown event received %u\", vc_event->event);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void\n+cpfl_handle_virtchnl_msg(struct cpfl_adapter_ext *adapter_ex)\n+{\n+\tstruct idpf_adapter *adapter = &adapter_ex->base;\n+\tstruct idpf_dma_mem *dma_mem = NULL;\n+\tstruct idpf_hw *hw = &adapter->hw;\n+\tstruct virtchnl2_event *vc_event;\n+\tstruct idpf_ctlq_msg ctlq_msg;\n+\tenum idpf_mbx_opc mbx_op;\n+\tstruct idpf_vport *vport;\n+\tenum virtchnl_ops vc_op;\n+\tuint16_t pending = 1;\n+\tint ret;\n+\n+\twhile (pending) {\n+\t\tret = idpf_vc_ctlq_recv(hw->arq, &pending, &ctlq_msg);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(INFO, \"Failed to read msg from virtual channel, ret: %d\", ret);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tmemcpy(adapter->mbx_resp, ctlq_msg.ctx.indirect.payload->va,\n+\t\t\t IDPF_DFLT_MBX_BUF_SIZE);\n+\n+\t\tmbx_op = rte_le_to_cpu_16(ctlq_msg.opcode);\n+\t\tvc_op = rte_le_to_cpu_32(ctlq_msg.cookie.mbx.chnl_opcode);\n+\t\tadapter->cmd_retval = rte_le_to_cpu_32(ctlq_msg.cookie.mbx.chnl_retval);\n+\n+\t\tswitch (mbx_op) {\n+\t\tcase idpf_mbq_opc_send_msg_to_peer_pf:\n+\t\t\tif (vc_op == VIRTCHNL2_OP_EVENT) {\n+\t\t\t\tif (ctlq_msg.data_len < sizeof(struct virtchnl2_event)) {\n+\t\t\t\t\tPMD_DRV_LOG(ERR, \"Error event\");\n+\t\t\t\t\treturn;\n+\t\t\t\t}\n+\t\t\t\tvc_event = (struct virtchnl2_event *)adapter->mbx_resp;\n+\t\t\t\tvport = cpfl_find_vport(adapter_ex, vc_event->vport_id);\n+\t\t\t\tif (!vport) {\n+\t\t\t\t\tPMD_DRV_LOG(ERR, \"Can't find vport.\");\n+\t\t\t\t\treturn;\n+\t\t\t\t}\n+\t\t\t\tcpfl_handle_event_msg(vport, adapter->mbx_resp,\n+\t\t\t\t\t\t ctlq_msg.data_len);\n+\t\t\t} else {\n+\t\t\t\tif (vc_op == adapter->pend_cmd)\n+\t\t\t\t\tnotify_cmd(adapter, adapter->cmd_retval);\n+\t\t\t\telse\n+\t\t\t\t\tPMD_DRV_LOG(ERR, \"command mismatch, expect %u, get %u\",\n+\t\t\t\t\t\t adapter->pend_cmd, vc_op);\n+\n+\t\t\t\tPMD_DRV_LOG(DEBUG, \" Virtual channel response is received,\"\n+\t\t\t\t\t \"opcode = %d\", vc_op);\n+\t\t\t}\n+\t\t\tgoto post_buf;\n+\t\tdefault:\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Request %u is not supported yet\", mbx_op);\n+\t\t}\n+\t}\n+\n+post_buf:\n+\tif (ctlq_msg.data_len)\n+\t\tdma_mem = ctlq_msg.ctx.indirect.payload;\n+\telse\n+\t\tpending = 0;\n+\n+\tret = idpf_vc_ctlq_post_rx_buffs(hw, hw->arq, &pending, &dma_mem);\n+\tif (ret && dma_mem)\n+\t\tidpf_free_dma_mem(hw, dma_mem);\n+}\n+\n+static void\n+cpfl_dev_alarm_handler(void *param)\n+{\n+\tstruct cpfl_adapter_ext *adapter = param;\n+\n+\tcpfl_handle_virtchnl_msg(adapter);\n+\n+\trte_eal_alarm_set(CPFL_ALARM_INTERVAL, cpfl_dev_alarm_handler, adapter);\n+}\n+\n+static int\n+cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)\n+{\n+\tstruct idpf_adapter *base = &adapter->base;\n+\tstruct idpf_hw *hw = &base->hw;\n+\tint ret = 0;\n+\n+\thw->hw_addr = (void *)pci_dev->mem_resource[0].addr;\n+\thw->hw_addr_len = pci_dev->mem_resource[0].len;\n+\thw->back = base;\n+\thw->vendor_id = pci_dev->id.vendor_id;\n+\thw->device_id = pci_dev->id.device_id;\n+\thw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;\n+\n+\tstrncpy(adapter->name, pci_dev->device.name, PCI_PRI_STR_SIZE);\n+\n+\tret = idpf_adapter_init(base);\n+\tif (ret != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init adapter\");\n+\t\tgoto err_adapter_init;\n+\t}\n+\n+\trte_eal_alarm_set(CPFL_ALARM_INTERVAL, cpfl_dev_alarm_handler, adapter);\n+\n+\tadapter->max_vport_nb = adapter->base.caps.max_vports;\n+\n+\tadapter->vports = rte_zmalloc(\"vports\",\n+\t\t\t\t adapter->max_vport_nb *\n+\t\t\t\t sizeof(*adapter->vports),\n+\t\t\t\t 0);\n+\tif (adapter->vports == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate vports memory\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_get_ptype;\n+\t}\n+\n+\tadapter->cur_vports = 0;\n+\tadapter->cur_vport_nb = 0;\n+\n+\tadapter->used_vecs_num = 0;\n+\n+\treturn ret;\n+\n+err_get_ptype:\n+\tidpf_adapter_deinit(base);\n+err_adapter_init:\n+\treturn ret;\n+}\n+\n+static const struct eth_dev_ops cpfl_eth_dev_ops = {\n+\t.dev_configure\t\t\t= cpfl_dev_configure,\n+\t.dev_close\t\t\t= cpfl_dev_close,\n+\t.dev_infos_get\t\t\t= cpfl_dev_info_get,\n+\t.link_update\t\t\t= cpfl_dev_link_update,\n+\t.dev_supported_ptypes_get\t= cpfl_dev_supported_ptypes_get,\n+};\n+\n+static uint16_t\n+cpfl_vport_idx_alloc(struct cpfl_adapter_ext *ad)\n+{\n+\tuint16_t vport_idx;\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < ad->max_vport_nb; i++) {\n+\t\tif (ad->vports[i] == NULL)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == ad->max_vport_nb)\n+\t\tvport_idx = CPFL_INVALID_VPORT_IDX;\n+\telse\n+\t\tvport_idx = i;\n+\n+\treturn vport_idx;\n+}\n+\n+static int\n+cpfl_dev_vport_init(struct rte_eth_dev *dev, void *init_params)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct cpfl_vport_param *param = init_params;\n+\tstruct cpfl_adapter_ext *adapter = param->adapter;\n+\t/* for sending create vport virtchnl msg prepare */\n+\tstruct virtchnl2_create_vport create_vport_info;\n+\tint ret = 0;\n+\n+\tdev->dev_ops = &cpfl_eth_dev_ops;\n+\tvport->adapter = &adapter->base;\n+\tvport->sw_idx = param->idx;\n+\tvport->devarg_id = param->devarg_id;\n+\tvport->dev = dev;\n+\n+\tmemset(&create_vport_info, 0, sizeof(create_vport_info));\n+\tret = idpf_vport_info_init(vport, &create_vport_info);\n+\tif (ret != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init vport req_info.\");\n+\t\tgoto err;\n+\t}\n+\n+\tret = idpf_vport_init(vport, &create_vport_info, dev->data);\n+\tif (ret != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init vports.\");\n+\t\tgoto err;\n+\t}\n+\n+\tadapter->vports[param->idx] = vport;\n+\tadapter->cur_vports |= RTE_BIT32(param->devarg_id);\n+\tadapter->cur_vport_nb++;\n+\n+\tdev->data->mac_addrs = rte_zmalloc(NULL, RTE_ETHER_ADDR_LEN, 0);\n+\tif (dev->data->mac_addrs == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Cannot allocate mac_addr memory.\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_mac_addrs;\n+\t}\n+\n+\trte_ether_addr_copy((struct rte_ether_addr *)vport->default_mac_addr,\n+\t\t\t &dev->data->mac_addrs[0]);\n+\n+\treturn 0;\n+\n+err_mac_addrs:\n+\tadapter->vports[param->idx] = NULL; /* reset */\n+\tidpf_vport_deinit(vport);\n+err:\n+\treturn ret;\n+}\n+\n+static const struct rte_pci_id pci_id_cpfl_map[] = {\n+\t{ RTE_PCI_DEVICE(IDPF_INTEL_VENDOR_ID, IDPF_DEV_ID_CPF) },\n+\t{ .vendor_id = 0, /* sentinel */ },\n+};\n+\n+static struct cpfl_adapter_ext *\n+cpfl_find_adapter_ext(struct rte_pci_device *pci_dev)\n+{\n+\tstruct cpfl_adapter_ext *adapter;\n+\tint found = 0;\n+\n+\tif (pci_dev == NULL)\n+\t\treturn NULL;\n+\n+\trte_spinlock_lock(&cpfl_adapter_lock);\n+\tTAILQ_FOREACH(adapter, &cpfl_adapter_list, next) {\n+\t\tif (strncmp(adapter->name, pci_dev->device.name, PCI_PRI_STR_SIZE) == 0) {\n+\t\t\tfound = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\trte_spinlock_unlock(&cpfl_adapter_lock);\n+\n+\tif (found == 0)\n+\t\treturn NULL;\n+\n+\treturn adapter;\n+}\n+\n+static void\n+cpfl_adapter_ext_deinit(struct cpfl_adapter_ext *adapter)\n+{\n+\trte_eal_alarm_cancel(cpfl_dev_alarm_handler, adapter);\n+\tidpf_adapter_deinit(&adapter->base);\n+\n+\trte_free(adapter->vports);\n+\tadapter->vports = NULL;\n+}\n+\n+static int\n+cpfl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t struct rte_pci_device *pci_dev)\n+{\n+\tstruct cpfl_vport_param vport_param;\n+\tstruct cpfl_adapter_ext *adapter;\n+\tstruct cpfl_devargs devargs;\n+\tchar name[RTE_ETH_NAME_MAX_LEN];\n+\tint i, retval;\n+\tbool first_probe = false;\n+\n+\tif (!cpfl_adapter_list_init) {\n+\t\trte_spinlock_init(&cpfl_adapter_lock);\n+\t\tTAILQ_INIT(&cpfl_adapter_list);\n+\t\tcpfl_adapter_list_init = true;\n+\t}\n+\n+\tadapter = cpfl_find_adapter_ext(pci_dev);\n+\tif (adapter == NULL) {\n+\t\tfirst_probe = true;\n+\t\tadapter = rte_zmalloc(\"cpfl_adapter_ext\",\n+\t\t\t\t sizeof(struct cpfl_adapter_ext), 0);\n+\t\tif (adapter == NULL) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate adapter.\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tretval = cpfl_adapter_ext_init(pci_dev, adapter);\n+\t\tif (retval != 0) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Failed to init adapter.\");\n+\t\t\treturn retval;\n+\t\t}\n+\n+\t\trte_spinlock_lock(&cpfl_adapter_lock);\n+\t\tTAILQ_INSERT_TAIL(&cpfl_adapter_list, adapter, next);\n+\t\trte_spinlock_unlock(&cpfl_adapter_lock);\n+\t}\n+\n+\tretval = cpfl_parse_devargs(pci_dev, adapter, &devargs);\n+\tif (retval != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to parse private devargs\");\n+\t\tgoto err;\n+\t}\n+\n+\tif (devargs.req_vport_nb == 0) {\n+\t\t/* If no vport devarg, create vport 0 by default. */\n+\t\tvport_param.adapter = adapter;\n+\t\tvport_param.devarg_id = 0;\n+\t\tvport_param.idx = cpfl_vport_idx_alloc(adapter);\n+\t\tif (vport_param.idx == CPFL_INVALID_VPORT_IDX) {\n+\t\t\tPMD_INIT_LOG(ERR, \"No space for vport %u\", vport_param.devarg_id);\n+\t\t\treturn 0;\n+\t\t}\n+\t\tsnprintf(name, sizeof(name), \"cpfl_%s_vport_0\",\n+\t\t\t pci_dev->device.name);\n+\t\tretval = rte_eth_dev_create(&pci_dev->device, name,\n+\t\t\t\t\t sizeof(struct idpf_vport),\n+\t\t\t\t\t NULL, NULL, cpfl_dev_vport_init,\n+\t\t\t\t\t &vport_param);\n+\t\tif (retval != 0)\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to create default vport 0\");\n+\t} else {\n+\t\tfor (i = 0; i < devargs.req_vport_nb; i++) {\n+\t\t\tvport_param.adapter = adapter;\n+\t\t\tvport_param.devarg_id = devargs.req_vports[i];\n+\t\t\tvport_param.idx = cpfl_vport_idx_alloc(adapter);\n+\t\t\tif (vport_param.idx == CPFL_INVALID_VPORT_IDX) {\n+\t\t\t\tPMD_INIT_LOG(ERR, \"No space for vport %u\", vport_param.devarg_id);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tsnprintf(name, sizeof(name), \"cpfl_%s_vport_%d\",\n+\t\t\t\t pci_dev->device.name,\n+\t\t\t\t devargs.req_vports[i]);\n+\t\t\tretval = rte_eth_dev_create(&pci_dev->device, name,\n+\t\t\t\t\t\t sizeof(struct idpf_vport),\n+\t\t\t\t\t\t NULL, NULL, cpfl_dev_vport_init,\n+\t\t\t\t\t\t &vport_param);\n+\t\t\tif (retval != 0)\n+\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to create vport %d\",\n+\t\t\t\t\t vport_param.devarg_id);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\tif (first_probe) {\n+\t\trte_spinlock_lock(&cpfl_adapter_lock);\n+\t\tTAILQ_REMOVE(&cpfl_adapter_list, adapter, next);\n+\t\trte_spinlock_unlock(&cpfl_adapter_lock);\n+\t\tcpfl_adapter_ext_deinit(adapter);\n+\t\trte_free(adapter);\n+\t}\n+\treturn retval;\n+}\n+\n+static int\n+cpfl_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct cpfl_adapter_ext *adapter = cpfl_find_adapter_ext(pci_dev);\n+\tuint16_t port_id;\n+\n+\t/* Ethdev created can be found RTE_ETH_FOREACH_DEV_OF through rte_device */\n+\tRTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {\n+\t\t\trte_eth_dev_close(port_id);\n+\t}\n+\n+\trte_spinlock_lock(&cpfl_adapter_lock);\n+\tTAILQ_REMOVE(&cpfl_adapter_list, adapter, next);\n+\trte_spinlock_unlock(&cpfl_adapter_lock);\n+\tcpfl_adapter_ext_deinit(adapter);\n+\trte_free(adapter);\n+\n+\treturn 0;\n+}\n+\n+static struct rte_pci_driver rte_cpfl_pmd = {\n+\t.id_table\t= pci_id_cpfl_map,\n+\t.drv_flags\t= RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe\t\t= cpfl_pci_probe,\n+\t.remove\t\t= cpfl_pci_remove,\n+};\n+\n+/**\n+ * Driver initialization routine.\n+ * Invoked once at EAL init time.\n+ * Register itself as the [Poll Mode] Driver of PCI devices.\n+ */\n+RTE_PMD_REGISTER_PCI(net_cpfl, rte_cpfl_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(net_cpfl, pci_id_cpfl_map);\n+RTE_PMD_REGISTER_KMOD_DEP(net_cpfl, \"* igb_uio | vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(net_cpfl,\n+\t\t\t CPFL_TX_SINGLE_Q \"=<0|1> \"\n+\t\t\t CPFL_RX_SINGLE_Q \"=<0|1> \"\n+\t\t\t CPFL_VPORT \"=[vport_set0,[vport_set1],...]\");\n+\n+RTE_LOG_REGISTER_SUFFIX(cpfl_logtype_init, init, NOTICE);\n+RTE_LOG_REGISTER_SUFFIX(cpfl_logtype_driver, driver, NOTICE);\ndiff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h\nnew file mode 100644\nindex 0000000000..9ca39b4558\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_ethdev.h\n@@ -0,0 +1,78 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_ETHDEV_H_\n+#define _CPFL_ETHDEV_H_\n+\n+#include <stdint.h>\n+#include <rte_malloc.h>\n+#include <rte_spinlock.h>\n+#include <rte_ethdev.h>\n+#include <rte_kvargs.h>\n+#include <ethdev_driver.h>\n+#include <ethdev_pci.h>\n+\n+#include \"cpfl_logs.h\"\n+\n+#include <idpf_common_device.h>\n+#include <idpf_common_virtchnl.h>\n+#include <base/idpf_prototype.h>\n+#include <base/virtchnl2.h>\n+\n+#define CPFL_MAX_VPORT_NUM\t8\n+\n+#define CPFL_INVALID_VPORT_IDX\t0xffff\n+\n+#define CPFL_MIN_BUF_SIZE\t1024\n+#define CPFL_MAX_FRAME_SIZE\t9728\n+#define CPFL_DEFAULT_MTU\tRTE_ETHER_MTU\n+\n+#define CPFL_NUM_MACADDR_MAX\t64\n+\n+#define CPFL_VLAN_TAG_SIZE\t4\n+#define CPFL_ETH_OVERHEAD \\\n+\t(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + CPFL_VLAN_TAG_SIZE * 2)\n+\n+#define CPFL_ADAPTER_NAME_LEN\t(PCI_PRI_STR_SIZE + 1)\n+\n+#define CPFL_ALARM_INTERVAL\t50000 /* us */\n+\n+/* Device IDs */\n+#define IDPF_DEV_ID_CPF\t\t\t0x1453\n+\n+struct cpfl_vport_param {\n+\tstruct cpfl_adapter_ext *adapter;\n+\tuint16_t devarg_id; /* arg id from user */\n+\tuint16_t idx; /* index in adapter->vports[]*/\n+};\n+\n+/* Struct used when parse driver specific devargs */\n+struct cpfl_devargs {\n+\tuint16_t req_vports[CPFL_MAX_VPORT_NUM];\n+\tuint16_t req_vport_nb;\n+};\n+\n+struct cpfl_adapter_ext {\n+\tTAILQ_ENTRY(cpfl_adapter_ext) next;\n+\tstruct idpf_adapter base;\n+\n+\tchar name[CPFL_ADAPTER_NAME_LEN];\n+\n+\tstruct idpf_vport **vports;\n+\tuint16_t max_vport_nb;\n+\n+\tuint16_t cur_vports; /* bit mask of created vport */\n+\tuint16_t cur_vport_nb;\n+\n+\tuint16_t used_vecs_num;\n+};\n+\n+TAILQ_HEAD(cpfl_adapter_list, cpfl_adapter_ext);\n+\n+#define CPFL_DEV_TO_PCI(eth_dev)\t\t\\\n+\tRTE_DEV_TO_PCI((eth_dev)->device)\n+#define CPFL_ADAPTER_TO_EXT(p)\t\t\t\t\t\\\n+\tcontainer_of((p), struct cpfl_adapter_ext, base)\n+\n+#endif /* _CPFL_ETHDEV_H_ */\ndiff --git a/drivers/net/cpfl/cpfl_logs.h b/drivers/net/cpfl/cpfl_logs.h\nnew file mode 100644\nindex 0000000000..365b53e8b3\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_logs.h\n@@ -0,0 +1,32 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_LOGS_H_\n+#define _CPFL_LOGS_H_\n+\n+#include <rte_log.h>\n+\n+extern int cpfl_logtype_init;\n+extern int cpfl_logtype_driver;\n+\n+#define PMD_INIT_LOG(level, ...) \\\n+\trte_log(RTE_LOG_ ## level, \\\n+\t\tcpfl_logtype_init, \\\n+\t\tRTE_FMT(\"%s(): \" \\\n+\t\t\tRTE_FMT_HEAD(__VA_ARGS__,) \"\\n\", \\\n+\t\t\t__func__, \\\n+\t\t\tRTE_FMT_TAIL(__VA_ARGS__,)))\n+\n+#define PMD_DRV_LOG_RAW(level, ...) \\\n+\trte_log(RTE_LOG_ ## level, \\\n+\t\tcpfl_logtype_driver, \\\n+\t\tRTE_FMT(\"%s(): \" \\\n+\t\t\tRTE_FMT_HEAD(__VA_ARGS__,) \"\\n\", \\\n+\t\t\t__func__, \\\n+\t\t\tRTE_FMT_TAIL(__VA_ARGS__,)))\n+\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n+\n+#endif /* _CPFL_LOGS_H_ */\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nnew file mode 100644\nindex 0000000000..2b9c20928b\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -0,0 +1,244 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#include <ethdev_driver.h>\n+#include <rte_net.h>\n+#include <rte_vect.h>\n+\n+#include \"cpfl_ethdev.h\"\n+#include \"cpfl_rxtx.h\"\n+\n+static uint64_t\n+cpfl_tx_offload_convert(uint64_t offload)\n+{\n+\tuint64_t ol = 0;\n+\n+\tif ((offload & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) != 0)\n+\t\tol |= IDPF_TX_OFFLOAD_IPV4_CKSUM;\n+\tif ((offload & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) != 0)\n+\t\tol |= IDPF_TX_OFFLOAD_UDP_CKSUM;\n+\tif ((offload & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) != 0)\n+\t\tol |= IDPF_TX_OFFLOAD_TCP_CKSUM;\n+\tif ((offload & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM) != 0)\n+\t\tol |= IDPF_TX_OFFLOAD_SCTP_CKSUM;\n+\tif ((offload & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) != 0)\n+\t\tol |= IDPF_TX_OFFLOAD_MULTI_SEGS;\n+\tif ((offload & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) != 0)\n+\t\tol |= IDPF_TX_OFFLOAD_MBUF_FAST_FREE;\n+\n+\treturn ol;\n+}\n+\n+static const struct rte_memzone *\n+cpfl_dma_zone_reserve(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t uint16_t len, uint16_t queue_type,\n+\t\t unsigned int socket_id, bool splitq)\n+{\n+\tchar ring_name[RTE_MEMZONE_NAMESIZE];\n+\tconst struct rte_memzone *mz;\n+\tuint32_t ring_size;\n+\n+\tmemset(ring_name, 0, RTE_MEMZONE_NAMESIZE);\n+\tswitch (queue_type) {\n+\tcase VIRTCHNL2_QUEUE_TYPE_TX:\n+\t\tif (splitq)\n+\t\t\tring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_sched_desc),\n+\t\t\t\t\t CPFL_DMA_MEM_ALIGN);\n+\t\telse\n+\t\t\tring_size = RTE_ALIGN(len * sizeof(struct idpf_flex_tx_desc),\n+\t\t\t\t\t CPFL_DMA_MEM_ALIGN);\n+\t\tmemcpy(ring_name, \"cpfl Tx ring\", sizeof(\"cpfl Tx ring\"));\n+\t\tbreak;\n+\tcase VIRTCHNL2_QUEUE_TYPE_RX:\n+\t\tif (splitq)\n+\t\t\tring_size = RTE_ALIGN(len * sizeof(struct virtchnl2_rx_flex_desc_adv_nic_3),\n+\t\t\t\t\t CPFL_DMA_MEM_ALIGN);\n+\t\telse\n+\t\t\tring_size = RTE_ALIGN(len * sizeof(struct virtchnl2_singleq_rx_buf_desc),\n+\t\t\t\t\t CPFL_DMA_MEM_ALIGN);\n+\t\tmemcpy(ring_name, \"cpfl Rx ring\", sizeof(\"cpfl Rx ring\"));\n+\t\tbreak;\n+\tcase VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION:\n+\t\tring_size = RTE_ALIGN(len * sizeof(struct idpf_splitq_tx_compl_desc),\n+\t\t\t\t CPFL_DMA_MEM_ALIGN);\n+\t\tmemcpy(ring_name, \"cpfl Tx compl ring\", sizeof(\"cpfl Tx compl ring\"));\n+\t\tbreak;\n+\tcase VIRTCHNL2_QUEUE_TYPE_RX_BUFFER:\n+\t\tring_size = RTE_ALIGN(len * sizeof(struct virtchnl2_splitq_rx_buf_desc),\n+\t\t\t\t CPFL_DMA_MEM_ALIGN);\n+\t\tmemcpy(ring_name, \"cpfl Rx buf ring\", sizeof(\"cpfl Rx buf ring\"));\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_INIT_LOG(ERR, \"Invalid queue type\");\n+\t\treturn NULL;\n+\t}\n+\n+\tmz = rte_eth_dma_zone_reserve(dev, ring_name, queue_idx,\n+\t\t\t\t ring_size, CPFL_RING_BASE_ALIGN,\n+\t\t\t\t socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to reserve DMA memory for ring\");\n+\t\treturn NULL;\n+\t}\n+\n+\t/* Zero all the descriptors in the ring. */\n+\tmemset(mz->addr, 0, ring_size);\n+\n+\treturn mz;\n+}\n+\n+static void\n+cpfl_dma_zone_release(const struct rte_memzone *mz)\n+{\n+\trte_memzone_free(mz);\n+}\n+\n+static int\n+cpfl_tx_complq_setup(struct rte_eth_dev *dev, struct idpf_tx_queue *txq,\n+\t\t uint16_t queue_idx, uint16_t nb_desc,\n+\t\t unsigned int socket_id)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tconst struct rte_memzone *mz;\n+\tstruct idpf_tx_queue *cq;\n+\tint ret;\n+\n+\tcq = rte_zmalloc_socket(\"cpfl splitq cq\",\n+\t\t\t\tsizeof(struct idpf_tx_queue),\n+\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (cq == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for Tx compl queue\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_cq_alloc;\n+\t}\n+\n+\tcq->nb_tx_desc = nb_desc;\n+\tcq->queue_id = vport->chunks_info.tx_compl_start_qid + queue_idx;\n+\tcq->port_id = dev->data->port_id;\n+\tcq->txqs = dev->data->tx_queues;\n+\tcq->tx_start_qid = vport->chunks_info.tx_start_qid;\n+\n+\tmz = cpfl_dma_zone_reserve(dev, queue_idx, nb_desc,\n+\t\t\t\t VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION,\n+\t\t\t\t socket_id, true);\n+\tif (mz == NULL) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err_mz_reserve;\n+\t}\n+\tcq->tx_ring_phys_addr = mz->iova;\n+\tcq->compl_ring = mz->addr;\n+\tcq->mz = mz;\n+\treset_split_tx_complq(cq);\n+\n+\ttxq->complq = cq;\n+\n+\treturn 0;\n+\n+err_mz_reserve:\n+\trte_free(cq);\n+err_cq_alloc:\n+\treturn ret;\n+}\n+\n+int\n+cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t uint16_t nb_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct idpf_vport *vport = dev->data->dev_private;\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tuint16_t tx_rs_thresh, tx_free_thresh;\n+\tstruct idpf_hw *hw = &adapter->hw;\n+\tconst struct rte_memzone *mz;\n+\tstruct idpf_tx_queue *txq;\n+\tuint64_t offloads;\n+\tuint16_t len;\n+\tbool is_splitq;\n+\tint ret;\n+\n+\toffloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;\n+\n+\ttx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh > 0) ?\n+\t\ttx_conf->tx_rs_thresh : CPFL_DEFAULT_TX_RS_THRESH);\n+\ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh > 0) ?\n+\t\ttx_conf->tx_free_thresh : CPFL_DEFAULT_TX_FREE_THRESH);\n+\tif (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)\n+\t\treturn -EINVAL;\n+\n+\t/* Allocate the TX queue data structure. */\n+\ttxq = rte_zmalloc_socket(\"cpfl txq\",\n+\t\t\t\t sizeof(struct idpf_tx_queue),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t socket_id);\n+\tif (txq == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for tx queue structure\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_txq_alloc;\n+\t}\n+\n+\tis_splitq = !!(vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT);\n+\n+\ttxq->nb_tx_desc = nb_desc;\n+\ttxq->rs_thresh = tx_rs_thresh;\n+\ttxq->free_thresh = tx_free_thresh;\n+\ttxq->queue_id = vport->chunks_info.tx_start_qid + queue_idx;\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->offloads = cpfl_tx_offload_convert(offloads);\n+\ttxq->tx_deferred_start = tx_conf->tx_deferred_start;\n+\n+\tif (is_splitq)\n+\t\tlen = 2 * nb_desc;\n+\telse\n+\t\tlen = nb_desc;\n+\ttxq->sw_nb_desc = len;\n+\n+\t/* Allocate TX hardware ring descriptors. */\n+\tmz = cpfl_dma_zone_reserve(dev, queue_idx, nb_desc, VIRTCHNL2_QUEUE_TYPE_TX,\n+\t\t\t\t socket_id, is_splitq);\n+\tif (mz == NULL) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err_mz_reserve;\n+\t}\n+\ttxq->tx_ring_phys_addr = mz->iova;\n+\ttxq->mz = mz;\n+\n+\ttxq->sw_ring = rte_zmalloc_socket(\"cpfl tx sw ring\",\n+\t\t\t\t\t sizeof(struct idpf_tx_entry) * len,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq->sw_ring == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory for SW TX ring\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_sw_ring_alloc;\n+\t}\n+\n+\tif (!is_splitq) {\n+\t\ttxq->tx_ring = mz->addr;\n+\t\treset_single_tx_queue(txq);\n+\t} else {\n+\t\ttxq->desc_ring = mz->addr;\n+\t\treset_split_tx_descq(txq);\n+\n+\t\t/* Setup tx completion queue if split model */\n+\t\tret = cpfl_tx_complq_setup(dev, txq, queue_idx,\n+\t\t\t\t\t 2 * nb_desc, socket_id);\n+\t\tif (ret != 0)\n+\t\t\tgoto err_complq_setup;\n+\t}\n+\n+\ttxq->qtx_tail = hw->hw_addr + (vport->chunks_info.tx_qtail_start +\n+\t\t\tqueue_idx * vport->chunks_info.tx_qtail_spacing);\n+\ttxq->q_set = true;\n+\tdev->data->tx_queues[queue_idx] = txq;\n+\n+\treturn 0;\n+\n+err_complq_setup:\n+err_sw_ring_alloc:\n+\tcpfl_dma_zone_release(mz);\n+err_mz_reserve:\n+\trte_free(txq);\n+err_txq_alloc:\n+\treturn ret;\n+}\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h\nnew file mode 100644\nindex 0000000000..232630c5e9\n--- /dev/null\n+++ b/drivers/net/cpfl/cpfl_rxtx.h\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef _CPFL_RXTX_H_\n+#define _CPFL_RXTX_H_\n+\n+#include <idpf_common_rxtx.h>\n+#include \"cpfl_ethdev.h\"\n+\n+/* In QLEN must be whole number of 32 descriptors. */\n+#define CPFL_ALIGN_RING_DESC\t32\n+#define CPFL_MIN_RING_DESC\t32\n+#define CPFL_MAX_RING_DESC\t4096\n+#define CPFL_DMA_MEM_ALIGN\t4096\n+/* Base address of the HW descriptor ring should be 128B aligned. */\n+#define CPFL_RING_BASE_ALIGN\t128\n+\n+#define CPFL_DEFAULT_TX_RS_THRESH\t32\n+#define CPFL_DEFAULT_TX_FREE_THRESH\t32\n+\n+int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\tuint16_t nb_desc, unsigned int socket_id,\n+\t\t\tconst struct rte_eth_txconf *tx_conf);\n+#endif /* _CPFL_RXTX_H_ */\ndiff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build\nnew file mode 100644\nindex 0000000000..c721732b50\n--- /dev/null\n+++ b/drivers/net/cpfl/meson.build\n@@ -0,0 +1,14 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2023 Intel Corporation\n+\n+if is_windows\n+ build = false\n+ reason = 'not supported on Windows'\n+ subdir_done()\n+endif\n+\n+deps += ['common_idpf']\n+\n+sources = files(\n+ 'cpfl_ethdev.c',\n+)\n\\ No newline at end of file\ndiff --git a/drivers/net/meson.build b/drivers/net/meson.build\nindex 6470bf3636..a8ca338875 100644\n--- a/drivers/net/meson.build\n+++ b/drivers/net/meson.build\n@@ -13,6 +13,7 @@ drivers = [\n 'bnxt',\n 'bonding',\n 'cnxk',\n+ 'cpfl',\n 'cxgbe',\n 'dpaa',\n 'dpaa2',\n", "prefixes": [ "v6", "01/21" ] }