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GET /api/patches/123710/?format=api
{ "id": 123710, "url": "https://patches.dpdk.org/api/patches/123710/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230210195110.683162-1-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230210195110.683162-1-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230210195110.683162-1-cristian.dumitrescu@intel.com", "date": "2023-02-10T19:51:10", "name": "pipeline: support conversion between big and small fields", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a83858e85c6e8f49e812fca960d432ad86d0ba6f", "submitter": { "id": 19, "url": "https://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230210195110.683162-1-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 26958, "url": "https://patches.dpdk.org/api/series/26958/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26958", "date": "2023-02-10T19:51:10", "name": "pipeline: support conversion between big and small fields", "version": 1, "mbox": "https://patches.dpdk.org/series/26958/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/123710/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/123710/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3322241C61;\n\tFri, 10 Feb 2023 20:51:25 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C67F0410D3;\n\tFri, 10 Feb 2023 20:51:24 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 6FC7B40687\n for <dev@dpdk.org>; Fri, 10 Feb 2023 20:51:22 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Feb 2023 11:51:12 -0800", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.222.53])\n by fmsmga006.fm.intel.com with ESMTP; 10 Feb 2023 11:51:10 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1676058682; x=1707594682;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=pKhYu8hPzz5XaG/0eA4oJDBIzLG7CLOR3Q2DLNRMJEI=;\n b=ExsIpSZBdGVwo6NycArs9aF8ETpQRIGYkI4KGNdto5qW5XqoPRA2nS88\n CsVWCpO6vosoGylZmSyJX0ca82uEQzgVOsylZjHgixj2AiRl/dFvDJCRq\n mgvpk1UsnEEDha1ycvl+9tF6dbsnxTHa7n63NqJqhjPwYCytvC+XQJf5p\n 71E6zaEEzdA5E6GTxfHvh+QBbx5vRcF6v+prVzyNkcAKk+0gEClFSM56E\n P8HsDL0ymbPzjDUJcjqC0ExtOti+R4YQYHhnlaCuQaT62VFM/wb1PttVq\n RNyPRbw4ThaZnOUoVdn2xoPJ6VmUXa/gqf8N3WQXTGe8jtJRHFCLyrakG w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10617\"; a=\"318530930\"", "E=Sophos;i=\"5.97,287,1669104000\"; d=\"scan'208\";a=\"318530930\"", "E=McAfee;i=\"6500,9779,10617\"; a=\"913657682\"", "E=Sophos;i=\"5.97,287,1669104000\"; d=\"scan'208\";a=\"913657682\"" ], "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Cc": "Kamalakannan R <kamalakannan.r@intel.com>", "Subject": "[PATCH] pipeline: support conversion between big and small fields", "Date": "Fri, 10 Feb 2023 19:51:10 +0000", "Message-Id": "<20230210195110.683162-1-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "While the small fields (size <= 64 bits) can be in either network byte\norder (header fields) or host byte order (meta-data fields), the big\nfields (size > 64 bits) are always expected to be in network byte\norder (big endian), both header and metadata fields.\n\nPreviously, a big field could be involved in an assignment only when\nboth the destination and the source are big fields of exactly the same\nsize. This restriction is now relaxed significantly: in case a big\nfield is involved as either destination or source, the other field can\nnow be either a big field (of the same or different size) or a small\nheader field, so in either case both destination and source are in the\nnetwork byte order.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\nSigned-off-by: Kamalakannan R <kamalakannan.r@intel.com>\n---\nDepends-on: patch-26863 (\"[V4] pipeline: add RSS support\")\n\n lib/pipeline/rte_swx_pipeline.c | 33 +++++++++-\n lib/pipeline/rte_swx_pipeline_internal.h | 77 ++++++++++++------------\n 2 files changed, 71 insertions(+), 39 deletions(-)", "diff": "diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c\nindex 53d97f0072..dea1378095 100644\n--- a/lib/pipeline/rte_swx_pipeline.c\n+++ b/lib/pipeline/rte_swx_pipeline.c\n@@ -3218,11 +3218,24 @@ instr_mov_translate(struct rte_swx_pipeline *p,\n \t\t\tif (dst[0] == 'h' && src[0] == 'h')\n \t\t\t\tinstr->type = INSTR_MOV_HH;\n \t\t} else {\n-\t\t\tCHECK(fdst->n_bits == fsrc->n_bits, EINVAL);\n+\t\t\t/* The big fields (field with size > 64 bits) are always expected in NBO,\n+\t\t\t * regardless of their type (H or MEFT). In case a big field is involved as\n+\t\t\t * either dst or src, the other field must also be NBO.\n+\t\t\t *\n+\t\t\t * In case the dst field is big, the src field must be either a big field\n+\t\t\t * (of the same or different size as dst) or a small H field. Similarly,\n+\t\t\t * in case the src field is big, the dst field must be either a big field\n+\t\t\t * (of the same or different size as src) or a small H field. Any other case\n+\t\t\t * involving a big field as either dst or src is rejected.\n+\t\t\t */\n+\t\t\tCHECK(fdst->n_bits > 64 || dst[0] == 'h', EINVAL);\n+\t\t\tCHECK(fsrc->n_bits > 64 || src[0] == 'h', EINVAL);\n \n \t\t\tinstr->type = INSTR_MOV_DMA;\n-\t\t\tif (fdst->n_bits == 128)\n+\t\t\tif (fdst->n_bits == 128 && fsrc->n_bits == 128)\n \t\t\t\tinstr->type = INSTR_MOV_128;\n+\t\t\tif (fdst->n_bits == 128 && fsrc->n_bits == 32)\n+\t\t\t\tinstr->type = INSTR_MOV_128_32;\n \t\t}\n \n \t\tinstr->mov.dst.struct_id = (uint8_t)dst_struct_id;\n@@ -3322,6 +3335,18 @@ instr_mov_128_exec(struct rte_swx_pipeline *p)\n \tthread_ip_inc(p);\n }\n \n+static inline void\n+instr_mov_128_32_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\t__instr_mov_128_32_exec(p, t, ip);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n static inline void\n instr_mov_i_exec(struct rte_swx_pipeline *p)\n {\n@@ -7435,6 +7460,7 @@ static instr_exec_t instruction_table[] = {\n \t[INSTR_MOV_HH] = instr_mov_hh_exec,\n \t[INSTR_MOV_DMA] = instr_mov_dma_exec,\n \t[INSTR_MOV_128] = instr_mov_128_exec,\n+\t[INSTR_MOV_128_32] = instr_mov_128_32_exec,\n \t[INSTR_MOV_I] = instr_mov_i_exec,\n \n \t[INSTR_DMA_HT] = instr_dma_ht_exec,\n@@ -11757,6 +11783,7 @@ instr_type_to_name(struct instruction *instr)\n \tcase INSTR_MOV_HH: return \"INSTR_MOV_HH\";\n \tcase INSTR_MOV_DMA: return \"INSTR_MOV_DMA\";\n \tcase INSTR_MOV_128: return \"INSTR_MOV_128\";\n+\tcase INSTR_MOV_128_32: return \"INSTR_MOV_128_32\";\n \tcase INSTR_MOV_I: return \"INSTR_MOV_I\";\n \n \tcase INSTR_DMA_HT: return \"INSTR_DMA_HT\";\n@@ -12797,6 +12824,7 @@ static instruction_export_t export_table[] = {\n \t[INSTR_MOV_HH] = instr_mov_export,\n \t[INSTR_MOV_DMA] = instr_mov_export,\n \t[INSTR_MOV_128] = instr_mov_export,\n+\t[INSTR_MOV_128_32] = instr_mov_export,\n \t[INSTR_MOV_I] = instr_mov_export,\n \n \t[INSTR_DMA_HT] = instr_dma_ht_export,\n@@ -13025,6 +13053,7 @@ instr_type_to_func(struct instruction *instr)\n \tcase INSTR_MOV_HH: return \"__instr_mov_hh_exec\";\n \tcase INSTR_MOV_DMA: return \"__instr_mov_dma_exec\";\n \tcase INSTR_MOV_128: return \"__instr_mov_128_exec\";\n+\tcase INSTR_MOV_128_32: return \"__instr_mov_128_32_exec\";\n \tcase INSTR_MOV_I: return \"__instr_mov_i_exec\";\n \n \tcase INSTR_DMA_HT: return \"__instr_dma_ht_exec\";\ndiff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h\nindex ac22d94a93..2f24e1a1c5 100644\n--- a/lib/pipeline/rte_swx_pipeline_internal.h\n+++ b/lib/pipeline/rte_swx_pipeline_internal.h\n@@ -327,8 +327,9 @@ enum instruction_type {\n \tINSTR_MOV_MH, /* dst = MEF, src = H; size(dst) <= 64 bits, size(src) <= 64 bits. */\n \tINSTR_MOV_HM, /* dst = H, src = MEFT; size(dst) <= 64 bits, size(src) <= 64 bits. */\n \tINSTR_MOV_HH, /* dst = H, src = H; size(dst) <= 64 bits, size(src) <= 64 bits. */\n-\tINSTR_MOV_DMA, /* dst = HMEF, src = HMEF; size(dst) = size(src) > 64 bits, NBO format. */\n-\tINSTR_MOV_128, /* dst = HMEF, src = HMEF; size(dst) = size(src) = 128 bits, NBO format. */\n+\tINSTR_MOV_DMA, /* dst and src in NBO format. */\n+\tINSTR_MOV_128, /* dst and src in NBO format, size(dst) = size(src) = 128 bits. */\n+\tINSTR_MOV_128_32, /* dst and src in NBO format, size(dst) = 128 bits, size(src) = 32 b. */\n \tINSTR_MOV_I, /* dst = HMEF, src = I; size(dst) <= 64 bits. */\n \n \t/* dma h.header t.field\n@@ -2611,48 +2612,31 @@ __instr_mov_dma_exec(struct rte_swx_pipeline *p __rte_unused,\n \t\t struct thread *t,\n \t\t const struct instruction *ip)\n {\n-\tuint8_t *dst_struct = t->structs[ip->mov.dst.struct_id];\n-\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[ip->mov.dst.offset];\n-\tuint32_t *dst32_ptr;\n-\tuint16_t *dst16_ptr;\n-\tuint8_t *dst8_ptr;\n+\tuint8_t *dst = t->structs[ip->mov.dst.struct_id] + ip->mov.dst.offset;\n+\tuint8_t *src = t->structs[ip->mov.src.struct_id] + ip->mov.src.offset;\n \n-\tuint8_t *src_struct = t->structs[ip->mov.src.struct_id];\n-\tuint64_t *src64_ptr = (uint64_t *)&src_struct[ip->mov.src.offset];\n-\tuint32_t *src32_ptr;\n-\tuint16_t *src16_ptr;\n-\tuint8_t *src8_ptr;\n-\n-\tuint32_t n = ip->mov.dst.n_bits >> 3, i;\n+\tuint32_t n_dst = ip->mov.dst.n_bits >> 3;\n+\tuint32_t n_src = ip->mov.src.n_bits >> 3;\n \n \tTRACE(\"[Thread %2u] mov (dma) %u bytes\\n\", p->thread_id, n);\n \n-\t/* 8-byte transfers. */\n-\tfor (i = 0; i < n >> 3; i++)\n-\t\t*dst64_ptr++ = *src64_ptr++;\n-\n-\t/* 4-byte transfers. */\n-\tn &= 7;\n-\tdst32_ptr = (uint32_t *)dst64_ptr;\n-\tsrc32_ptr = (uint32_t *)src64_ptr;\n+\t/* Both dst and src are in NBO format. */\n+\tif (n_dst > n_src) {\n+\t\tuint32_t n_dst_zero = n_dst - n_src;\n \n-\tfor (i = 0; i < n >> 2; i++)\n-\t\t*dst32_ptr++ = *src32_ptr++;\n+\t\t/* Zero padding the most significant bytes in dst. */\n+\t\tmemset(dst, 0, n_dst_zero);\n+\t\tdst += n_dst_zero;\n \n-\t/* 2-byte transfers. */\n-\tn &= 3;\n-\tdst16_ptr = (uint16_t *)dst32_ptr;\n-\tsrc16_ptr = (uint16_t *)src32_ptr;\n+\t\t/* Copy src to dst. */\n+\t\tmemcpy(dst, src, n_src);\n+\t} else {\n+\t\tuint32_t n_src_skipped = n_src - n_dst;\n \n-\tfor (i = 0; i < n >> 1; i++)\n-\t\t*dst16_ptr++ = *src16_ptr++;\n-\n-\t/* 1-byte transfer. */\n-\tn &= 1;\n-\tdst8_ptr = (uint8_t *)dst16_ptr;\n-\tsrc8_ptr = (uint8_t *)src16_ptr;\n-\tif (n)\n-\t\t*dst8_ptr = *src8_ptr;\n+\t\t/* Copy src to dst. */\n+\t\tsrc += n_src_skipped;\n+\t\tmemcpy(dst, src, n_dst);\n+\t}\n }\n \n static inline void\n@@ -2672,6 +2656,25 @@ __instr_mov_128_exec(struct rte_swx_pipeline *p __rte_unused,\n \tdst64_ptr[1] = src64_ptr[1];\n }\n \n+static inline void\n+__instr_mov_128_32_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t\tstruct thread *t,\n+\t\t\tconst struct instruction *ip)\n+{\n+\tuint8_t *dst = t->structs[ip->mov.dst.struct_id] + ip->mov.dst.offset;\n+\tuint8_t *src = t->structs[ip->mov.src.struct_id] + ip->mov.src.offset;\n+\n+\tuint32_t *dst32 = (uint32_t *)dst;\n+\tuint32_t *src32 = (uint32_t *)src;\n+\n+\tTRACE(\"[Thread %2u] mov (128 <- 32)\\n\", p->thread_id);\n+\n+\tdst32[0] = 0;\n+\tdst32[1] = 0;\n+\tdst32[2] = 0;\n+\tdst32[3] = src32[0];\n+}\n+\n static inline void\n __instr_mov_i_exec(struct rte_swx_pipeline *p __rte_unused,\n \t\t struct thread *t,\n", "prefixes": [] }