Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/123338/?format=api
{ "id": 123338, "url": "https://patches.dpdk.org/api/patches/123338/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230207160719.1307-21-syalavarthi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230207160719.1307-21-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230207160719.1307-21-syalavarthi@marvell.com", "date": "2023-02-07T16:07:00", "name": "[v5,20/39] ml/cnxk: enable support to get model information", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "159c74828380287a39ba76269b3e0119034a244d", "submitter": { "id": 2480, "url": "https://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230207160719.1307-21-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26860, "url": "https://patches.dpdk.org/api/series/26860/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26860", "date": "2023-02-07T16:06:40", "name": "Implementation of ML CNXK driver", "version": 5, "mbox": "https://patches.dpdk.org/series/26860/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/123338/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/123338/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8B73B41C30;\n\tTue, 7 Feb 2023 17:10:15 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 08BD942F9C;\n\tTue, 7 Feb 2023 17:07:52 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 73E6342B8E\n for <dev@dpdk.org>; Tue, 7 Feb 2023 17:07:32 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 317BL2vl005847 for <dev@dpdk.org>; Tue, 7 Feb 2023 08:07:31 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nhqrtmsnd-9\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 07 Feb 2023 08:07:31 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42;\n Tue, 7 Feb 2023 08:07:27 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend\n Transport; Tue, 7 Feb 2023 08:07:27 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 988E73F7043;\n Tue, 7 Feb 2023 08:07:27 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=jfFFtagwoLhGzlImTyPjiK2mcsfv/BsxhY/LDUD7hqI=;\n b=c9McDda8FJdVG107C6aeio7ggmKj5vLS6PgFQFciwabyIvmK7XB8R5e9pC+PDm8mZI1A\n u5Ts6YYE9lM+rExZSL1ABVZwq27L75RW3EOZqV2L2S5c2PpEmpvV3T9nmZ3ghDsiKS8v\n D4Z7m1eo7VqqiA/0Y3LYLBK0nruR06ohz431Ix25hc6uZHbrIdJthOeCd6rSz4CVJO75\n qX63DwApN6vXgJWvmi/Q5s5iA/DJoN7mW6EFTLBZ+iKMdeafpM0qLuahcKNqskhJrsq2\n BCiWjOCaLbu8FMsop5qQ9lkVoNHKUhJoFJwI0GphSNTErrgSFZL6QdVbjR953INYF3Mc vQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>, <ptakkar@marvell.com>, <pshukla@marvell.com>", "Subject": "[PATCH v5 20/39] ml/cnxk: enable support to get model information", "Date": "Tue, 7 Feb 2023 08:07:00 -0800", "Message-ID": "<20230207160719.1307-21-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230207160719.1307-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20230207160719.1307-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "SNsdhUb3zhTq2ZxQ9IaVmdyn0wv3t7Vs", "X-Proofpoint-ORIG-GUID": "SNsdhUb3zhTq2ZxQ9IaVmdyn0wv3t7Vs", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1\n definitions=2023-02-07_07,2023-02-06_03,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added driver functions to get model information. Added\ninternal functions to set and get model info.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_model.c | 55 ++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_model.h | 9 ++++++\n drivers/ml/cnxk/cn10k_ml_ops.c | 37 ++++++++++++++++++---\n 3 files changed, 97 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_model.c b/drivers/ml/cnxk/cn10k_ml_model.c\nindex 69d6306104..0ded355d81 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.c\n+++ b/drivers/ml/cnxk/cn10k_ml_model.c\n@@ -356,3 +356,58 @@ cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, uint16_t model_id, ui\n \n \treturn 0;\n }\n+\n+void\n+cn10k_ml_model_info_set(struct rte_ml_dev *dev, struct cn10k_ml_model *model)\n+{\n+\tstruct rte_ml_model_info *info;\n+\tstruct rte_ml_io_info *output;\n+\tstruct rte_ml_io_info *input;\n+\tuint8_t i;\n+\n+\tinfo = PLT_PTR_CAST(model->info);\n+\tinput = PLT_PTR_ADD(info, sizeof(struct rte_ml_model_info));\n+\toutput =\n+\t\tPLT_PTR_ADD(input, model->metadata.model.num_input * sizeof(struct rte_ml_io_info));\n+\n+\t/* Set model info */\n+\tmemset(info, 0, sizeof(struct rte_ml_model_info));\n+\trte_memcpy(info->name, model->metadata.model.name, MRVL_ML_MODEL_NAME_LEN);\n+\tsnprintf(info->version, RTE_ML_STR_MAX, \"%u.%u.%u.%u\", model->metadata.model.version[0],\n+\t\t model->metadata.model.version[1], model->metadata.model.version[2],\n+\t\t model->metadata.model.version[3]);\n+\tinfo->model_id = model->model_id;\n+\tinfo->device_id = dev->data->dev_id;\n+\tinfo->batch_size = model->batch_size;\n+\tinfo->nb_inputs = model->metadata.model.num_input;\n+\tinfo->input_info = input;\n+\tinfo->nb_outputs = model->metadata.model.num_output;\n+\tinfo->output_info = output;\n+\tinfo->wb_size = model->metadata.weights_bias.file_size;\n+\n+\t/* Set input info */\n+\tfor (i = 0; i < info->nb_inputs; i++) {\n+\t\trte_memcpy(input[i].name, model->metadata.input[i].input_name,\n+\t\t\t MRVL_ML_INPUT_NAME_LEN);\n+\t\tinput[i].dtype = model->metadata.input[i].input_type;\n+\t\tinput[i].qtype = model->metadata.input[i].model_input_type;\n+\t\tinput[i].shape.format = model->metadata.input[i].shape.format;\n+\t\tinput[i].shape.w = model->metadata.input[i].shape.w;\n+\t\tinput[i].shape.x = model->metadata.input[i].shape.x;\n+\t\tinput[i].shape.y = model->metadata.input[i].shape.y;\n+\t\tinput[i].shape.z = model->metadata.input[i].shape.z;\n+\t}\n+\n+\t/* Set output info */\n+\tfor (i = 0; i < info->nb_outputs; i++) {\n+\t\trte_memcpy(output[i].name, model->metadata.output[i].output_name,\n+\t\t\t MRVL_ML_OUTPUT_NAME_LEN);\n+\t\toutput[i].dtype = model->metadata.output[i].output_type;\n+\t\toutput[i].qtype = model->metadata.output[i].model_output_type;\n+\t\toutput[i].shape.format = RTE_ML_IO_FORMAT_1D;\n+\t\toutput[i].shape.w = model->metadata.output[i].size;\n+\t\toutput[i].shape.x = 1;\n+\t\toutput[i].shape.y = 1;\n+\t\toutput[i].shape.z = 1;\n+\t}\n+}\ndiff --git a/drivers/ml/cnxk/cn10k_ml_model.h b/drivers/ml/cnxk/cn10k_ml_model.h\nindex 355915deeb..75990fe1e4 100644\n--- a/drivers/ml/cnxk/cn10k_ml_model.h\n+++ b/drivers/ml/cnxk/cn10k_ml_model.h\n@@ -422,6 +422,14 @@ struct cn10k_ml_model {\n \t/* Tile and memory information object */\n \tstruct cn10k_ml_ocm_model_map model_mem_map;\n \n+\t/* Internal model information structure\n+\t * Size of the buffer = sizeof(struct rte_ml_model_info)\n+\t * + num_inputs * sizeof(struct rte_ml_io_info)\n+\t * + num_outputs * sizeof(struct rte_ml_io_info).\n+\t * Structures would be arranged in the same order in the buffer.\n+\t */\n+\tuint8_t *info;\n+\n \t/* Spinlock, used to update model state */\n \tplt_spinlock_t lock;\n \n@@ -438,5 +446,6 @@ void cn10k_ml_model_addr_update(struct cn10k_ml_model *model, uint8_t *buffer,\n \t\t\t\tuint8_t *base_dma_addr);\n int cn10k_ml_model_ocm_pages_count(struct cn10k_ml_dev *mldev, uint16_t model_id, uint8_t *buffer,\n \t\t\t\t uint16_t *wb_pages, uint16_t *scratch_pages);\n+void cn10k_ml_model_info_set(struct rte_ml_dev *dev, struct cn10k_ml_model *model);\n \n #endif /* _CN10K_ML_MODEL_H_ */\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 77d3728d8d..ad9b3dfd21 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -506,6 +506,7 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \tchar str[RTE_MEMZONE_NAMESIZE];\n \tconst struct plt_memzone *mz;\n \tsize_t model_data_size;\n+\tsize_t model_info_size;\n \tuint8_t *base_dma_addr;\n \tuint16_t scratch_pages;\n \tuint16_t wb_pages;\n@@ -544,8 +545,13 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \tmodel_data_size = metadata->init_model.file_size + metadata->main_model.file_size +\n \t\t\t metadata->finish_model.file_size + metadata->weights_bias.file_size;\n \tmodel_data_size = PLT_ALIGN_CEIL(model_data_size, ML_CN10K_ALIGN_SIZE);\n+\tmodel_info_size = sizeof(struct rte_ml_model_info) +\n+\t\t\t metadata->model.num_input * sizeof(struct rte_ml_io_info) +\n+\t\t\t metadata->model.num_output * sizeof(struct rte_ml_io_info);\n+\tmodel_info_size = PLT_ALIGN_CEIL(model_info_size, ML_CN10K_ALIGN_SIZE);\n+\n \tmz_size = PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE) +\n-\t\t 2 * model_data_size +\n+\t\t 2 * model_data_size + model_info_size +\n \t\t PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_req), ML_CN10K_ALIGN_SIZE);\n \n \t/* Allocate memzone for model object and model data */\n@@ -585,10 +591,12 @@ cn10k_ml_model_load(struct rte_ml_dev *dev, struct rte_ml_model_params *params,\n \tmodel->model_mem_map.wb_pages = wb_pages;\n \tmodel->model_mem_map.scratch_pages = scratch_pages;\n \n+\t/* Set model info */\n+\tmodel->info = PLT_PTR_ADD(base_dma_addr, 2 * model_data_size);\n+\tcn10k_ml_model_info_set(dev, model);\n+\n \t/* Set slow-path request address and state */\n-\tmodel->req = PLT_PTR_ADD(\n-\t\tmz->addr, PLT_ALIGN_CEIL(sizeof(struct cn10k_ml_model), ML_CN10K_ALIGN_SIZE) +\n-\t\t\t\t 2 * model_data_size);\n+\tmodel->req = PLT_PTR_ADD(model->info, model_info_size);\n \n \tplt_spinlock_init(&model->lock);\n \tmodel->state = ML_CN10K_MODEL_STATE_LOADED;\n@@ -877,6 +885,26 @@ cn10k_ml_model_stop(struct rte_ml_dev *dev, uint16_t model_id)\n \treturn ret;\n }\n \n+static int\n+cn10k_ml_model_info_get(struct rte_ml_dev *dev, uint16_t model_id,\n+\t\t\tstruct rte_ml_model_info *model_info)\n+{\n+\tstruct cn10k_ml_model *model;\n+\n+\tmodel = dev->data->models[model_id];\n+\n+\tif (model == NULL) {\n+\t\tplt_err(\"Invalid model_id = %u\", model_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trte_memcpy(model_info, model->info, sizeof(struct rte_ml_model_info));\n+\tmodel_info->input_info = ((struct rte_ml_model_info *)model->info)->input_info;\n+\tmodel_info->output_info = ((struct rte_ml_model_info *)model->info)->output_info;\n+\n+\treturn 0;\n+}\n+\n struct rte_ml_dev_ops cn10k_ml_ops = {\n \t/* Device control ops */\n \t.dev_info_get = cn10k_ml_dev_info_get,\n@@ -894,4 +922,5 @@ struct rte_ml_dev_ops cn10k_ml_ops = {\n \t.model_unload = cn10k_ml_model_unload,\n \t.model_start = cn10k_ml_model_start,\n \t.model_stop = cn10k_ml_model_stop,\n+\t.model_info_get = cn10k_ml_model_info_get,\n };\n", "prefixes": [ "v5", "20/39" ] }