Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/122737/?format=api
{ "id": 122737, "url": "https://patches.dpdk.org/api/patches/122737/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-14-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230131093346.1261066-14-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230131093346.1261066-14-valex@nvidia.com", "date": "2023-01-31T09:33:42", "name": "[v1,13/16] net/mlx5/hws: add FW WQE rule creation logic", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6157c8c5da2c598b15db436f05aa03eb26486da9", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-14-valex@nvidia.com/mbox/", "series": [ { "id": 26709, "url": "https://patches.dpdk.org/api/series/26709/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26709", "date": "2023-01-31T09:33:29", "name": "net/mlx5/hws: support range and partial hash matching", "version": 1, "mbox": "https://patches.dpdk.org/series/26709/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/122737/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/122737/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C7BEE41B8D;\n\tTue, 31 Jan 2023 10:36:38 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4C3FC42FBE;\n\tTue, 31 Jan 2023 10:35:08 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41])\n by mails.dpdk.org (Postfix) with ESMTP id 1994542FB6\n for <dev@dpdk.org>; Tue, 31 Jan 2023 10:35:06 +0100 (CET)", "from MW4PR02CA0029.namprd02.prod.outlook.com (2603:10b6:303:16d::34)\n by IA1PR12MB6460.namprd12.prod.outlook.com (2603:10b6:208:3a8::13)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.36; Tue, 31 Jan\n 2023 09:35:02 +0000", "from CO1NAM11FT073.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:16d:cafe::1a) by MW4PR02CA0029.outlook.office365.com\n (2603:10b6:303:16d::34) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.38 via Frontend\n Transport; Tue, 31 Jan 2023 09:35:02 +0000", "from mail.nvidia.com (216.228.117.161) by\n CO1NAM11FT073.mail.protection.outlook.com (10.13.174.196) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6043.22 via Frontend Transport; Tue, 31 Jan 2023 09:35:01 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 31 Jan\n 2023 01:34:35 -0800", "from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 31 Jan\n 2023 01:34:33 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=UbrfKTUI45bRBbd34I+J79Ot9GXG1F7W69WPjTO/BB5mLflmBK8p9780pd/BFBhQ87d2KC6bpjT4pSo9f9VVsYZkRpZVQpe3lw7GYjVQdCzoTDdUINliWERo0scTpwqVqsoEEDq2G7FrVerDldgND//QttndgiM94zd8P62cVLRDu7cAXDLde+SxfQX90zEsQehlDSbo6PBhap11K7EzVudl2pFX7RorhUvknpm3KtUOhHS5K5xX4bA4+32rXo7he8mBIa8U0n0CwzbTuA4+e1NLngOOBKk0pPu6iV4cHqUy8ppC6w6oGUMm7JQ0xf3iARmnXiE1KU2MCrikW6bdpg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=OxgQ0X7ix7NBxlZTaovIw5RPA+AoAz67E6HKahbO9i8=;\n b=EK28TS0yP5zhKn3z9YwtMiZY9kzUvkUOAbFnIzyQDc8TC3NyB6ZdqWvkYAHWK2ORm1QBcilbTo5UYZeuktk5132EzZsfr42CE7yz+sHRYH6i4LgqCT8mc5Z5rLAUV1iU+eSgkqssG41WQgrogTxFnb8HmH7iNzwQxlimJs4+vjrW0BfWa81RbhHagCobzxXVxXbL0pktiwaRcB4W0qxq+izfdCWpZwvQPjz5aAcKVV4F6D4dJfAB1GR72Mx7sb2nhzekgjKTLJb4ithFEfcCd+Q4I9TSm/TdT1m9J3feixFMYIrNErYa1byZf2V1nTv7OdBSHVlZBqSNrUo3MizY9g==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=OxgQ0X7ix7NBxlZTaovIw5RPA+AoAz67E6HKahbO9i8=;\n b=lBLLRFF0cinpiTQ7hMimxJvNPTD5iA1QpfJBNCWkrfsiOGSQnYyUZV6vBgHIkIxfh9zqQ8s9zCfimwls+a1PWFDTjpfdQUwAT2Dibu3kYVqzTR28+O+mMIczBO0o6c3tnJ9fWzzwh0rxBTV7T79VfWA8kGXT3uTtfbSKum0yCaJdzIIn4crpq/r371w9Kt81RnMaWcok7QimMrcQl5dZ4XWTpJrJHM4cuOx2VOKY70kcTz6vUnveTpWOYjN1Q3Ui4gK67iVqkJqMjosm5w9HIDlyWvFuCAXMj/wE6OiZ1WN7hPmywz5Vv/48aUHDXl8wFE0k3F+zN9t/PKgcv+CCcg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v1 13/16] net/mlx5/hws: add FW WQE rule creation logic", "Date": "Tue, 31 Jan 2023 11:33:42 +0200", "Message-ID": "<20230131093346.1261066-14-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT073:EE_|IA1PR12MB6460:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f3c843c7-5abb-492a-925f-08db036e6d67", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +f+Kt965ZyEKjlJ9iKa0ir/4al25v7b7vwTBGjm7XQ1wk3OV7eRz79jP6YHn1BqZElQe5aI+OtKiDpWVcnrXzJz1UXcynJqlwaz9nyq6eSeB4bb9t9KTk0tKi40bj519y/7nfy+8j2aB/S+0VbJJRWVVCkBW9AI/2ak0GCFfBEATL/Z562d46Yn4yin8y2Yovw6C+dFeIJvTd+/TmXt/37U7GtxvoHJHrsYdW1HubJbL/E9RLKDmKu0tL1MMXfE/Akr4h+0uny3IJlvItE2c6fLD7O9p67925JnAaKed6zo7+kYvtQsknxBS6y/froIyXPkJmSlUa6iUXrfyYzQY2jeydQCpY3KVEF5UuuzN87SUk0ingPkOtaVV5VHbyV7ItuBtWSMqEv8kaOIc+ZPTz6kZjwnJQjiwCZx/HJJcHW9LwBZljgojvvD+HCDgbGqLP15PuXzkBRPAZ7D8ki9rO7q3C+BrDZadX6EpHRvU4tZmLGlMfsYC+g80Ykcrtm3DDGs/Of/qe1LDNTRbdvPuECkVixRlm3hPdh+smXO2b2/qKyKOH3+JY4kxurxD9rykDpZEjy0iAhKcCdkOeFEirIfE2cBstf+q5165rGlyJE+7yh5S3KPv9eI0uTU+namVvqgiqQOxnTDWKkiUNIyBRIJ2yRPKb1eJdP35BPh5eRJkXjtkWUHs8HLWgBdvK3+jmAT1YuEl6vkX4d16YkFvlg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(396003)(346002)(136003)(376002)(39860400002)(451199018)(46966006)(40470700004)(36840700001)(30864003)(83380400001)(47076005)(426003)(336012)(7636003)(86362001)(82740400003)(356005)(82310400005)(36756003)(2906002)(7696005)(40460700003)(36860700001)(1076003)(478600001)(16526019)(2616005)(6286002)(186003)(26005)(107886003)(55016003)(6666004)(8676002)(8936002)(4326008)(41300700001)(70586007)(70206006)(40480700001)(54906003)(5660300002)(6636002)(110136005)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Jan 2023 09:35:01.8284 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f3c843c7-5abb-492a-925f-08db036e6d67", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT073.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6460", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "FW WQE and HW WQE are done in a similar way but not to\njeopardize the performance rule creation is done over\nthe new FW rule creation function. The deletion function\nis shared between both flows.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_rule.c | 180 +++++++++++++++++++++++++++--\n drivers/net/mlx5/hws/mlx5dr_rule.h | 2 +\n drivers/net/mlx5/hws/mlx5dr_send.h | 9 +-\n 3 files changed, 180 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c\nindex f5a0c46315..9d5e5b11a5 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c\n@@ -112,6 +112,62 @@ static void mlx5dr_rule_gen_comp(struct mlx5dr_send_engine *queue,\n \tmlx5dr_send_engine_gen_comp(queue, user_data, comp_status);\n }\n \n+static void\n+mlx5dr_rule_save_delete_info(struct mlx5dr_rule *rule,\n+\t\t\t struct mlx5dr_send_ste_attr *ste_attr)\n+{\n+\tif (unlikely(mlx5dr_matcher_req_fw_wqe(rule->matcher))) {\n+\t\tuint8_t *src_tag;\n+\n+\t\t/* Save match definer id and tag for delete */\n+\t\trule->tag_ptr = simple_calloc(2, sizeof(*rule->tag_ptr));\n+\t\tassert(rule->tag_ptr);\n+\n+\t\tsrc_tag = (uint8_t *)ste_attr->wqe_data->tag;\n+\t\tmemcpy(rule->tag_ptr[0].match, src_tag, MLX5DR_MATCH_TAG_SZ);\n+\t\trule->tag_ptr[1].reserved[0] = ste_attr->send_attr.match_definer_id;\n+\n+\t\t/* Save range definer id and tag for delete */\n+\t\tif (ste_attr->range_wqe_data) {\n+\t\t\tsrc_tag = (uint8_t *)ste_attr->range_wqe_data->tag;\n+\t\t\tmemcpy(rule->tag_ptr[1].match, src_tag, MLX5DR_MATCH_TAG_SZ);\n+\t\t\trule->tag_ptr[1].reserved[1] = ste_attr->send_attr.range_definer_id;\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\tif (ste_attr->wqe_tag_is_jumbo)\n+\t\tmemcpy(rule->tag.jumbo, ste_attr->wqe_data->jumbo, MLX5DR_JUMBO_TAG_SZ);\n+\telse\n+\t\tmemcpy(rule->tag.match, ste_attr->wqe_data->tag, MLX5DR_MATCH_TAG_SZ);\n+}\n+\n+static void\n+mlx5dr_rule_clear_delete_info(struct mlx5dr_rule *rule)\n+{\n+\tif (unlikely(mlx5dr_matcher_req_fw_wqe(rule->matcher)))\n+\t\tsimple_free(rule->tag_ptr);\n+}\n+\n+static void\n+mlx5dr_rule_load_delete_info(struct mlx5dr_rule *rule,\n+\t\t\t struct mlx5dr_send_ste_attr *ste_attr)\n+{\n+\tif (unlikely(mlx5dr_matcher_req_fw_wqe(rule->matcher))) {\n+\t\t/* Load match definer id and tag for delete */\n+\t\tste_attr->wqe_tag = &rule->tag_ptr[0];\n+\t\tste_attr->send_attr.match_definer_id = rule->tag_ptr[1].reserved[0];\n+\n+\t\t/* Load range definer id and tag for delete */\n+\t\tif (rule->matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER) {\n+\t\t\tste_attr->range_wqe_tag = &rule->tag_ptr[1];\n+\t\t\tste_attr->send_attr.range_definer_id = rule->tag_ptr[1].reserved[1];\n+\t\t}\n+\t} else {\n+\t\tste_attr->wqe_tag = &rule->tag;\n+\t}\n+}\n+\n static int mlx5dr_rule_alloc_action_ste(struct mlx5dr_rule *rule,\n \t\t\t\t\tstruct mlx5dr_rule_attr *attr)\n {\n@@ -180,6 +236,97 @@ static void mlx5dr_rule_create_init(struct mlx5dr_rule *rule,\n \tapply->require_dep = 0;\n }\n \n+static int mlx5dr_rule_create_hws_fw_wqe(struct mlx5dr_rule *rule,\n+\t\t\t\t\t struct mlx5dr_rule_attr *attr,\n+\t\t\t\t\t uint8_t mt_idx,\n+\t\t\t\t\t const struct rte_flow_item items[],\n+\t\t\t\t\t uint8_t at_idx,\n+\t\t\t\t\t struct mlx5dr_rule_action rule_actions[])\n+{\n+\tstruct mlx5dr_action_template *at = &rule->matcher->at[at_idx];\n+\tstruct mlx5dr_match_template *mt = &rule->matcher->mt[mt_idx];\n+\tstruct mlx5dr_send_ring_dep_wqe range_wqe = {{0}};\n+\tstruct mlx5dr_send_ring_dep_wqe match_wqe = {{0}};\n+\tbool is_range = mlx5dr_matcher_mt_is_range(mt);\n+\tbool is_jumbo = mlx5dr_matcher_mt_is_jumbo(mt);\n+\tstruct mlx5dr_matcher *matcher = rule->matcher;\n+\tstruct mlx5dr_context *ctx = matcher->tbl->ctx;\n+\tstruct mlx5dr_send_ste_attr ste_attr = {0};\n+\tstruct mlx5dr_actions_apply_data apply;\n+\tstruct mlx5dr_send_engine *queue;\n+\n+\tqueue = &ctx->send_queue[attr->queue_id];\n+\tif (unlikely(mlx5dr_send_engine_err(queue))) {\n+\t\trte_errno = EIO;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tmlx5dr_rule_create_init(rule, &ste_attr, &apply);\n+\tmlx5dr_rule_init_dep_wqe(&match_wqe, rule, items, mt, attr->user_data);\n+\tmlx5dr_rule_init_dep_wqe(&range_wqe, rule, items, mt, attr->user_data);\n+\n+\tste_attr.direct_index = 0;\n+\tste_attr.rtc_0 = match_wqe.rtc_0;\n+\tste_attr.rtc_1 = match_wqe.rtc_1;\n+\tste_attr.used_id_rtc_0 = &rule->rtc_0;\n+\tste_attr.used_id_rtc_1 = &rule->rtc_1;\n+\tste_attr.retry_rtc_0 = match_wqe.retry_rtc_0;\n+\tste_attr.retry_rtc_1 = match_wqe.retry_rtc_1;\n+\tste_attr.send_attr.rule = match_wqe.rule;\n+\tste_attr.send_attr.user_data = match_wqe.user_data;\n+\n+\tste_attr.send_attr.fence = 1;\n+\tste_attr.send_attr.notify_hw = 1;\n+\tste_attr.wqe_tag_is_jumbo = is_jumbo;\n+\n+\t/* Prepare match STE TAG */\n+\tste_attr.wqe_ctrl = &match_wqe.wqe_ctrl;\n+\tste_attr.wqe_data = &match_wqe.wqe_data;\n+\tste_attr.send_attr.match_definer_id = mlx5dr_definer_get_id(mt->definer);\n+\n+\tmlx5dr_definer_create_tag(items,\n+\t\t\t\t mt->fc,\n+\t\t\t\t mt->fc_sz,\n+\t\t\t\t (uint8_t *)match_wqe.wqe_data.action);\n+\n+\t/* Prepare range STE TAG */\n+\tif (is_range) {\n+\t\tste_attr.range_wqe_data = &range_wqe.wqe_data;\n+\t\tste_attr.send_attr.len += MLX5DR_WQE_SZ_GTA_DATA;\n+\t\tste_attr.send_attr.range_definer_id = mlx5dr_definer_get_id(mt->range_definer);\n+\n+\t\tmlx5dr_definer_create_tag_range(items,\n+\t\t\t\t\t\tmt->fcr,\n+\t\t\t\t\t\tmt->fcr_sz,\n+\t\t\t\t\t\t(uint8_t *)range_wqe.wqe_data.action);\n+\t}\n+\n+\t/* Apply the actions on the last STE */\n+\tapply.queue = queue;\n+\tapply.next_direct_idx = 0;\n+\tapply.rule_action = rule_actions;\n+\tapply.wqe_ctrl = &match_wqe.wqe_ctrl;\n+\tapply.wqe_data = (uint32_t *)(is_range ?\n+\t\t\t\t &range_wqe.wqe_data :\n+\t\t\t\t &match_wqe.wqe_data);\n+\n+\t/* Skip setters[0] used for jumbo STE since not support with FW WQE */\n+\tmlx5dr_action_apply_setter(&apply, &at->setters[1], 0);\n+\n+\t/* Send WQEs to FW */\n+\tmlx5dr_send_stes_fw(queue, &ste_attr);\n+\n+\t/* Backup TAG on the rule for deletion */\n+\tmlx5dr_rule_save_delete_info(rule, &ste_attr);\n+\tmlx5dr_send_engine_inc_rule(queue);\n+\n+\t/* Send dependent WQEs */\n+\tif (!attr->burst)\n+\t\tmlx5dr_send_all_dep_wqe(queue);\n+\n+\treturn 0;\n+}\n+\n static int mlx5dr_rule_create_hws(struct mlx5dr_rule *rule,\n \t\t\t\t struct mlx5dr_rule_attr *attr,\n \t\t\t\t uint8_t mt_idx,\n@@ -189,7 +336,7 @@ static int mlx5dr_rule_create_hws(struct mlx5dr_rule *rule,\n {\n \tstruct mlx5dr_action_template *at = &rule->matcher->at[at_idx];\n \tstruct mlx5dr_match_template *mt = &rule->matcher->mt[mt_idx];\n-\tbool is_jumbo = mlx5dr_definer_is_jumbo(mt->definer);\n+\tbool is_jumbo = mlx5dr_matcher_mt_is_jumbo(mt);\n \tstruct mlx5dr_matcher *matcher = rule->matcher;\n \tstruct mlx5dr_context *ctx = matcher->tbl->ctx;\n \tstruct mlx5dr_send_ste_attr ste_attr = {0};\n@@ -200,6 +347,11 @@ static int mlx5dr_rule_create_hws(struct mlx5dr_rule *rule,\n \tuint8_t total_stes, action_stes;\n \tint i, ret;\n \n+\t/* Insert rule using FW WQE if cannot use GTA WQE */\n+\tif (unlikely(mlx5dr_matcher_req_fw_wqe(matcher)))\n+\t\treturn mlx5dr_rule_create_hws_fw_wqe(rule, attr, mt_idx, items,\n+\t\t\t\t\t\t at_idx, rule_actions);\n+\n \tqueue = &ctx->send_queue[attr->queue_id];\n \tif (unlikely(mlx5dr_send_engine_err(queue))) {\n \t\trte_errno = EIO;\n@@ -283,11 +435,7 @@ static int mlx5dr_rule_create_hws(struct mlx5dr_rule *rule,\n \t}\n \n \t/* Backup TAG on the rule for deletion */\n-\tif (is_jumbo)\n-\t\tmemcpy(rule->tag.jumbo, dep_wqe->wqe_data.action, MLX5DR_JUMBO_TAG_SZ);\n-\telse\n-\t\tmemcpy(rule->tag.match, dep_wqe->wqe_data.tag, MLX5DR_MATCH_TAG_SZ);\n-\n+\tmlx5dr_rule_save_delete_info(rule, &ste_attr);\n \tmlx5dr_send_engine_inc_rule(queue);\n \n \t/* Send dependent WQEs */\n@@ -311,6 +459,9 @@ static void mlx5dr_rule_destroy_failed_hws(struct mlx5dr_rule *rule,\n \t/* Rule failed now we can safely release action STEs */\n \tmlx5dr_rule_free_action_ste_idx(rule);\n \n+\t/* Clear complex tag */\n+\tmlx5dr_rule_clear_delete_info(rule);\n+\n \t/* If a rule that was indicated as burst (need to trigger HW) has failed\n \t * insertion we won't ring the HW as nothing is being written to the WQ.\n \t * In such case update the last WQE and ring the HW with that work\n@@ -327,6 +478,9 @@ static int mlx5dr_rule_destroy_hws(struct mlx5dr_rule *rule,\n {\n \tstruct mlx5dr_context *ctx = rule->matcher->tbl->ctx;\n \tstruct mlx5dr_matcher *matcher = rule->matcher;\n+\tbool fw_wqe = mlx5dr_matcher_req_fw_wqe(matcher);\n+\tbool is_range = mlx5dr_matcher_mt_is_range(matcher->mt);\n+\tbool is_jumbo = mlx5dr_matcher_mt_is_jumbo(matcher->mt);\n \tstruct mlx5dr_wqe_gta_ctrl_seg wqe_ctrl = {0};\n \tstruct mlx5dr_send_ste_attr ste_attr = {0};\n \tstruct mlx5dr_send_engine *queue;\n@@ -361,6 +515,8 @@ static int mlx5dr_rule_destroy_hws(struct mlx5dr_rule *rule,\n \tste_attr.send_attr.opmod = MLX5DR_WQE_GTA_OPMOD_STE;\n \tste_attr.send_attr.opcode = MLX5DR_WQE_OPCODE_TBL_ACCESS;\n \tste_attr.send_attr.len = MLX5DR_WQE_SZ_GTA_CTRL + MLX5DR_WQE_SZ_GTA_DATA;\n+\tif (unlikely(is_range))\n+\t\tste_attr.send_attr.len += MLX5DR_WQE_SZ_GTA_DATA;\n \n \tste_attr.send_attr.rule = rule;\n \tste_attr.send_attr.notify_hw = !attr->burst;\n@@ -371,13 +527,19 @@ static int mlx5dr_rule_destroy_hws(struct mlx5dr_rule *rule,\n \tste_attr.used_id_rtc_0 = &rule->rtc_0;\n \tste_attr.used_id_rtc_1 = &rule->rtc_1;\n \tste_attr.wqe_ctrl = &wqe_ctrl;\n-\tste_attr.wqe_tag = &rule->tag;\n-\tste_attr.wqe_tag_is_jumbo = mlx5dr_definer_is_jumbo(matcher->mt->definer);\n+\tste_attr.wqe_tag_is_jumbo = is_jumbo;\n \tste_attr.gta_opcode = MLX5DR_WQE_GTA_OP_DEACTIVATE;\n \tif (unlikely(mlx5dr_matcher_is_insert_by_idx(matcher)))\n \t\tste_attr.direct_index = attr->rule_idx;\n \n-\tmlx5dr_send_ste(queue, &ste_attr);\n+\tmlx5dr_rule_load_delete_info(rule, &ste_attr);\n+\n+\tif (unlikely(fw_wqe)) {\n+\t\tmlx5dr_send_stes_fw(queue, &ste_attr);\n+\t\tmlx5dr_rule_clear_delete_info(rule);\n+\t} else {\n+\t\tmlx5dr_send_ste(queue, &ste_attr);\n+\t}\n \n \treturn 0;\n }\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_rule.h b/drivers/net/mlx5/hws/mlx5dr_rule.h\nindex f2fe418159..886cf77992 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.h\n@@ -36,6 +36,8 @@ struct mlx5dr_rule {\n \tstruct mlx5dr_matcher *matcher;\n \tunion {\n \t\tstruct mlx5dr_rule_match_tag tag;\n+\t\t/* Pointer to tag to store more than one tag */\n+\t\tstruct mlx5dr_rule_match_tag *tag_ptr;\n \t\tstruct ibv_flow *flow;\n \t};\n \tuint32_t rtc_0; /* The RTC into which the STE was inserted */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.h b/drivers/net/mlx5/hws/mlx5dr_send.h\nindex 47bb66b3c7..d0977ec851 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.h\n@@ -54,8 +54,13 @@ struct mlx5dr_wqe_gta_data_seg_ste {\n \t__be32 rsvd0_ctr_id;\n \t__be32 rsvd1_definer;\n \t__be32 rsvd2[3];\n-\t__be32 action[3];\n-\t__be32 tag[8];\n+\tunion {\n+\t\tstruct {\n+\t\t\t__be32 action[3];\n+\t\t\t__be32 tag[8];\n+\t\t};\n+\t\t__be32 jumbo[11];\n+\t};\n };\n \n struct mlx5dr_wqe_gta_data_seg_arg {\n", "prefixes": [ "v1", "13/16" ] }