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GET /api/patches/122734/?format=api
{ "id": 122734, "url": "https://patches.dpdk.org/api/patches/122734/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-17-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230131093346.1261066-17-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230131093346.1261066-17-valex@nvidia.com", "date": "2023-01-31T09:33:45", "name": "[v1,16/16] net/mlx5/hws: cache definer for reuse", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "043beb268cefed16cf81752ca89da78b3016423f", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-17-valex@nvidia.com/mbox/", "series": [ { "id": 26709, "url": "https://patches.dpdk.org/api/series/26709/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26709", "date": "2023-01-31T09:33:29", "name": "net/mlx5/hws: support range and partial hash matching", "version": 1, "mbox": "https://patches.dpdk.org/series/26709/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/122734/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/122734/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A30DF41B8D;\n\tTue, 31 Jan 2023 10:36:16 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5898642D5D;\n\tTue, 31 Jan 2023 10:35:00 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2075.outbound.protection.outlook.com [40.107.243.75])\n by mails.dpdk.org (Postfix) with ESMTP id D679142D79\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v1 16/16] net/mlx5/hws: cache definer for reuse", "Date": "Tue, 31 Jan 2023 11:33:45 +0200", "Message-ID": "<20230131093346.1261066-17-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT039:EE_|PH0PR12MB7012:EE_", "X-MS-Office365-Filtering-Correlation-Id": "40032da9-1d18-4e96-af9e-08db036e6a69", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n bDR9fcGw8iusGzhUSMJMJ0AFI8uaBTicbikeAiNF1rSuwL3l0UrrJpNCNFYhOV+yJVr6YXfamx+eTK8OsLrwbo1ta/29s33Zze7YCws3A1CWAqAwBG6kLbvYWHousdKbuDugcn/fmd94CUhOkljfSPpLbKmaI6bRshz/Va6/zu/vO1XsL5Zd7ZaO/qBeYae5Q/Lo7fqm3uSF13ptJl5Y2WgiUs9e1j3AXkYmw0P7mzurkvN9BlPrKQ1aJmNJD2KE1BH1K1uLARoq60Mp4DxOX2NeSmr0GTDJKUwbsFJdVLBhrMagFoghKPdvGH/8AJ3Pr1SXr/xmAqIduTYeWAYMml0Lq6daUzoZbfNy6cS0CyY3xXda0BbMc1kjrR/JyVhvRShyYfnD5gckckissQaGYBYuMvcxKq8VhA9TSLLPdIjR7rE0tVYAxu6FX6ThWB6b7OBv+XOx5TTcJWxarMntQnSOkCIQt9av2/8kj/fxNMN7Q+GoW/QnvsgZoCM2hZ2G6jQEWHkLooMT/60pwHNxYV8dfF3aJDL/KDab6wicvg+09pQhVFLM2vjTnUb9WolKoyNgSUF7lBn6JIwsu3K2RnuKNXWmoIeEGLtElpKIoo3V8UONG6N7sNxqs1G/DAMepl5Kj5fNYO6TeeauOakImCcXof4vgy9cduz/Lh/xYP4oJXwjmFsOzYY3gAiXHRqv4fbaCz/X+hWtlwkq5GXjXA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(346002)(136003)(396003)(376002)(39860400002)(451199018)(36840700001)(46966006)(40470700004)(40460700003)(8936002)(5660300002)(41300700001)(336012)(82740400003)(2616005)(8676002)(356005)(54906003)(478600001)(316002)(7636003)(6636002)(36756003)(4326008)(7696005)(2906002)(110136005)(16526019)(426003)(26005)(6286002)(47076005)(55016003)(186003)(107886003)(1076003)(70206006)(83380400001)(70586007)(36860700001)(86362001)(40480700001)(82310400005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Jan 2023 09:34:56.8560 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 40032da9-1d18-4e96-af9e-08db036e6a69", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT039.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7012", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Definers are a limited resource in the system per GVMI, to\navoid failure we try to improve bt checking if it is possible\nto reuse the definers in some cases. Added a cache on the context\nfor this purpose.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_context.c | 12 ++-\n drivers/net/mlx5/hws/mlx5dr_context.h | 1 +\n drivers/net/mlx5/hws/mlx5dr_definer.c | 122 ++++++++++++++++++++++----\n drivers/net/mlx5/hws/mlx5dr_definer.h | 14 +++\n 4 files changed, 130 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_context.c b/drivers/net/mlx5/hws/mlx5dr_context.c\nindex 6627337d9e..08a5ee92a5 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_context.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_context.c\n@@ -13,6 +13,9 @@ static int mlx5dr_context_pools_init(struct mlx5dr_context *ctx)\n \tif (mlx5dr_pat_init_pattern_cache(&ctx->pattern_cache))\n \t\treturn rte_errno;\n \n+\tif (mlx5dr_definer_init_cache(&ctx->definer_cache))\n+\t\tgoto uninit_pat_cache;\n+\n \t/* Create an STC pool per FT type */\n \tpool_attr.pool_type = MLX5DR_POOL_TYPE_STC;\n \tpool_attr.flags = MLX5DR_POOL_FLAGS_FOR_STC_POOL;\n@@ -35,8 +38,10 @@ static int mlx5dr_context_pools_init(struct mlx5dr_context *ctx)\n \t\tif (ctx->stc_pool[i])\n \t\t\tmlx5dr_pool_destroy(ctx->stc_pool[i]);\n \n-\tmlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);\n+\tmlx5dr_definer_uninit_cache(ctx->definer_cache);\n \n+uninit_pat_cache:\n+\tmlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);\n \treturn rte_errno;\n }\n \n@@ -44,12 +49,13 @@ static void mlx5dr_context_pools_uninit(struct mlx5dr_context *ctx)\n {\n \tint i;\n \n-\tmlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);\n-\n \tfor (i = 0; i < MLX5DR_TABLE_TYPE_MAX; i++) {\n \t\tif (ctx->stc_pool[i])\n \t\t\tmlx5dr_pool_destroy(ctx->stc_pool[i]);\n \t}\n+\n+\tmlx5dr_definer_uninit_cache(ctx->definer_cache);\n+\tmlx5dr_pat_uninit_pattern_cache(ctx->pattern_cache);\n }\n \n static int mlx5dr_context_init_pd(struct mlx5dr_context *ctx,\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_context.h b/drivers/net/mlx5/hws/mlx5dr_context.h\nindex a38d9484b3..0ba8d0c92e 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_context.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_context.h\n@@ -39,6 +39,7 @@ struct mlx5dr_context {\n \tstruct mlx5dr_context_common_res common_res[MLX5DR_TABLE_TYPE_MAX];\n \tstruct mlx5dr_context_shared_gvmi_res gvmi_res[MLX5DR_TABLE_TYPE_MAX];\n \tstruct mlx5dr_pattern_cache *pattern_cache;\n+\tstruct mlx5dr_definer_cache *definer_cache;\n \tpthread_spinlock_t ctrl_lock;\n \tenum mlx5dr_context_flags flags;\n \tstruct mlx5dr_send_engine *send_queue;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex cf84fbea71..b91f98ee8f 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -2061,6 +2061,7 @@ mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,\n {\n \tint i;\n \n+\t/* Future: Optimize by comparing selectors with valid mask only */\n \tfor (i = 0; i < BYTE_SELECTORS; i++)\n \t\tif (definer_a->byte_selector[i] != definer_b->byte_selector[i])\n \t\t\treturn 1;\n@@ -2133,15 +2134,106 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n \treturn rte_errno;\n }\n \n+int mlx5dr_definer_init_cache(struct mlx5dr_definer_cache **cache)\n+{\n+\tstruct mlx5dr_definer_cache *new_cache;\n+\n+\tnew_cache = simple_calloc(1, sizeof(*new_cache));\n+\tif (!new_cache) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn rte_errno;\n+\t}\n+\tLIST_INIT(&new_cache->head);\n+\t*cache = new_cache;\n+\n+\treturn 0;\n+}\n+\n+void mlx5dr_definer_uninit_cache(struct mlx5dr_definer_cache *cache)\n+{\n+\tsimple_free(cache);\n+}\n+\n+static struct mlx5dr_devx_obj *\n+mlx5dr_definer_get_obj(struct mlx5dr_context *ctx,\n+\t\t struct mlx5dr_definer *definer)\n+{\n+\tstruct mlx5dr_definer_cache *cache = ctx->definer_cache;\n+\tstruct mlx5dr_cmd_definer_create_attr def_attr = {0};\n+\tstruct mlx5dr_definer_cache_item *cached_definer;\n+\tstruct mlx5dr_devx_obj *obj;\n+\n+\t/* Search definer cache for requested definer */\n+\tLIST_FOREACH(cached_definer, &cache->head, next) {\n+\t\tif (mlx5dr_definer_compare(&cached_definer->definer, definer))\n+\t\t\tcontinue;\n+\n+\t\t/* Reuse definer and set LRU (move to be first in the list) */\n+\t\tLIST_REMOVE(cached_definer, next);\n+\t\tLIST_INSERT_HEAD(&cache->head, cached_definer, next);\n+\t\tcached_definer->refcount++;\n+\t\treturn cached_definer->definer.obj;\n+\t}\n+\n+\t/* Allocate and create definer based on the bitmask tag */\n+\tdef_attr.match_mask = definer->mask.jumbo;\n+\tdef_attr.dw_selector = definer->dw_selector;\n+\tdef_attr.byte_selector = definer->byte_selector;\n+\n+\tobj = mlx5dr_cmd_definer_create(ctx->ibv_ctx, &def_attr);\n+\tif (!obj)\n+\t\treturn NULL;\n+\n+\tcached_definer = simple_calloc(1, sizeof(*cached_definer));\n+\tif (!cached_definer) {\n+\t\trte_errno = ENOMEM;\n+\t\tgoto free_definer_obj;\n+\t}\n+\n+\tmemcpy(&cached_definer->definer, definer, sizeof(*definer));\n+\tcached_definer->definer.obj = obj;\n+\tcached_definer->refcount = 1;\n+\tLIST_INSERT_HEAD(&cache->head, cached_definer, next);\n+\n+\treturn obj;\n+\n+free_definer_obj:\n+\tmlx5dr_cmd_destroy_obj(obj);\n+\treturn NULL;\n+}\n+\n+static void\n+mlx5dr_definer_put_obj(struct mlx5dr_context *ctx,\n+\t\t struct mlx5dr_devx_obj *obj)\n+{\n+\tstruct mlx5dr_definer_cache_item *cached_definer;\n+\n+\tLIST_FOREACH(cached_definer, &ctx->definer_cache->head, next) {\n+\t\tif (cached_definer->definer.obj != obj)\n+\t\t\tcontinue;\n+\n+\t\t/* Object found */\n+\t\tif (--cached_definer->refcount)\n+\t\t\treturn;\n+\n+\t\tLIST_REMOVE(cached_definer, next);\n+\t\tmlx5dr_cmd_destroy_obj(cached_definer->definer.obj);\n+\t\tsimple_free(cached_definer);\n+\t\treturn;\n+\t}\n+\n+\t/* Programming error, object must be part of cache */\n+\tassert(false);\n+}\n+\n static struct mlx5dr_definer *\n-mlx5dr_definer_alloc(struct ibv_context *ibv_ctx,\n+mlx5dr_definer_alloc(struct mlx5dr_context *ctx,\n \t\t struct mlx5dr_definer_fc *fc,\n \t\t int fc_sz,\n \t\t struct rte_flow_item *items,\n \t\t struct mlx5dr_definer *layout,\n \t\t bool bind_fc)\n {\n-\tstruct mlx5dr_cmd_definer_create_attr def_attr = {0};\n \tstruct mlx5dr_definer *definer;\n \tint ret;\n \n@@ -2166,12 +2258,7 @@ mlx5dr_definer_alloc(struct ibv_context *ibv_ctx,\n \t/* Create the tag mask used for definer creation */\n \tmlx5dr_definer_create_tag_mask(items, fc, fc_sz, definer->mask.jumbo);\n \n-\t/* Create definer based on the bitmask tag */\n-\tdef_attr.match_mask = definer->mask.jumbo;\n-\tdef_attr.dw_selector = layout->dw_selector;\n-\tdef_attr.byte_selector = layout->byte_selector;\n-\n-\tdefiner->obj = mlx5dr_cmd_definer_create(ibv_ctx, &def_attr);\n+\tdefiner->obj = mlx5dr_definer_get_obj(ctx, definer);\n \tif (!definer->obj)\n \t\tgoto free_definer;\n \n@@ -2183,9 +2270,10 @@ mlx5dr_definer_alloc(struct ibv_context *ibv_ctx,\n }\n \n static void\n-mlx5dr_definer_free(struct mlx5dr_definer *definer)\n+mlx5dr_definer_free(struct mlx5dr_context *ctx,\n+\t\t struct mlx5dr_definer *definer)\n {\n-\tmlx5dr_cmd_destroy_obj(definer->obj);\n+\tmlx5dr_definer_put_obj(ctx, definer->obj);\n \tsimple_free(definer);\n }\n \n@@ -2199,7 +2287,7 @@ mlx5dr_definer_matcher_match_init(struct mlx5dr_context *ctx,\n \n \t/* Create mendatory match definer */\n \tfor (i = 0; i < matcher->num_of_mt; i++) {\n-\t\tmt[i].definer = mlx5dr_definer_alloc(ctx->ibv_ctx,\n+\t\tmt[i].definer = mlx5dr_definer_alloc(ctx,\n \t\t\t\t\t\t mt[i].fc,\n \t\t\t\t\t\t mt[i].fc_sz,\n \t\t\t\t\t\t mt[i].items,\n@@ -2214,7 +2302,7 @@ mlx5dr_definer_matcher_match_init(struct mlx5dr_context *ctx,\n \n free_definers:\n \twhile (i--)\n-\t\tmlx5dr_definer_free(mt[i].definer);\n+\t\tmlx5dr_definer_free(ctx, mt[i].definer);\n \n \treturn rte_errno;\n }\n@@ -2222,10 +2310,11 @@ mlx5dr_definer_matcher_match_init(struct mlx5dr_context *ctx,\n static void\n mlx5dr_definer_matcher_match_uninit(struct mlx5dr_matcher *matcher)\n {\n+\tstruct mlx5dr_context *ctx = matcher->tbl->ctx;\n \tint i;\n \n \tfor (i = 0; i < matcher->num_of_mt; i++)\n-\t\tmlx5dr_definer_free(matcher->mt[i].definer);\n+\t\tmlx5dr_definer_free(ctx, matcher->mt[i].definer);\n }\n \n static int\n@@ -2249,7 +2338,7 @@ mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx,\n \n \t\tmatcher->flags |= MLX5DR_MATCHER_FLAGS_RANGE_DEFINER;\n \t\t/* Create definer without fcr binding, already binded */\n-\t\tmt[i].range_definer = mlx5dr_definer_alloc(ctx->ibv_ctx,\n+\t\tmt[i].range_definer = mlx5dr_definer_alloc(ctx,\n \t\t\t\t\t\t\t mt[i].fcr,\n \t\t\t\t\t\t\t mt[i].fcr_sz,\n \t\t\t\t\t\t\t mt[i].items,\n@@ -2265,7 +2354,7 @@ mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx,\n free_definers:\n \twhile (i--)\n \t\tif (mt[i].range_definer)\n-\t\t\tmlx5dr_definer_free(mt[i].range_definer);\n+\t\t\tmlx5dr_definer_free(ctx, mt[i].range_definer);\n \n \treturn rte_errno;\n }\n@@ -2273,11 +2362,12 @@ mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx,\n static void\n mlx5dr_definer_matcher_range_uninit(struct mlx5dr_matcher *matcher)\n {\n+\tstruct mlx5dr_context *ctx = matcher->tbl->ctx;\n \tint i;\n \n \tfor (i = 0; i < matcher->num_of_mt; i++)\n \t\tif (matcher->mt[i].range_definer)\n-\t\t\tmlx5dr_definer_free(matcher->mt[i].range_definer);\n+\t\t\tmlx5dr_definer_free(ctx, matcher->mt[i].range_definer);\n }\n \n static int\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex dd9a297007..464872acd6 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -569,6 +569,16 @@ struct mlx5dr_definer {\n \tstruct mlx5dr_devx_obj *obj;\n };\n \n+struct mlx5dr_definer_cache {\n+\tLIST_HEAD(definer_head, mlx5dr_definer_cache_item) head;\n+};\n+\n+struct mlx5dr_definer_cache_item {\n+\tstruct mlx5dr_definer definer;\n+\tuint32_t refcount;\n+\tLIST_ENTRY(mlx5dr_definer_cache_item) next;\n+};\n+\n static inline bool\n mlx5dr_definer_is_jumbo(struct mlx5dr_definer *definer)\n {\n@@ -592,4 +602,8 @@ int mlx5dr_definer_matcher_init(struct mlx5dr_context *ctx,\n \n void mlx5dr_definer_matcher_uninit(struct mlx5dr_matcher *matcher);\n \n+int mlx5dr_definer_init_cache(struct mlx5dr_definer_cache **cache);\n+\n+void mlx5dr_definer_uninit_cache(struct mlx5dr_definer_cache *cache);\n+\n #endif\n", "prefixes": [ "v1", "16/16" ] }