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GET /api/patches/122723/?format=api
{ "id": 122723, "url": "https://patches.dpdk.org/api/patches/122723/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-2-valex@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230131093346.1261066-2-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230131093346.1261066-2-valex@nvidia.com", "date": "2023-01-31T09:33:30", "name": "[v1,01/16] net/mlx5/hws: support synchronous drain", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8cda7352acb4f421bd42a6f1c35404988b22801e", "submitter": { "id": 2858, "url": "https://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230131093346.1261066-2-valex@nvidia.com/mbox/", "series": [ { "id": 26709, "url": "https://patches.dpdk.org/api/series/26709/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26709", "date": "2023-01-31T09:33:29", "name": "net/mlx5/hws: support range and partial hash matching", "version": 1, "mbox": "https://patches.dpdk.org/series/26709/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/122723/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/122723/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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"Subject": "[v1 01/16] net/mlx5/hws: support synchronous drain", "Date": "Tue, 31 Jan 2023 11:33:30 +0200", "Message-ID": "<20230131093346.1261066-2-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT009:EE_|LV2PR12MB5799:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8b2ac231-e212-4a15-2466-08db036e5cae", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230025)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199018)(46966006)(36840700001)(40470700004)(36756003)(40460700003)(5660300002)(2906002)(82310400005)(2616005)(426003)(336012)(26005)(55016003)(6286002)(83380400001)(478600001)(7696005)(186003)(8676002)(54906003)(1076003)(6636002)(110136005)(16526019)(40480700001)(82740400003)(7636003)(356005)(316002)(47076005)(107886003)(86362001)(6666004)(4326008)(8936002)(41300700001)(70206006)(36860700001)(70586007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Jan 2023 09:34:33.7540 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8b2ac231-e212-4a15-2466-08db036e5cae", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT009.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5799", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Until now we supported asynchronous drain, triggering the queue\nto start the drain, now we added support for synchronous which\nassures all the work was processed on the queue.\n\nThis is useful when working over a FW command and HW queue in parallel\nsending arguments over the HW queue and match over the FW command\nwhich requires synchronization.\n\nThis also fixes an issue with shared arguments send that require more than\none WQE.\n\nSigned-off-by: Erez Shitrit <erezsh@nvidia.com>\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr.h | 6 ++++--\n drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 27 ++++-----------------------\n drivers/net/mlx5/hws/mlx5dr_send.c | 16 ++++++++++++++--\n drivers/net/mlx5/hws/mlx5dr_send.h | 5 +++++\n drivers/net/mlx5/mlx5_flow_hw.c | 2 +-\n 5 files changed, 28 insertions(+), 28 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h\nindex b3b2bf34f2..2b02884dc3 100644\n--- a/drivers/net/mlx5/hws/mlx5dr.h\n+++ b/drivers/net/mlx5/hws/mlx5dr.h\n@@ -86,8 +86,10 @@ enum mlx5dr_match_template_flags {\n };\n \n enum mlx5dr_send_queue_actions {\n-\t/* Start executing all pending queued rules and write to HW */\n-\tMLX5DR_SEND_QUEUE_ACTION_DRAIN = 1 << 0,\n+\t/* Start executing all pending queued rules */\n+\tMLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC = 1 << 0,\n+\t/* Start executing all pending queued rules wait till completion */\n+\tMLX5DR_SEND_QUEUE_ACTION_DRAIN_SYNC = 1 << 1,\n };\n \n struct mlx5dr_context_attr {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c\nindex df451f1ae0..152025d302 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_pat_arg.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_pat_arg.c\n@@ -306,27 +306,6 @@ void mlx5dr_arg_decapl3_write(struct mlx5dr_send_engine *queue,\n \tmlx5dr_send_engine_post_end(&ctrl, &send_attr);\n }\n \n-static int\n-mlx5dr_arg_poll_for_comp(struct mlx5dr_context *ctx, uint16_t queue_id)\n-{\n-\tstruct rte_flow_op_result comp[1];\n-\tint ret;\n-\n-\twhile (true) {\n-\t\tret = mlx5dr_send_queue_poll(ctx, queue_id, comp, 1);\n-\t\tif (ret) {\n-\t\t\tif (ret < 0) {\n-\t\t\t\tDR_LOG(ERR, \"Failed mlx5dr_send_queue_poll\");\n-\t\t\t} else if (comp[0].status == RTE_FLOW_OP_ERROR) {\n-\t\t\t\tDR_LOG(ERR, \"Got comp with error\");\n-\t\t\t\trte_errno = ENOENT;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\treturn (ret == 1 ? 0 : ret);\n-}\n-\n void mlx5dr_arg_write(struct mlx5dr_send_engine *queue,\n \t\t void *comp_data,\n \t\t uint32_t arg_idx,\n@@ -388,9 +367,11 @@ int mlx5dr_arg_write_inline_arg_data(struct mlx5dr_context *ctx,\n \tmlx5dr_send_engine_flush_queue(queue);\n \n \t/* Poll for completion */\n-\tret = mlx5dr_arg_poll_for_comp(ctx, ctx->queues - 1);\n+\tret = mlx5dr_send_queue_action(ctx, ctx->queues - 1,\n+\t\t\t\t MLX5DR_SEND_QUEUE_ACTION_DRAIN_SYNC);\n+\n \tif (ret)\n-\t\tDR_LOG(ERR, \"Failed to get completions for shared action\");\n+\t\tDR_LOG(ERR, \"Failed to drain arg queue\");\n \n \tpthread_spin_unlock(&ctx->ctrl_lock);\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c\nindex 5c8bbe6fc6..a507e5f626 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.c\n@@ -830,18 +830,30 @@ int mlx5dr_send_queue_action(struct mlx5dr_context *ctx,\n {\n \tstruct mlx5dr_send_ring_sq *send_sq;\n \tstruct mlx5dr_send_engine *queue;\n+\tbool wait_comp = false;\n+\tint64_t polled = 0;\n \n \tqueue = &ctx->send_queue[queue_id];\n \tsend_sq = &queue->send_ring->send_sq;\n \n-\tif (actions == MLX5DR_SEND_QUEUE_ACTION_DRAIN) {\n+\tswitch (actions) {\n+\tcase MLX5DR_SEND_QUEUE_ACTION_DRAIN_SYNC:\n+\t\twait_comp = true;\n+\t\t/* FALLTHROUGH */\n+\tcase MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC:\n \t\tif (send_sq->head_dep_idx != send_sq->tail_dep_idx)\n \t\t\t/* Send dependent WQEs to drain the queue */\n \t\t\tmlx5dr_send_all_dep_wqe(queue);\n \t\telse\n \t\t\t/* Signal on the last posted WQE */\n \t\t\tmlx5dr_send_engine_flush_queue(queue);\n-\t} else {\n+\n+\t\t/* Poll queue until empty */\n+\t\twhile (wait_comp && !mlx5dr_send_engine_empty(queue))\n+\t\t\tmlx5dr_send_engine_poll_cqs(queue, NULL, &polled, 0);\n+\n+\t\tbreak;\n+\tdefault:\n \t\trte_errno = -EINVAL;\n \t\treturn rte_errno;\n \t}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.h b/drivers/net/mlx5/hws/mlx5dr_send.h\nindex 8d4769495d..fcddcc6366 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.h\n@@ -240,6 +240,11 @@ void mlx5dr_send_ste(struct mlx5dr_send_engine *queue,\n \n void mlx5dr_send_engine_flush_queue(struct mlx5dr_send_engine *queue);\n \n+static inline bool mlx5dr_send_engine_empty(struct mlx5dr_send_engine *queue)\n+{\n+\treturn (queue->send_ring->send_sq.cur_post == queue->send_ring->send_cq.poll_wqe);\n+}\n+\n static inline bool mlx5dr_send_engine_full(struct mlx5dr_send_engine *queue)\n {\n \treturn queue->used_entries >= queue->th_entries;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 20c71ff7f0..7e87d589cb 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2851,7 +2851,7 @@ flow_hw_push(struct rte_eth_dev *dev,\n \n \t__flow_hw_push_action(dev, queue);\n \tret = mlx5dr_send_queue_action(priv->dr_ctx, queue,\n-\t\t\t\t MLX5DR_SEND_QUEUE_ACTION_DRAIN);\n+\t\t\t\t MLX5DR_SEND_QUEUE_ACTION_DRAIN_ASYNC);\n \tif (ret) {\n \t\trte_flow_error_set(error, rte_errno,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n", "prefixes": [ "v1", "01/16" ] }