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GET /api/patches/122255/?format=api
{ "id": 122255, "url": "https://patches.dpdk.org/api/patches/122255/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230118073154.903012-3-mingxia.liu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230118073154.903012-3-mingxia.liu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230118073154.903012-3-mingxia.liu@intel.com", "date": "2023-01-18T07:31:38", "name": "[v3,02/21] net/cpfl: add Tx queue setup", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6fdab323c237feb15da22cd3fd7114ed600e2ec3", "submitter": { "id": 2514, "url": "https://patches.dpdk.org/api/people/2514/?format=api", "name": "Liu, Mingxia", "email": "mingxia.liu@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230118073154.903012-3-mingxia.liu@intel.com/mbox/", "series": [ { "id": 26588, "url": "https://patches.dpdk.org/api/series/26588/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26588", "date": "2023-01-18T07:31:36", "name": "add support for cpfl PMD in DPDK", "version": 3, "mbox": "https://patches.dpdk.org/series/26588/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/122255/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/122255/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7119F4240B;\n\tWed, 18 Jan 2023 09:27:50 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B5E1D42D47;\n\tWed, 18 Jan 2023 09:27:41 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by mails.dpdk.org (Postfix) with ESMTP id B331D42C4D\n for <dev@dpdk.org>; Wed, 18 Jan 2023 09:27:39 +0100 (CET)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Jan 2023 00:27:38 -0800", "from dpdk-mingxial-01.sh.intel.com ([10.67.119.167])\n by orsmga007.jf.intel.com with ESMTP; 18 Jan 2023 00:27:36 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1674030459; x=1705566459;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=jCSGPJlu3dq/8PkKQsF3rRtHxEMPYZyoyVWM5i0tR2s=;\n b=YHi7Nn+3V5DeJAtNw1Y4W5fAkRaC6CKgkO2f6VvhuZgxFE1iRGnYevLT\n 9xnxihoCGlbZbKTNiH6yrE0HGfQ7b80GwdnBTqvgMw1fXg5phjKlk7t2e\n RR/+a2cpgu08Xm0ps3vdxzNK0BxTnG3n+ekbG7+GFsMoL3FwNtXF7PQPA\n EN+ADPywAjucBG6eoFa6uW+KEveipfM0sNjJnckwRnWC4FusXu7MXv0Ge\n z9hzoa5yacRoM6WiVfiIrY0euwdLnROEV7kcu/QNCtwsm6tPiTRWPTf7A\n xCFxgRTrWbj0W9kF3E2LKvjPSR4fuBqGJZQkTbNEttTkIqvttS2apG+fB Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10593\"; a=\"305304183\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"305304183\"", "E=McAfee;i=\"6500,9779,10593\"; a=\"652835184\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"652835184\"" ], "X-ExtLoop1": "1", "From": "Mingxia Liu <mingxia.liu@intel.com>", "To": "dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com,\n beilei.xing@intel.com", "Cc": "wenjun1.wu@intel.com,\n\tMingxia Liu <mingxia.liu@intel.com>", "Subject": "[PATCH v3 02/21] net/cpfl: add Tx queue setup", "Date": "Wed, 18 Jan 2023 07:31:38 +0000", "Message-Id": "<20230118073154.903012-3-mingxia.liu@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230118073154.903012-1-mingxia.liu@intel.com>", "References": "<20230113081931.221576-1-mingxia.liu@intel.com>\n <20230118073154.903012-1-mingxia.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for tx_queue_setup ops.\n\nIn the single queue model, the same descriptor queue is used by SW to\npost buffer descriptors to HW and by HW to post completed descriptors\nto SW.\n\nIn the split queue model, \"RX buffer queues\" are used to pass\ndescriptor buffers from SW to HW while Rx queues are used only to\npass the descriptor completions, that is, descriptors that point\nto completed buffers, from HW to SW. This is contrary to the single\nqueue model in which Rx queues are used for both purposes.\n\nSigned-off-by: Mingxia Liu <mingxia.liu@intel.com>\n---\n drivers/net/cpfl/cpfl_ethdev.c | 13 +++++++++++++\n drivers/net/cpfl/cpfl_rxtx.c | 8 ++++----\n drivers/net/cpfl/meson.build | 1 +\n 3 files changed, 18 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c\nindex 2ac53bc5b0..4a569c2f7e 100644\n--- a/drivers/net/cpfl/cpfl_ethdev.c\n+++ b/drivers/net/cpfl/cpfl_ethdev.c\n@@ -12,6 +12,7 @@\n #include <rte_alarm.h>\n \n #include \"cpfl_ethdev.h\"\n+#include \"cpfl_rxtx.h\"\n \n #define CPFL_TX_SINGLE_Q\t\"tx_single\"\n #define CPFL_RX_SINGLE_Q\t\"rx_single\"\n@@ -96,6 +97,17 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \tdev_info->max_mtu = vport->max_mtu;\n \tdev_info->min_mtu = RTE_ETHER_MIN_MTU;\n \n+\tdev_info->default_txconf = (struct rte_eth_txconf) {\n+\t\t.tx_free_thresh = CPFL_DEFAULT_TX_FREE_THRESH,\n+\t\t.tx_rs_thresh = CPFL_DEFAULT_TX_RS_THRESH,\n+\t};\n+\n+\tdev_info->tx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = CPFL_MAX_RING_DESC,\n+\t\t.nb_min = CPFL_MIN_RING_DESC,\n+\t\t.nb_align = CPFL_ALIGN_RING_DESC,\n+\t};\n+\n \treturn 0;\n }\n \n@@ -513,6 +525,7 @@ cpfl_adapter_ext_init(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *a\n static const struct eth_dev_ops cpfl_eth_dev_ops = {\n \t.dev_configure\t\t\t= cpfl_dev_configure,\n \t.dev_close\t\t\t= cpfl_dev_close,\n+\t.tx_queue_setup\t\t\t= cpfl_tx_queue_setup,\n \t.dev_infos_get\t\t\t= cpfl_dev_info_get,\n \t.link_update\t\t\t= cpfl_dev_link_update,\n \t.dev_supported_ptypes_get\t= cpfl_dev_supported_ptypes_get,\ndiff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c\nindex ea4a2002bf..a9742379db 100644\n--- a/drivers/net/cpfl/cpfl_rxtx.c\n+++ b/drivers/net/cpfl/cpfl_rxtx.c\n@@ -130,7 +130,7 @@ cpfl_tx_complq_setup(struct rte_eth_dev *dev, struct idpf_tx_queue *txq,\n \tcq->tx_ring_phys_addr = mz->iova;\n \tcq->compl_ring = mz->addr;\n \tcq->mz = mz;\n-\treset_split_tx_complq(cq);\n+\tidpf_reset_split_tx_complq(cq);\n \n \ttxq->complq = cq;\n \n@@ -164,7 +164,7 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\ttx_conf->tx_rs_thresh : CPFL_DEFAULT_TX_RS_THRESH);\n \ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh > 0) ?\n \t\ttx_conf->tx_free_thresh : CPFL_DEFAULT_TX_FREE_THRESH);\n-\tif (check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)\n+\tif (idpf_check_tx_thresh(nb_desc, tx_rs_thresh, tx_free_thresh) != 0)\n \t\treturn -EINVAL;\n \n \t/* Allocate the TX queue data structure. */\n@@ -215,10 +215,10 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \n \tif (!is_splitq) {\n \t\ttxq->tx_ring = mz->addr;\n-\t\treset_single_tx_queue(txq);\n+\t\tidpf_reset_single_tx_queue(txq);\n \t} else {\n \t\ttxq->desc_ring = mz->addr;\n-\t\treset_split_tx_descq(txq);\n+\t\tidpf_reset_split_tx_descq(txq);\n \n \t\t/* Setup tx completion queue if split model */\n \t\tret = cpfl_tx_complq_setup(dev, txq, queue_idx,\ndiff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build\nindex 106cc97e60..3ccee15703 100644\n--- a/drivers/net/cpfl/meson.build\n+++ b/drivers/net/cpfl/meson.build\n@@ -11,4 +11,5 @@ deps += ['common_idpf']\n \n sources = files(\n 'cpfl_ethdev.c',\n+ 'cpfl_rxtx.c',\n )\n\\ No newline at end of file\n", "prefixes": [ "v3", "02/21" ] }