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GET /api/patches/121617/?format=api
{ "id": 121617, "url": "https://patches.dpdk.org/api/patches/121617/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230105130304.537205-6-erezsh@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230105130304.537205-6-erezsh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230105130304.537205-6-erezsh@nvidia.com", "date": "2023-01-05T13:02:58", "name": "[v2,05/10] net/mlx5/hws: added allow-other-vhca-access command", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3fed101ef9c60cd209c22a222cabce95971f3eae", "submitter": { "id": 2911, "url": "https://patches.dpdk.org/api/people/2911/?format=api", "name": "Erez Shitrit", "email": "erezsh@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230105130304.537205-6-erezsh@nvidia.com/mbox/", "series": [ { "id": 26398, "url": "https://patches.dpdk.org/api/series/26398/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26398", "date": "2023-01-05T13:02:53", "name": "Support resource sharing among ibv_devices", "version": 2, "mbox": "https://patches.dpdk.org/series/26398/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/121617/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/121617/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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<viacheslavo@nvidia.com>", "Subject": "[PATCH v2 05/10] net/mlx5/hws: added allow-other-vhca-access command", "Date": "Thu, 5 Jan 2023 15:02:58 +0200", "Message-ID": "<20230105130304.537205-6-erezsh@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20230105130304.537205-1-erezsh@nvidia.com>", "References": "<20221219082416.2223812-3-erezsh@nvidia.com>\n <20230105130304.537205-1-erezsh@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT073:EE_|MN6PR12MB8544:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3559bfb6-3e7b-4cd4-5f68-08daef1d4c87", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230022)(4636009)(346002)(396003)(376002)(39860400002)(136003)(451199015)(36840700001)(46966006)(40470700004)(316002)(16526019)(54906003)(186003)(26005)(36860700001)(107886003)(2616005)(6286002)(6916009)(1076003)(4326008)(6666004)(70206006)(478600001)(426003)(41300700001)(47076005)(8936002)(5660300002)(83380400001)(2906002)(8676002)(336012)(70586007)(55016003)(40480700001)(82740400003)(356005)(86362001)(7636003)(7696005)(36756003)(40460700003)(82310400005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Jan 2023 13:03:54.1814 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3559bfb6-3e7b-4cd4-5f68-08daef1d4c87", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT073.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN6PR12MB8544", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Yevgeny Kliteynik <kliteyn@nvidia.com>\n\n\nAdded FW command to allow creation of alias objects.\n\nSigned-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>\nReviewed-by: Alex Vesker <valex@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 23 +++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 28 ++++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 9 +++++++++\n 3 files changed, 60 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex dfa25c2b49..9d36645949 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1133,6 +1133,7 @@ enum {\n \tMLX5_CMD_SET_REGEX_REGISTERS = 0xb06,\n \tMLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,\n \tMLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,\n+\tMLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16,\n };\n \n enum {\n@@ -3150,6 +3151,28 @@ struct mlx5_ifc_general_obj_out_cmd_hdr_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+struct mlx5_ifc_allow_other_vhca_access_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x50];\n+\tu8 object_type_to_be_accessed[0x10];\n+\tu8 object_id_to_be_accessed[0x20];\n+\tu8 reserved_at_c0[0x40];\n+\tunion {\n+\t\tu8 access_key_raw[0x100];\n+\t\tu8 access_key[8][0x20];\n+\t};\n+};\n+\n+struct mlx5_ifc_allow_other_vhca_access_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n struct mlx5_ifc_virtio_q_counters_bits {\n \tu8 modify_field_select[0x40];\n \tu8 reserved_at_40[0x40];\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nindex 2156fd6643..b120be2d88 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -716,6 +716,34 @@ int mlx5dr_cmd_sq_modify_rdy(struct mlx5dr_devx_obj *devx_obj)\n \treturn ret;\n }\n \n+int mlx5dr_cmd_allow_other_vhca_access(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5dr_cmd_allow_other_vhca_access_attr *attr)\n+{\n+\tuint32_t out[MLX5_ST_SZ_DW(allow_other_vhca_access_out)] = {0};\n+\tuint32_t in[MLX5_ST_SZ_DW(allow_other_vhca_access_in)] = {0};\n+\tvoid *key;\n+\tint ret;\n+\n+\tMLX5_SET(allow_other_vhca_access_in,\n+\t\t in, opcode, MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS);\n+\tMLX5_SET(allow_other_vhca_access_in,\n+\t\t in, object_type_to_be_accessed, attr->obj_type);\n+\tMLX5_SET(allow_other_vhca_access_in,\n+\t\t in, object_id_to_be_accessed, attr->obj_id);\n+\n+\tkey = MLX5_ADDR_OF(allow_other_vhca_access_in, in, access_key);\n+\tmemcpy(key, attr->access_key, sizeof(attr->access_key));\n+\n+\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to execute ALLOW_OTHER_VHCA_ACCESS command\");\n+\t\trte_errno = errno;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n int mlx5dr_cmd_query_caps(struct ibv_context *ctx,\n \t\t\t struct mlx5dr_cmd_query_caps *caps)\n {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nindex ab61e27fd8..ea6ced9d27 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -124,6 +124,12 @@ struct mlx5dr_cmd_sq_create_attr {\n \tuint32_t ts_format;\n };\n \n+struct mlx5dr_cmd_allow_other_vhca_access_attr {\n+\tuint16_t obj_type;\n+\tuint32_t obj_id;\n+\tuint8_t access_key[32];\n+};\n+\n struct mlx5dr_cmd_query_ft_caps {\n \tuint8_t max_level;\n \tuint8_t reparse;\n@@ -230,4 +236,7 @@ void mlx5dr_cmd_set_attr_connect_miss_tbl(struct mlx5dr_context *ctx,\n \t\t\t\t\t uint32_t fw_ft_type,\n \t\t\t\t\t enum mlx5dr_table_type type,\n \t\t\t\t\t struct mlx5dr_cmd_ft_modify_attr *ft_attr);\n+\n+int mlx5dr_cmd_allow_other_vhca_access(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5dr_cmd_allow_other_vhca_access_attr *attr);\n #endif /* MLX5DR_CMD_H_ */\n", "prefixes": [ "v2", "05/10" ] }