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GET /api/patches/121615/?format=api
{ "id": 121615, "url": "https://patches.dpdk.org/api/patches/121615/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20230105130304.537205-4-erezsh@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230105130304.537205-4-erezsh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230105130304.537205-4-erezsh@nvidia.com", "date": "2023-01-05T13:02:56", "name": "[v2,03/10] net/mlx5/hws: add PRM definitions for cross-vhca capabilities", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1f1471a5bf6991f21d8e2ac9b390bdfd3ac16323", "submitter": { "id": 2911, "url": "https://patches.dpdk.org/api/people/2911/?format=api", "name": "Erez Shitrit", "email": "erezsh@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20230105130304.537205-4-erezsh@nvidia.com/mbox/", "series": [ { "id": 26398, "url": "https://patches.dpdk.org/api/series/26398/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26398", "date": "2023-01-05T13:02:53", "name": "Support resource sharing among ibv_devices", "version": 2, "mbox": "https://patches.dpdk.org/series/26398/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/121615/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/121615/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EAF68A00C2;\n\tThu, 5 Jan 2023 14:03:56 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BAF8D42D27;\n\tThu, 5 Jan 2023 14:03:46 +0100 (CET)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam02on2070.outbound.protection.outlook.com [40.107.95.70])\n by mails.dpdk.org (Postfix) with ESMTP id 7AF3A4282D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Erez Shitrit <erezsh@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<valex@nvidia.com>, <rasland@nvidia.com>, Yevgeny Kliteynik\n <kliteyn@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "Subject": "[PATCH v2 03/10] net/mlx5/hws: add PRM definitions for cross-vhca\n capabilities", "Date": "Thu, 5 Jan 2023 15:02:56 +0200", "Message-ID": "<20230105130304.537205-4-erezsh@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20230105130304.537205-1-erezsh@nvidia.com>", "References": "<20221219082416.2223812-3-erezsh@nvidia.com>\n <20230105130304.537205-1-erezsh@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT003:EE_|DM4PR12MB6181:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9b3a298a-5c41-4fc7-0682-08daef1d465c", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n JFPs3L9VBJZ2g4M6JIZa6tTjf1Ctgn44RNmr9F/rr+/v3H9/gXu92Fd4HjgoBYELu8TLY2lUde0zyMjnRPJEUqqxy5AI7Fy/5cxEaFNt/e3IEsoqnTxQwuCP3oQ74hFhm7cbMBbQJC4qog/FmgVD+TfUrISEZn/kywQ/TlgQSkZhIA4lmVvvKWAkLLUa7V6EvFc2intX+9WTBPQtDV3/LDZx5+jzQRH9ez94ANO5cry7Uldj+tyK7I7KiHfTobq3tea0GLl6haPQe55pQzd7q4ANXiaVP4XdNIau+qPvhxvRfTJalVokplYCKzQAMqxdlUXeHBq3A6Pg9vX05zLTt9rvRJ+0lZo7iw3nwll5MMfLLt8w4rty1HUxQ8ai+BEkjB0EUp05lFAu/nKreIE9xY5GFRrP/cUMmo+g37/p3WzYX9vySr0SdXSiYI4YsBRiUVvTsZbHEGPO5SCvTVLaAI75+fzOoHLkgR0/aMjPlzCWjr9U3/dq8oBMhK8orcQiSsh7vhbj2u/RDA3nbE8seYbpsDpDuEFCt83zXSVAO7jzk7yvvTV8RJsF7yLnDXxYsNOYAt3SJ03YQAP3lIG17kLhucQcjjoGZY4BAnmhH7d5wnpEeGLfzT6c5OGikOXu4+NvK8KAz4e5z+tikqTtww2HmM2oEtMBZKcnaBvOuVoqdrXNTSMWyqrTbOARlPBKaddENlm88yjl2yWCW+GjvA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(136003)(396003)(39860400002)(376002)(451199015)(40470700004)(46966006)(36840700001)(54906003)(186003)(107886003)(1076003)(26005)(6286002)(6666004)(70206006)(478600001)(2616005)(16526019)(83380400001)(336012)(8676002)(426003)(8936002)(47076005)(5660300002)(41300700001)(4326008)(2906002)(316002)(70586007)(36860700001)(40480700001)(82740400003)(55016003)(356005)(7636003)(86362001)(40460700003)(7696005)(6916009)(36756003)(82310400005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Jan 2023 13:03:43.8153 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9b3a298a-5c41-4fc7-0682-08daef1d465c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT003.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6181", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Yevgeny Kliteynik <kliteyn@nvidia.com>\n\n\nEach new cap was defined.\n\nSigned-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>\nReviewed-by: Alex Vesker <valex@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 19 ++++++++++++++++++-\n 1 file changed, 18 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 3d9d69d9cf..dfa25c2b49 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1930,7 +1930,9 @@ struct mlx5_ifc_flow_table_prop_layout_bits {\n \tu8 metadata_reg_a_width[0x8];\n \tu8 reserved_at_60[0xa];\n \tu8 reparse[0x1];\n-\tu8 reserved_at_6b[0xd];\n+\tu8 reserved_at_6b[0x1];\n+\tu8 cross_vhca_object[0x1];\n+\tu8 reserved_at_6d[0xb];\n \tu8 log_max_ft_num[0x8];\n \tu8 reserved_at_80[0x10];\n \tu8 log_max_flow_counter[0x8];\n@@ -2084,6 +2086,19 @@ struct mlx5_ifc_flow_table_esw_cap_bits {\n \tu8 reserved_at_C00[0x7400];\n };\n \n+enum mlx5_ifc_cross_vhca_object_to_object_supported_types {\n+\tMLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR = 1 << 10,\n+\tMLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT = 1 << 11,\n+\tMLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT = 1 << 12,\n+\tMLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC = 1 << 13,\n+};\n+\n+enum mlx5_ifc_cross_vhca_allowed_objects_types {\n+\tMLX5_CROSS_VHCA_ALLOWED_OBJS_TIR = 1 << 0x8,\n+\tMLX5_CROSS_VHCA_ALLOWED_OBJS_FT = 1 << 0x9,\n+\tMLX5_CROSS_VHCA_ALLOWED_OBJS_RTC = 1 << 0xa,\n+};\n+\n /*\n * HCA Capabilities 2\n */\n@@ -3108,6 +3123,8 @@ enum {\n \tMLX5_GENERAL_OBJ_TYPE_RTC = 0x0041,\n \tMLX5_GENERAL_OBJ_TYPE_STE = 0x0042,\n \tMLX5_GENERAL_OBJ_TYPE_MODIFY_HEADER_PATTERN = 0x0043,\n+\tMLX5_GENERAL_OBJ_TYPE_FT_ALIAS = 0xff15,\n+\tMLX5_GENERAL_OBJ_TYPE_TIR_ALIAS = 0xff16,\n };\n \n struct mlx5_ifc_general_obj_in_cmd_hdr_bits {\n", "prefixes": [ "v2", "03/10" ] }