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GET /api/patches/120663/?format=api
{ "id": 120663, "url": "https://patches.dpdk.org/api/patches/120663/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221208201806.21893-26-syalavarthi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221208201806.21893-26-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221208201806.21893-26-syalavarthi@marvell.com", "date": "2022-12-08T20:17:53", "name": "[v2,25/37] ml/cnxk: enqueue a burst of inference requests", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e71a0572efb164694553b9fee135c777717b6aee", "submitter": { "id": 2480, "url": "https://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221208201806.21893-26-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26050, "url": "https://patches.dpdk.org/api/series/26050/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26050", "date": "2022-12-08T20:17:28", "name": "Implementation of ML CNXK driver", "version": 2, "mbox": "https://patches.dpdk.org/series/26050/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/120663/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/120663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1B100A0093;\n\tThu, 8 Dec 2022 21:21:38 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D784C42DC3;\n\tThu, 8 Dec 2022 21:19:34 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 7FF5B42D45\n for <dev@dpdk.org>; Thu, 8 Dec 2022 21:19:18 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2B8JkNPA006986 for <dev@dpdk.org>; Thu, 8 Dec 2022 12:19:18 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3m86usnj1h-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 08 Dec 2022 12:19:17 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 8 Dec 2022 12:19:15 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 8 Dec 2022 12:19:15 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id F0E8E3F70F7;\n Thu, 8 Dec 2022 12:18:18 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=D24L1HYc9AOcLiy/6DQcLXGzH/3/MuQtQTalBzOVzdw=;\n b=T5HDTZcGPVBOAn1xp252894hKQVThck2HdmWQRpLzXObNcBQ43xvNElwtg9UPy9L5aKn\n KZ3GBNBDk833qa9wLfg0rTmxEwb20sR65FqlpPVx6jFduiEXO+Dd4nBewnnfBkB8Uanb\n Kcy9pEUWh3VGrEP18+1H2dw7YmhuwppdNTKng0rOiPU+7EjYh2D7YaHAoltPdiHYQOG5\n HBJCZtXrYXZShvIzevuxRgQlaBWlgQNB5SJT2D0aFFfGPTXwP+BIEHrqwmRvDfuN+rWL\n tPSTpmoWh8VvboE0XqEFeNNhKSuiudvDxp3ajBxpaE5qNxANEFPz39vpAwdcHfyPwb42 vg==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v2 25/37] ml/cnxk: enqueue a burst of inference requests", "Date": "Thu, 8 Dec 2022 12:17:53 -0800", "Message-ID": "<20221208201806.21893-26-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221208201806.21893-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>\n <20221208201806.21893-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "ers6DzDskz7hhscEtv7iXsay2OrHRGku", "X-Proofpoint-ORIG-GUID": "ers6DzDskz7hhscEtv7iXsay2OrHRGku", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-12-08_11,2022-12-08_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enabled driver support to enqueue a burst of inference requests\nto ML device. Enqueue uses internal ML request structure to queue\nthe inferences and job completion through polling.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_ops.c | 96 ++++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_ops.h | 7 +++\n 2 files changed, 103 insertions(+)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 9cf3bb4a9f..6f2d1adac8 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -285,6 +285,28 @@ cn10k_ml_prep_sp_job_descriptor(struct cn10k_ml_dev *mldev, struct cn10k_ml_mode\n \t}\n }\n \n+static __rte_always_inline void\n+cn10k_ml_prep_fp_job_descriptor(struct rte_ml_dev *dev, struct cn10k_ml_req *req,\n+\t\t\t\tstruct rte_ml_op *op)\n+{\n+\tstruct cn10k_ml_dev *mldev;\n+\n+\tmldev = dev->data->dev_private;\n+\n+\treq->jd.hdr.jce.w0.u64 = 0;\n+\treq->jd.hdr.jce.w1.u64 = PLT_U64_CAST(&req->status);\n+\treq->jd.hdr.model_id = op->model_id;\n+\treq->jd.hdr.job_type = ML_CN10K_JOB_TYPE_MODEL_RUN;\n+\treq->jd.hdr.fp_flags = ML_FLAGS_POLL_COMPL;\n+\treq->jd.hdr.sp_flags = 0x0;\n+\treq->jd.hdr.result = roc_ml_addr_ap2mlip(&mldev->roc, &req->result);\n+\treq->jd.model_run.input_ddr_addr =\n+\t\tPLT_U64_CAST(roc_ml_addr_ap2mlip(&mldev->roc, op->input.addr));\n+\treq->jd.model_run.output_ddr_addr =\n+\t\tPLT_U64_CAST(roc_ml_addr_ap2mlip(&mldev->roc, op->output.addr));\n+\treq->jd.model_run.num_batches = op->nb_batches;\n+}\n+\n static int\n cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n {\n@@ -450,6 +472,8 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \n \trte_spinlock_init(&ocm->lock);\n \n+\tdev->enqueue_burst = cn10k_ml_enqueue_burst;\n+\n \tmldev->nb_models_loaded = 0;\n \tmldev->state = ML_CN10K_DEV_STATE_CONFIGURED;\n \n@@ -1379,6 +1403,78 @@ cn10k_ml_io_dequantize(struct rte_ml_dev *dev, int16_t model_id, uint16_t nb_bat\n \treturn 0;\n }\n \n+static __rte_always_inline void\n+queue_index_advance(uint64_t *index, uint64_t nb_desc)\n+{\n+\t*index = (*index + 1) % nb_desc;\n+}\n+\n+static __rte_always_inline uint64_t\n+queue_pending_count(uint64_t head, uint64_t tail, uint64_t nb_desc)\n+{\n+\treturn (nb_desc + head - tail) % nb_desc;\n+}\n+\n+static __rte_always_inline uint64_t\n+queue_free_count(uint64_t head, uint64_t tail, uint64_t nb_desc)\n+{\n+\treturn nb_desc - queue_pending_count(head, tail, nb_desc) - 1;\n+}\n+\n+__rte_hot uint16_t\n+cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op **ops,\n+\t\t uint16_t nb_ops)\n+{\n+\tstruct cn10k_ml_queue *queue;\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_req *req;\n+\tstruct cn10k_ml_qp *qp;\n+\tstruct rte_ml_op *op;\n+\n+\tuint16_t count;\n+\tuint64_t head;\n+\tbool enqueued;\n+\n+\tmldev = dev->data->dev_private;\n+\tqp = dev->data->queue_pairs[qp_id];\n+\tqueue = &qp->queue;\n+\n+\thead = queue->head;\n+\tnb_ops = PLT_MIN(nb_ops, queue_free_count(head, queue->tail, qp->nb_desc));\n+\tcount = 0;\n+\n+\tif (unlikely(nb_ops == 0))\n+\t\treturn 0;\n+\n+enqueue_req:\n+\top = ops[count];\n+\treq = &queue->reqs[head];\n+\n+\tcn10k_ml_prep_fp_job_descriptor(dev, req, op);\n+\n+\tmemset(&req->result, 0, sizeof(struct cn10k_ml_result));\n+\treq->result.user_ptr = op->user_ptr;\n+\n+\tplt_write64(ML_CN10K_POLL_JOB_START, &req->status);\n+\tenqueued = roc_ml_jcmdq_enqueue_lf(&mldev->roc, &req->jcmd);\n+\tif (unlikely(!enqueued))\n+\t\tgoto jcmdq_full;\n+\n+\treq->timeout = plt_tsc_cycles() + queue->wait_cycles;\n+\treq->op = op;\n+\n+\tqueue_index_advance(&head, qp->nb_desc);\n+\tcount++;\n+\n+\tif (count < nb_ops)\n+\t\tgoto enqueue_req;\n+\n+jcmdq_full:\n+\tqueue->head = head;\n+\n+\treturn count;\n+}\n+\n struct rte_ml_dev_ops cn10k_ml_ops = {\n \t/* Device control ops */\n \t.dev_info_get = cn10k_ml_dev_info_get,\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex 5e7e42ee88..e3f61beeab 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -28,6 +28,9 @@ struct cn10k_ml_req {\n \n \t/* Request timeout cycle */\n \tuint64_t timeout;\n+\n+\t/* ML op */\n+\tstruct rte_ml_op *op;\n } __rte_aligned(ROC_ALIGN);\n \n /* ML request queue */\n@@ -67,4 +70,8 @@ int cn10k_ml_model_unload(struct rte_ml_dev *dev, int16_t model_id);\n int cn10k_ml_model_start(struct rte_ml_dev *dev, int16_t model_id);\n int cn10k_ml_model_stop(struct rte_ml_dev *dev, int16_t model_id);\n \n+/* Fast-path ops */\n+__rte_hot uint16_t cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id,\n+\t\t\t\t\t struct rte_ml_op **ops, uint16_t nb_ops);\n+\n #endif /* _CN10K_ML_OPS_H_ */\n", "prefixes": [ "v2", "25/37" ] }