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GET /api/patches/120623/?format=api
{ "id": 120623, "url": "https://patches.dpdk.org/api/patches/120623/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221208200220.20267-17-syalavarthi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221208200220.20267-17-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221208200220.20267-17-syalavarthi@marvell.com", "date": "2022-12-08T20:01:59", "name": "[v1,16/37] ml/cnxk: add support to reserve and free OCM pages", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a77b8e22c16d138d5486c432f9dccf4fa6bb3fa5", "submitter": { "id": 2480, "url": "https://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221208200220.20267-17-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26049, "url": "https://patches.dpdk.org/api/series/26049/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26049", "date": "2022-12-08T20:01:43", "name": "Implementation of ML CNXK driver", "version": 1, "mbox": "https://patches.dpdk.org/series/26049/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/120623/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/120623/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A32A0A0093;\n\tThu, 8 Dec 2022 21:04:52 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 00FB742D97;\n\tThu, 8 Dec 2022 21:02:50 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 48AE242D40\n for <dev@dpdk.org>; Thu, 8 Dec 2022 21:02:34 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2B8JjnOG005114 for <dev@dpdk.org>; Thu, 8 Dec 2022 12:02:33 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3m86usnfsn-13\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 08 Dec 2022 12:02:33 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 8 Dec 2022 12:02:27 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 8 Dec 2022 12:02:27 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 572E63F7059;\n Thu, 8 Dec 2022 12:02:27 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=jwvsW1/kN9Xyrk3uBY6gtNNzZQhKaHyM7J+AFB2lHLo=;\n b=bX0YHtZrczBJpv0Tq5AK38kQ2TYuO6OyH9iRH7qQcrkGFIZ2NUJIuSNNN+YLkNn6VlCO\n uBh3U4UwuK+d8Rw1SInEO4DmcilJUBntOdPtr1QYbNamb2pTfeL5iEQr9UVf3teQ/nFd\n hj19JCSMIoY08Oi8w4T917IGXkBH+m01CnEgbJar9mQEdUfdXum0Z+3UNPUjshfBkOcv\n zxgHf+ImUvNdwwH9XA7nYL/6z2ezoMBkmYnK9y4CXF+1SXNGNdNhJjHXE9iwOgmOjs2/\n vYy75kYGmu7Pj0Lt/dSlJTAbJM0q0tPXQC/3TnSU/0L7STNfKA/AHgILHenxptmq+fk8 GA==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v1 16/37] ml/cnxk: add support to reserve and free OCM pages", "Date": "Thu, 8 Dec 2022 12:01:59 -0800", "Message-ID": "<20221208200220.20267-17-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221208200220.20267-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "f_NyJrDFFdH5nCGx7-LSLpznYC0rOl1H", "X-Proofpoint-ORIG-GUID": "f_NyJrDFFdH5nCGx7-LSLpznYC0rOl1H", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-12-08_11,2022-12-08_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added support to reserve and free OCM pages for a model. OCM\npages are reserved upon completion of model start and are\nreleased after model stop.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_ocm.c | 131 ++++++++++++++++++++++++++++++++-\n drivers/ml/cnxk/cn10k_ml_ocm.h | 3 +\n 2 files changed, 131 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_ocm.c b/drivers/ml/cnxk/cn10k_ml_ocm.c\nindex a465848558..ddc0936cec 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.c\n@@ -5,14 +5,17 @@\n #include <rte_mldev_pmd.h>\n \n #include \"cn10k_ml_dev.h\"\n+#include \"cn10k_ml_model.h\"\n #include \"cn10k_ml_ocm.h\"\n \n #include \"roc_api.h\"\n \n /* OCM macros */\n-#define BYTE_LEN\t 8\n-#define OCM_MAP_WORD_SIZE (sizeof(uint8_t) * BYTE_LEN)\n-#define SET_BIT(num, n)\t ((num) | (1 << (n)))\n+#define BYTE_LEN\t 8\n+#define OCM_MAP_WORD_SIZE (sizeof(uint8_t) * BYTE_LEN)\n+#define IS_BIT_SET(num, n) ((num) & (1 << (n)))\n+#define SET_BIT(num, n)\t ((num) | (1 << (n)))\n+#define CLEAR_BIT(num, n) ((num) &= ~((1) << (n)))\n \n /* Left shift multi-word mask by 1 bit.\n *\n@@ -333,3 +336,125 @@ cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t w\n \n \treturn wb_page_start;\n }\n+\n+void\n+cn10k_ml_ocm_reserve_pages(struct rte_ml_dev *dev, int16_t model_id, uint64_t tilemask,\n+\t\t\t int wb_page_start, uint16_t wb_pages, uint16_t scratch_pages)\n+{\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_ocm *ocm;\n+\n+\tint scratch_page_start;\n+\tint scratch_page_end;\n+\tint wb_page_end;\n+\tint tile_start;\n+\tint tile_end;\n+\tint tile_id;\n+\tint page_id;\n+\n+\tmldev = dev->data->dev_private;\n+\tocm = &mldev->ocm;\n+\tmodel = dev->data->models[model_id];\n+\n+\t/* Get first set bit, tile_start */\n+\ttile_start = 0;\n+\ttile_end = 0;\n+\tcn10k_ml_ocm_tilecount(tilemask, &tile_start, &tile_end);\n+\twb_page_end = wb_page_start + wb_pages - 1;\n+\tscratch_page_start = ocm->num_pages - scratch_pages;\n+\tscratch_page_end = ocm->num_pages - 1;\n+\n+\t/* Update tile_ocm_info */\n+\tfor (tile_id = tile_start; tile_id <= tile_end; tile_id++) {\n+\t\t/* Scratch pages */\n+\t\tfor (page_id = scratch_page_start; page_id <= scratch_page_end; page_id++)\n+\t\t\tocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = SET_BIT(\n+\t\t\t\tocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE],\n+\t\t\t\tpage_id % OCM_MAP_WORD_SIZE);\n+\t\tocm->tile_ocm_info[tile_id].scratch_pages =\n+\t\t\tPLT_MAX(ocm->tile_ocm_info[tile_id].scratch_pages, scratch_pages);\n+\n+\t\t/* WB pages */\n+\t\tfor (page_id = wb_page_start; page_id <= wb_page_end; page_id++)\n+\t\t\tocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] = SET_BIT(\n+\t\t\t\tocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE],\n+\t\t\t\tpage_id % OCM_MAP_WORD_SIZE);\n+\t\tif (wb_pages != 0)\n+\t\t\tocm->tile_ocm_info[tile_id].last_wb_page =\n+\t\t\t\tPLT_MAX(ocm->tile_ocm_info[tile_id].last_wb_page, wb_page_end);\n+\t}\n+\n+\tmodel->addr.tile_start = tile_start;\n+\tmodel->addr.tile_end = tile_end;\n+\n+\tplt_ml_dbg(\"model_id = %d, tilemask = 0x%016lx\", model_id, tilemask);\n+\tplt_ml_dbg(\"model_id = %d, wb_page_start = %d, wb_page_end = %d\", model_id, wb_page_start,\n+\t\t wb_page_end);\n+\tplt_ml_dbg(\"model_id = %d, scratch_page_start = %d, scratch_page_end = %d\", model_id,\n+\t\t scratch_page_start, scratch_page_end);\n+}\n+\n+void\n+cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, int16_t model_id)\n+{\n+\tstruct cn10k_ml_model *model;\n+\tstruct cn10k_ml_dev *mldev;\n+\tstruct cn10k_ml_ocm *ocm;\n+\n+\tint scratch_resize_pages;\n+\tint wb_page_start;\n+\tint wb_page_end;\n+\tint prev_start;\n+\tint curr_start;\n+\tint tile_id;\n+\tint page_id;\n+\tint16_t i;\n+\n+\tmldev = dev->data->dev_private;\n+\tocm = &mldev->ocm;\n+\tmodel = dev->data->models[model_id];\n+\n+\t/* Update OCM info for WB memory */\n+\twb_page_start = model->model_mem_map.wb_page_start;\n+\twb_page_end = wb_page_start + model->model_mem_map.wb_pages - 1;\n+\tfor (tile_id = model->addr.tile_start; tile_id <= model->addr.tile_end; tile_id++) {\n+\t\tfor (page_id = wb_page_start; page_id <= wb_page_end; page_id++) {\n+\t\t\tocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] =\n+\t\t\t\tCLEAR_BIT(ocm->tile_ocm_info[tile_id]\n+\t\t\t\t\t\t .ocm_mask[page_id / OCM_MAP_WORD_SIZE],\n+\t\t\t\t\t page_id % OCM_MAP_WORD_SIZE);\n+\t\t}\n+\n+\t\t/* Update last_wb_page size */\n+\t\tif (wb_page_end == ocm->tile_ocm_info[tile_id].last_wb_page)\n+\t\t\tocm->tile_ocm_info[tile_id].last_wb_page = wb_page_start - 1;\n+\n+\t\t/* Update scratch page size and clear extra bits */\n+\t\tscratch_resize_pages = 0;\n+\t\t/* Get max scratch pages required, excluding the current model */\n+\t\tfor (i = 0; i < dev->data->nb_models; i++) {\n+\t\t\tstruct cn10k_ml_model *model = dev->data->models[i];\n+\n+\t\t\tif ((i != model_id) && (model != NULL)) {\n+\t\t\t\tif (IS_BIT_SET(model->model_mem_map.tilemask, tile_id))\n+\t\t\t\t\tscratch_resize_pages =\n+\t\t\t\t\t\tPLT_MAX((int)model->model_mem_map.scratch_pages,\n+\t\t\t\t\t\t\tscratch_resize_pages);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Clear extra scratch pages */\n+\t\tif (scratch_resize_pages < ocm->tile_ocm_info[tile_id].scratch_pages) {\n+\t\t\tprev_start = ocm->num_pages - ocm->tile_ocm_info[tile_id].scratch_pages;\n+\t\t\tcurr_start = ocm->num_pages - scratch_resize_pages;\n+\t\t\tfor (page_id = prev_start; page_id < curr_start; page_id++) {\n+\t\t\t\tocm->tile_ocm_info[tile_id].ocm_mask[page_id / OCM_MAP_WORD_SIZE] =\n+\t\t\t\t\tCLEAR_BIT(ocm->tile_ocm_info[tile_id]\n+\t\t\t\t\t\t\t .ocm_mask[page_id / OCM_MAP_WORD_SIZE],\n+\t\t\t\t\t\t page_id % OCM_MAP_WORD_SIZE);\n+\t\t\t}\n+\t\t\tocm->tile_ocm_info[tile_id].scratch_pages = scratch_resize_pages;\n+\t\t}\n+\t}\n+}\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ocm.h b/drivers/ml/cnxk/cn10k_ml_ocm.h\nindex 2b7166bbca..7c6b1432c5 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ocm.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ocm.h\n@@ -80,5 +80,8 @@ struct cn10k_ml_ocm {\n int cn10k_ml_ocm_tilecount(uint64_t tilemask, int *start, int *end);\n int cn10k_ml_ocm_tilemask_find(struct rte_ml_dev *dev, uint8_t num_tiles, uint16_t wb_pages,\n \t\t\t uint16_t scratch_pages, uint64_t *tilemask);\n+void cn10k_ml_ocm_reserve_pages(struct rte_ml_dev *dev, int16_t model_id, uint64_t tilemask,\n+\t\t\t\tint wb_page_start, uint16_t wb_pages, uint16_t scratch_pages);\n+void cn10k_ml_ocm_free_pages(struct rte_ml_dev *dev, int16_t model_id);\n \n #endif /* _CN10K_ML_OCM_H_ */\n", "prefixes": [ "v1", "16/37" ] }