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GET /api/patches/120602/?format=api
{ "id": 120602, "url": "https://patches.dpdk.org/api/patches/120602/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221208200220.20267-3-syalavarthi@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221208200220.20267-3-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221208200220.20267-3-syalavarthi@marvell.com", "date": "2022-12-08T20:01:45", "name": "[v1,02/37] ml/cnxk: enable probe and remove of ML device", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4fc8481a90b009f55aa12d91852a9b9ffde62726", "submitter": { "id": 2480, "url": "https://patches.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221208200220.20267-3-syalavarthi@marvell.com/mbox/", "series": [ { "id": 26049, "url": "https://patches.dpdk.org/api/series/26049/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26049", "date": "2022-12-08T20:01:43", "name": "Implementation of ML CNXK driver", "version": 1, "mbox": "https://patches.dpdk.org/series/26049/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/120602/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/120602/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2811AA0093;\n\tThu, 8 Dec 2022 21:02:33 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4C3C442D23;\n\tThu, 8 Dec 2022 21:02:29 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id D2C9D410FB\n for <dev@dpdk.org>; Thu, 8 Dec 2022 21:02:26 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2B8Jja5v001963; Thu, 8 Dec 2022 12:02:26 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3mb22svpd3-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 08 Dec 2022 12:02:25 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 8 Dec 2022 12:02:24 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 8 Dec 2022 12:02:24 -0800", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id 0AB4D3F705E;\n Thu, 8 Dec 2022 12:02:24 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=o5zLGvhUfnZka0Xl5dWDOfoCB09OvUWpZXgKvXvo8FA=;\n b=c7ywoCIBb2/r6PyEE4OkP45IOL9Q5XjzShgSP1z3eU65oqEG4HcvpPEpuPP4MusoMpOX\n uUvl1j1KIp/k4Ha5E8nd5jP4+Ov8piISlDXxOQeH9IuPMbXbY/BngmelAw8wJ5ld9v2z\n jf2vACfB0MVuPptyPUsXiSsj8K6C8bM6mrd2+ezOmH3sdUGDF/GGwX5/X0Q3xWq/umXy\n vsMBOXbJm/gHGNjsTOoTkSHuqgPnPdnkOfgcnrLx0OuSo48PcS6fa3U0lh8xnOUFkEad\n phxQByDt11prUWOZVlAJ0T18AjWU0Dx6iTKDsF6qm6jLU20MSAKw4dpTW5NOaVfQAClK KA==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>, Anatoly Burakov\n <anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <jerinj@marvell.com>,\n <aprabhu@marvell.com>", "Subject": "[PATCH v1 02/37] ml/cnxk: enable probe and remove of ML device", "Date": "Thu, 8 Dec 2022 12:01:45 -0800", "Message-ID": "<20221208200220.20267-3-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221208200220.20267-1-syalavarthi@marvell.com>", "References": "<20221208200220.20267-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "GXO29EVZMivOv32g_ZZ5VT-6mf0X6UJY", "X-Proofpoint-GUID": "GXO29EVZMivOv32g_ZZ5VT-6mf0X6UJY", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-12-08_11,2022-12-08_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "ML inference engine on cn10k platform is a PCI based device. Added\ndriver support to probe and remove the device for cn10k poll mode\ndriver. The device is named by the PMD as \"ml_cn10k\".\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n drivers/ml/cnxk/cn10k_ml_dev.c | 114 +++++++++++++++++++++++++++++++++\n drivers/ml/cnxk/cn10k_ml_dev.h | 11 ++++\n drivers/ml/cnxk/cn10k_ml_ops.c | 10 +++\n drivers/ml/cnxk/cn10k_ml_ops.h | 11 ++++\n drivers/ml/cnxk/meson.build | 2 +\n 5 files changed, 148 insertions(+)\n create mode 100644 drivers/ml/cnxk/cn10k_ml_ops.c\n create mode 100644 drivers/ml/cnxk/cn10k_ml_ops.h", "diff": "diff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex cc96a7bdb3..c2e93c9a1a 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -2,7 +2,121 @@\n * Copyright (c) 2022 Marvell.\n */\n \n+#include <rte_common.h>\n+#include <rte_dev.h>\n #include <rte_mldev.h>\n #include <rte_mldev_pmd.h>\n+#include <rte_pci.h>\n+\n+#include <roc_api.h>\n \n #include \"cn10k_ml_dev.h\"\n+#include \"cn10k_ml_ops.h\"\n+\n+/* Dummy operations for ML device */\n+struct rte_ml_dev_ops ml_dev_dummy_ops = {0};\n+\n+static int\n+cn10k_ml_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_ml_dev_pmd_init_params init_params;\n+\tstruct cn10k_ml_dev *mldev;\n+\tchar name[RTE_ML_STR_MAX];\n+\tstruct rte_ml_dev *dev;\n+\tint ret;\n+\n+\tPLT_SET_USED(pci_drv);\n+\n+\tinit_params = (struct rte_ml_dev_pmd_init_params){\n+\t\t.socket_id = rte_socket_id(), .private_data_size = sizeof(struct cn10k_ml_dev)};\n+\n+\tret = roc_plt_init();\n+\tif (ret < 0) {\n+\t\tplt_err(\"Failed to initialize platform model\");\n+\t\treturn ret;\n+\t}\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\tdev = rte_ml_dev_pmd_create(name, &pci_dev->device, &init_params);\n+\tif (dev == NULL) {\n+\t\tret = -ENODEV;\n+\t\tgoto error_exit;\n+\t}\n+\n+\t/* Get private data space allocated */\n+\tmldev = dev->data->dev_private;\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\tmldev->roc.pci_dev = pci_dev;\n+\n+\t\tret = roc_ml_dev_init(&mldev->roc);\n+\t\tif (ret) {\n+\t\t\tplt_err(\"Failed to initialize ML ROC, ret = %d\", ret);\n+\t\t\tgoto pmd_destroy;\n+\t\t}\n+\n+\t\tdev->dev_ops = &cn10k_ml_ops;\n+\t} else {\n+\t\tplt_err(\"CN10K ML Ops are not supported on secondary process\");\n+\t\tdev->dev_ops = &ml_dev_dummy_ops;\n+\t}\n+\n+\tdev->enqueue_burst = NULL;\n+\tdev->dequeue_burst = NULL;\n+\tdev->op_error_get = NULL;\n+\n+\treturn 0;\n+\n+pmd_destroy:\n+\trte_ml_dev_pmd_destroy(dev);\n+\n+error_exit:\n+\tplt_err(\"Could not create device (vendor_id: 0x%x device_id: 0x%x)\", pci_dev->id.vendor_id,\n+\t\tpci_dev->id.device_id);\n+\n+\treturn ret;\n+}\n+\n+static int\n+cn10k_ml_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct cn10k_ml_dev *mldev;\n+\tchar name[RTE_ML_STR_MAX];\n+\tstruct rte_ml_dev *dev;\n+\tint ret;\n+\n+\tif (pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\n+\tdev = rte_ml_dev_pmd_get_named_dev(name);\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n+\t\tmldev = dev->data->dev_private;\n+\t\tret = roc_ml_dev_fini(&mldev->roc);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn rte_ml_dev_pmd_destroy(dev);\n+}\n+\n+static struct rte_pci_id pci_id_ml_table[] = {\n+\t{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_ML_PF)},\n+\t/* sentinel */\n+\t{},\n+};\n+\n+static struct rte_pci_driver cn10k_mldev_pmd = {\n+\t.id_table = pci_id_ml_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,\n+\t.probe = cn10k_ml_pci_probe,\n+\t.remove = cn10k_ml_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(MLDEV_NAME_CN10K_PMD, cn10k_mldev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(MLDEV_NAME_CN10K_PMD, pci_id_ml_table);\n+RTE_PMD_REGISTER_KMOD_DEP(MLDEV_NAME_CN10K_PMD, \"vfio-pci\");\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex 049ac13fcd..4827d29bf7 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -5,4 +5,15 @@\n #ifndef _CN10K_ML_DEV_H_\n #define _CN10K_ML_DEV_H_\n \n+#include <roc_api.h>\n+\n+/* Marvell OCTEON CN10K ML PMD device name */\n+#define MLDEV_NAME_CN10K_PMD ml_cn10k\n+\n+/* Device private data */\n+struct cn10k_ml_dev {\n+\t/* ML device ROC */\n+\tstruct roc_ml roc;\n+};\n+\n #endif /* _CN10K_ML_DEV_H_ */\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nnew file mode 100644\nindex 0000000000..39843e3ee5\n--- /dev/null\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#include <rte_mldev.h>\n+#include <rte_mldev_pmd.h>\n+\n+#include \"cn10k_ml_ops.h\"\n+\n+struct rte_ml_dev_ops cn10k_ml_ops = {0};\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nnew file mode 100644\nindex 0000000000..adb0035fd7\n--- /dev/null\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 Marvell.\n+ */\n+\n+#ifndef _CN10K_ML_OPS_H_\n+#define _CN10K_ML_OPS_H_\n+\n+/* CN10K device ops */\n+extern struct rte_ml_dev_ops cn10k_ml_ops;\n+\n+#endif /* _CN10K_ML_OPS_H_ */\ndiff --git a/drivers/ml/cnxk/meson.build b/drivers/ml/cnxk/meson.build\nindex f04e78cce5..bf4ccde2c5 100644\n--- a/drivers/ml/cnxk/meson.build\n+++ b/drivers/ml/cnxk/meson.build\n@@ -9,10 +9,12 @@ endif\n \n sources = files(\n 'cn10k_ml_dev.c',\n+ 'cn10k_ml_ops.c',\n )\n \n headers = files(\n 'cn10k_ml_dev.h',\n+ 'cn10k_ml_ops.h',\n )\n \n deps += ['mldev', 'common_ml', 'common_cnxk']\n", "prefixes": [ "v1", "02/37" ] }