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GET /api/patches/120566/?format=api
{ "id": 120566, "url": "https://patches.dpdk.org/api/patches/120566/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221208075309.37852-12-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221208075309.37852-12-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221208075309.37852-12-beilei.xing@intel.com", "date": "2022-12-08T07:53:05", "name": "[11/15] common/idpf: add rxq and txq struct", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "842f58d1305bb532ecc84e6249eff73306467741", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221208075309.37852-12-beilei.xing@intel.com/mbox/", "series": [ { "id": 26041, "url": "https://patches.dpdk.org/api/series/26041/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26041", "date": "2022-12-08T07:52:54", "name": "net/idpf: refactor idpf pmd", "version": 1, "mbox": "https://patches.dpdk.org/series/26041/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/120566/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/120566/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 00404A00C2;\n\tThu, 8 Dec 2022 08:54:43 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8EBDB42D4A;\n\tThu, 8 Dec 2022 08:53:46 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 5B1AB42D4F\n for <dev@dpdk.org>; Thu, 8 Dec 2022 08:53:43 +0100 (CET)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Dec 2022 23:53:42 -0800", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by fmsmga004.fm.intel.com with ESMTP; 07 Dec 2022 23:53:41 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1670486024; x=1702022024;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=glbc5PSesf8nSLWiQdh0/pha9kH66SlxjKonvTyLz3Q=;\n b=NbGu5DgXqqNhzn0L7L/LkQJzNXMGES1V2YmT63K9EgFDfYLML7VKHV6X\n ZBc+MrNrn/IfLBFbD72Pwp+VeT0T+5DEnKiXxmteaZzK2Vh9bap2jhqJU\n J4DeBzk/fibcBRdf92Ly1zQ7xRzHMC/wctRhAgdplzlZjDxSoXBaMTAP2\n XBuI/5YV8IKsU9QXyTSLGUbjoSrXZH2CpPySA1YgSQh8dKwdKgsOrsWsH\n mgAmuH8VHFl472tts7WeBRu0R1Z9Rc7wX3YOjPxXum75GZsvFD274Mw7l\n dMZ4NNmpVGyrc145/R2V/6Rmpq5zEBn7dmoHePUdLUb9dIJp3H9AQCGk+ Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10554\"; a=\"318244212\"", "E=Sophos;i=\"5.96,227,1665471600\"; d=\"scan'208\";a=\"318244212\"", "E=McAfee;i=\"6500,9779,10554\"; a=\"715499352\"", "E=Sophos;i=\"5.96,227,1665471600\"; d=\"scan'208\";a=\"715499352\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org,\n\tBeilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH 11/15] common/idpf: add rxq and txq struct", "Date": "Thu, 8 Dec 2022 07:53:05 +0000", "Message-Id": "<20221208075309.37852-12-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20221208075309.37852-1-beilei.xing@intel.com>", "References": "<20221208075309.37852-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nAdd idpf_rxq and idpf_txq structure in common module.\nMove configure rxq and txq to common module.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/idpf_common_device.h | 2 +\n drivers/common/idpf/idpf_common_rxtx.h | 112 +++++++++++++\n drivers/common/idpf/idpf_common_virtchnl.c | 160 ++++++++++++++++++\n drivers/common/idpf/idpf_common_virtchnl.h | 9 +-\n drivers/common/idpf/version.map | 3 +-\n drivers/net/idpf/idpf_ethdev.h | 2 -\n drivers/net/idpf/idpf_rxtx.h | 97 +----------\n drivers/net/idpf/idpf_vchnl.c | 184 ---------------------\n drivers/net/idpf/meson.build | 1 -\n 9 files changed, 283 insertions(+), 287 deletions(-)\n create mode 100644 drivers/common/idpf/idpf_common_rxtx.h\n delete mode 100644 drivers/net/idpf/idpf_vchnl.c", "diff": "diff --git a/drivers/common/idpf/idpf_common_device.h b/drivers/common/idpf/idpf_common_device.h\nindex 78f41554eb..c007c0b705 100644\n--- a/drivers/common/idpf/idpf_common_device.h\n+++ b/drivers/common/idpf/idpf_common_device.h\n@@ -18,8 +18,10 @@\n \n #define IDPF_DEFAULT_RXQ_NUM\t16\n #define IDPF_RX_BUFQ_PER_GRP\t2\n+#define IDPF_RXQ_PER_GRP\t1\n #define IDPF_DEFAULT_TXQ_NUM\t16\n #define IDPF_TX_COMPLQ_PER_GRP\t1\n+#define IDPF_TXQ_PER_GRP\t1\n \n #define IDPF_MAX_PKT_TYPE\t1024\n \ndiff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h\nnew file mode 100644\nindex 0000000000..a9ed31c08a\n--- /dev/null\n+++ b/drivers/common/idpf/idpf_common_rxtx.h\n@@ -0,0 +1,112 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#ifndef _IDPF_COMMON_RXTX_H_\n+#define _IDPF_COMMON_RXTX_H_\n+\n+#include <rte_mbuf_ptype.h>\n+#include <rte_mbuf_core.h>\n+\n+#include \"idpf_common_device.h\"\n+\n+struct idpf_rx_stats {\n+\tuint64_t mbuf_alloc_failed;\n+};\n+\n+struct idpf_rx_queue {\n+\tstruct idpf_adapter *adapter; /* the adapter this queue belongs to */\n+\tstruct rte_mempool *mp; /* mbuf pool to populate Rx ring */\n+\tconst struct rte_memzone *mz; /* memzone for Rx ring */\n+\tvolatile void *rx_ring;\n+\tstruct rte_mbuf **sw_ring; /* address of SW ring */\n+\tuint64_t rx_ring_phys_addr; /* Rx ring DMA address */\n+\n+\tuint16_t nb_rx_desc; /* ring length */\n+\tuint16_t rx_tail; /* current value of tail */\n+\tvolatile uint8_t *qrx_tail; /* register address of tail */\n+\tuint16_t rx_free_thresh; /* max free RX desc to hold */\n+\tuint16_t nb_rx_hold; /* number of held free RX desc */\n+\tstruct rte_mbuf *pkt_first_seg; /* first segment of current packet */\n+\tstruct rte_mbuf *pkt_last_seg; /* last segment of current packet */\n+\tstruct rte_mbuf fake_mbuf; /* dummy mbuf */\n+\n+\t/* used for VPMD */\n+\tuint16_t rxrearm_nb; /* number of remaining to be re-armed */\n+\tuint16_t rxrearm_start; /* the idx we start the re-arming from */\n+\tuint64_t mbuf_initializer; /* value to init mbufs */\n+\n+\tuint16_t rx_nb_avail;\n+\tuint16_t rx_next_avail;\n+\n+\tuint16_t port_id; /* device port ID */\n+\tuint16_t queue_id; /* Rx queue index */\n+\tuint16_t rx_buf_len; /* The packet buffer size */\n+\tuint16_t rx_hdr_len; /* The header buffer size */\n+\tuint16_t max_pkt_len; /* Maximum packet length */\n+\tuint8_t rxdid;\n+\n+\tbool q_set; /* if rx queue has been configured */\n+\tbool q_started; /* if rx queue has been started */\n+\tbool rx_deferred_start; /* don't start this queue in dev start */\n+\tconst struct idpf_rxq_ops *ops;\n+\n+\tstruct idpf_rx_stats rx_stats;\n+\n+\t/* only valid for split queue mode */\n+\tuint8_t expected_gen_id;\n+\tstruct idpf_rx_queue *bufq1;\n+\tstruct idpf_rx_queue *bufq2;\n+\n+\tuint64_t offloads;\n+\tuint32_t hw_register_set;\n+};\n+\n+struct idpf_tx_entry {\n+\tstruct rte_mbuf *mbuf;\n+\tuint16_t next_id;\n+\tuint16_t last_id;\n+};\n+\n+/* Structure associated with each TX queue. */\n+struct idpf_tx_queue {\n+\tconst struct rte_memzone *mz;\t\t/* memzone for Tx ring */\n+\tvolatile struct idpf_flex_tx_desc *tx_ring;\t/* Tx ring virtual address */\n+\tvolatile union {\n+\t\tstruct idpf_flex_tx_sched_desc *desc_ring;\n+\t\tstruct idpf_splitq_tx_compl_desc *compl_ring;\n+\t};\n+\tuint64_t tx_ring_phys_addr;\t\t/* Tx ring DMA address */\n+\tstruct idpf_tx_entry *sw_ring;\t\t/* address array of SW ring */\n+\n+\tuint16_t nb_tx_desc;\t\t/* ring length */\n+\tuint16_t tx_tail;\t\t/* current value of tail */\n+\tvolatile uint8_t *qtx_tail;\t/* register address of tail */\n+\t/* number of used desc since RS bit set */\n+\tuint16_t nb_used;\n+\tuint16_t nb_free;\n+\tuint16_t last_desc_cleaned;\t/* last desc have been cleaned*/\n+\tuint16_t free_thresh;\n+\tuint16_t rs_thresh;\n+\n+\tuint16_t port_id;\n+\tuint16_t queue_id;\n+\tuint64_t offloads;\n+\tuint16_t next_dd;\t/* next to set RS, for VPMD */\n+\tuint16_t next_rs;\t/* next to check DD, for VPMD */\n+\n+\tbool q_set;\t\t/* if tx queue has been configured */\n+\tbool q_started;\t\t/* if tx queue has been started */\n+\tbool tx_deferred_start; /* don't start this queue in dev start */\n+\tconst struct idpf_txq_ops *ops;\n+\n+\t/* only valid for split queue mode */\n+\tuint16_t sw_nb_desc;\n+\tuint16_t sw_tail;\n+\tvoid **txqs;\n+\tuint32_t tx_start_qid;\n+\tuint8_t expected_gen_id;\n+\tstruct idpf_tx_queue *complq;\n+};\n+\n+#endif /* _IDPF_COMMON_RXTX_H_ */\ndiff --git a/drivers/common/idpf/idpf_common_virtchnl.c b/drivers/common/idpf/idpf_common_virtchnl.c\nindex c5b68e8968..324214caa1 100644\n--- a/drivers/common/idpf/idpf_common_virtchnl.c\n+++ b/drivers/common/idpf/idpf_common_virtchnl.c\n@@ -805,3 +805,163 @@ idpf_vc_query_ptype_info(struct idpf_adapter *adapter)\n \trte_free(ptype_info);\n \treturn err;\n }\n+\n+#define IDPF_RX_BUF_STRIDE\t\t64\n+int\n+idpf_vc_config_rxq(struct idpf_vport *vport, struct idpf_rx_queue *rxq)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_config_rx_queues *vc_rxqs = NULL;\n+\tstruct virtchnl2_rxq_info *rxq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t num_qs;\n+\tint size, err, i;\n+\n+\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE)\n+\t\tnum_qs = IDPF_RXQ_PER_GRP;\n+\telse\n+\t\tnum_qs = IDPF_RXQ_PER_GRP + IDPF_RX_BUFQ_PER_GRP;\n+\n+\tsize = sizeof(*vc_rxqs) + (num_qs - 1) *\n+\t\tsizeof(struct virtchnl2_rxq_info);\n+\tvc_rxqs = rte_zmalloc(\"cfg_rxqs\", size, 0);\n+\tif (vc_rxqs == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate virtchnl2_config_rx_queues\");\n+\t\terr = -ENOMEM;\n+\t\treturn err;\n+\t}\n+\tvc_rxqs->vport_id = vport->vport_id;\n+\tvc_rxqs->num_qinfo = num_qs;\n+\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\trxq_info = &vc_rxqs->qinfo[0];\n+\t\trxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;\n+\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\t\trxq_info->queue_id = rxq->queue_id;\n+\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\trxq_info->data_buffer_size = rxq->rx_buf_len;\n+\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n+\n+\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M;\n+\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n+\n+\t\trxq_info->ring_len = rxq->nb_rx_desc;\n+\t} else {\n+\t\t/* Rx queue */\n+\t\trxq_info = &vc_rxqs->qinfo[0];\n+\t\trxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;\n+\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n+\t\trxq_info->queue_id = rxq->queue_id;\n+\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\trxq_info->data_buffer_size = rxq->rx_buf_len;\n+\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n+\n+\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n+\n+\t\trxq_info->ring_len = rxq->nb_rx_desc;\n+\t\trxq_info->rx_bufq1_id = rxq->bufq1->queue_id;\n+\t\trxq_info->rx_bufq2_id = rxq->bufq2->queue_id;\n+\t\trxq_info->rx_buffer_low_watermark = 64;\n+\n+\t\t/* Buffer queue */\n+\t\tfor (i = 1; i <= IDPF_RX_BUFQ_PER_GRP; i++) {\n+\t\t\tstruct idpf_rx_queue *bufq = i == 1 ? rxq->bufq1 : rxq->bufq2;\n+\t\t\trxq_info = &vc_rxqs->qinfo[i];\n+\t\t\trxq_info->dma_ring_addr = bufq->rx_ring_phys_addr;\n+\t\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n+\t\t\trxq_info->queue_id = bufq->queue_id;\n+\t\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\t\trxq_info->data_buffer_size = bufq->rx_buf_len;\n+\t\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n+\t\t\trxq_info->ring_len = bufq->nb_rx_desc;\n+\n+\t\t\trxq_info->buffer_notif_stride = IDPF_RX_BUF_STRIDE;\n+\t\t\trxq_info->rx_buffer_low_watermark = 64;\n+\t\t}\n+\t}\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL2_OP_CONFIG_RX_QUEUES;\n+\targs.in_args = (uint8_t *)vc_rxqs;\n+\targs.in_args_size = size;\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\trte_free(vc_rxqs);\n+\tif (err != 0)\n+\t\tDRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_RX_QUEUES\");\n+\n+\treturn err;\n+}\n+\n+int\n+idpf_vc_config_txq(struct idpf_vport *vport, struct idpf_tx_queue *txq)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_config_tx_queues *vc_txqs = NULL;\n+\tstruct virtchnl2_txq_info *txq_info;\n+\tstruct idpf_cmd_info args;\n+\tuint16_t num_qs;\n+\tint size, err;\n+\n+\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE)\n+\t\tnum_qs = IDPF_TXQ_PER_GRP;\n+\telse\n+\t\tnum_qs = IDPF_TXQ_PER_GRP + IDPF_TX_COMPLQ_PER_GRP;\n+\n+\tsize = sizeof(*vc_txqs) + (num_qs - 1) *\n+\t\tsizeof(struct virtchnl2_txq_info);\n+\tvc_txqs = rte_zmalloc(\"cfg_txqs\", size, 0);\n+\tif (vc_txqs == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate virtchnl2_config_tx_queues\");\n+\t\terr = -ENOMEM;\n+\t\treturn err;\n+\t}\n+\tvc_txqs->vport_id = vport->vport_id;\n+\tvc_txqs->num_qinfo = num_qs;\n+\n+\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n+\t\ttxq_info = &vc_txqs->qinfo[0];\n+\t\ttxq_info->dma_ring_addr = txq->tx_ring_phys_addr;\n+\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n+\t\ttxq_info->queue_id = txq->queue_id;\n+\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n+\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_QUEUE;\n+\t\ttxq_info->ring_len = txq->nb_tx_desc;\n+\t} else {\n+\t\t/* txq info */\n+\t\ttxq_info = &vc_txqs->qinfo[0];\n+\t\ttxq_info->dma_ring_addr = txq->tx_ring_phys_addr;\n+\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n+\t\ttxq_info->queue_id = txq->queue_id;\n+\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\t\ttxq_info->ring_len = txq->nb_tx_desc;\n+\t\ttxq_info->tx_compl_queue_id = txq->complq->queue_id;\n+\t\ttxq_info->relative_queue_id = txq_info->queue_id;\n+\n+\t\t/* tx completion queue info */\n+\t\ttxq_info = &vc_txqs->qinfo[1];\n+\t\ttxq_info->dma_ring_addr = txq->complq->tx_ring_phys_addr;\n+\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n+\t\ttxq_info->queue_id = txq->complq->queue_id;\n+\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n+\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n+\t\ttxq_info->ring_len = txq->complq->nb_tx_desc;\n+\t}\n+\n+\tmemset(&args, 0, sizeof(args));\n+\targs.ops = VIRTCHNL2_OP_CONFIG_TX_QUEUES;\n+\targs.in_args = (uint8_t *)vc_txqs;\n+\targs.in_args_size = size;\n+\targs.out_buffer = adapter->mbx_resp;\n+\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n+\n+\terr = idpf_execute_vc_cmd(adapter, &args);\n+\trte_free(vc_txqs);\n+\tif (err != 0)\n+\t\tDRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_TX_QUEUES\");\n+\n+\treturn err;\n+}\ndiff --git a/drivers/common/idpf/idpf_common_virtchnl.h b/drivers/common/idpf/idpf_common_virtchnl.h\nindex e3e0825d75..d16b6b66f4 100644\n--- a/drivers/common/idpf/idpf_common_virtchnl.h\n+++ b/drivers/common/idpf/idpf_common_virtchnl.h\n@@ -6,6 +6,7 @@\n #define _IDPF_COMMON_VIRTCHNL_H_\n \n #include <idpf_common_device.h>\n+#include <idpf_common_rxtx.h>\n \n int idpf_vc_check_api_version(struct idpf_adapter *adapter);\n int idpf_vc_get_caps(struct idpf_adapter *adapter);\n@@ -20,6 +21,8 @@ int idpf_vc_config_irq_map_unmap(struct idpf_vport *vport,\n int idpf_vc_query_ptype_info(struct idpf_adapter *adapter);\n int idpf_read_one_msg(struct idpf_adapter *adapter, uint32_t ops,\n \t\t uint16_t buf_len, uint8_t *buf);\n+int idpf_execute_vc_cmd(struct idpf_adapter *adapter,\n+\t\t\tstruct idpf_cmd_info *args);\n __rte_internal\n int idpf_switch_queue(struct idpf_vport *vport, uint16_t qid,\n \t\t bool rx, bool on);\n@@ -32,7 +35,7 @@ int idpf_vc_alloc_vectors(struct idpf_vport *vport, uint16_t num_vectors);\n __rte_internal\n int idpf_vc_dealloc_vectors(struct idpf_vport *vport);\n __rte_internal\n-int idpf_execute_vc_cmd(struct idpf_adapter *adapter,\n-\t\t\tstruct idpf_cmd_info *args);\n-\n+int idpf_vc_config_rxq(struct idpf_vport *vport, struct idpf_rx_queue *rxq);\n+__rte_internal\n+int idpf_vc_config_txq(struct idpf_vport *vport, struct idpf_tx_queue *txq);\n #endif /* _IDPF_COMMON_VIRTCHNL_H_ */\ndiff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map\nindex ca94196248..0e3ed57b88 100644\n--- a/drivers/common/idpf/version.map\n+++ b/drivers/common/idpf/version.map\n@@ -12,7 +12,8 @@ INTERNAL {\n \tidpf_vc_ena_dis_vport;\n \tidpf_vc_alloc_vectors;\n \tidpf_vc_dealloc_vectors;\n-\tidpf_execute_vc_cmd;\n+\tidpf_vc_config_rxq;\n+\tidpf_vc_config_txq;\n \tidpf_adapter_init;\n \tidpf_adapter_deinit;\n \tidpf_vport_init;\ndiff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h\nindex 130c02030b..6d4738f6fe 100644\n--- a/drivers/net/idpf/idpf_ethdev.h\n+++ b/drivers/net/idpf/idpf_ethdev.h\n@@ -23,8 +23,6 @@\n #define IDPF_MAX_VPORT_NUM\t8\n \n #define IDPF_INVALID_VPORT_IDX\t0xffff\n-#define IDPF_TXQ_PER_GRP\t1\n-#define IDPF_RXQ_PER_GRP\t1\n \n #define IDPF_DFLT_Q_VEC_NUM\t1\n \ndiff --git a/drivers/net/idpf/idpf_rxtx.h b/drivers/net/idpf/idpf_rxtx.h\nindex cac6040943..b8325f9b96 100644\n--- a/drivers/net/idpf/idpf_rxtx.h\n+++ b/drivers/net/idpf/idpf_rxtx.h\n@@ -5,6 +5,7 @@\n #ifndef _IDPF_RXTX_H_\n #define _IDPF_RXTX_H_\n \n+#include <idpf_common_rxtx.h>\n #include \"idpf_ethdev.h\"\n \n /* MTS */\n@@ -84,103 +85,10 @@\n \n extern uint64_t idpf_timestamp_dynflag;\n \n-struct idpf_rx_queue {\n-\tstruct idpf_adapter *adapter; /* the adapter this queue belongs to */\n-\tstruct rte_mempool *mp; /* mbuf pool to populate Rx ring */\n-\tconst struct rte_memzone *mz; /* memzone for Rx ring */\n-\tvolatile void *rx_ring;\n-\tstruct rte_mbuf **sw_ring; /* address of SW ring */\n-\tuint64_t rx_ring_phys_addr; /* Rx ring DMA address */\n-\n-\tuint16_t nb_rx_desc; /* ring length */\n-\tuint16_t rx_tail; /* current value of tail */\n-\tvolatile uint8_t *qrx_tail; /* register address of tail */\n-\tuint16_t rx_free_thresh; /* max free RX desc to hold */\n-\tuint16_t nb_rx_hold; /* number of held free RX desc */\n-\tstruct rte_mbuf *pkt_first_seg; /* first segment of current packet */\n-\tstruct rte_mbuf *pkt_last_seg; /* last segment of current packet */\n-\tstruct rte_mbuf fake_mbuf; /* dummy mbuf */\n-\n-\t/* used for VPMD */\n-\tuint16_t rxrearm_nb; /* number of remaining to be re-armed */\n-\tuint16_t rxrearm_start; /* the idx we start the re-arming from */\n-\tuint64_t mbuf_initializer; /* value to init mbufs */\n-\n-\tuint16_t rx_nb_avail;\n-\tuint16_t rx_next_avail;\n-\n-\tuint16_t port_id; /* device port ID */\n-\tuint16_t queue_id; /* Rx queue index */\n-\tuint16_t rx_buf_len; /* The packet buffer size */\n-\tuint16_t rx_hdr_len; /* The header buffer size */\n-\tuint16_t max_pkt_len; /* Maximum packet length */\n-\tuint8_t rxdid;\n-\n-\tbool q_set; /* if rx queue has been configured */\n-\tbool q_started; /* if rx queue has been started */\n-\tbool rx_deferred_start; /* don't start this queue in dev start */\n-\tconst struct idpf_rxq_ops *ops;\n-\n-\t/* only valid for split queue mode */\n-\tuint8_t expected_gen_id;\n-\tstruct idpf_rx_queue *bufq1;\n-\tstruct idpf_rx_queue *bufq2;\n-\n-\tuint64_t offloads;\n-\tuint32_t hw_register_set;\n-};\n-\n-struct idpf_tx_entry {\n-\tstruct rte_mbuf *mbuf;\n-\tuint16_t next_id;\n-\tuint16_t last_id;\n-};\n-\n struct idpf_tx_vec_entry {\n \tstruct rte_mbuf *mbuf;\n };\n \n-/* Structure associated with each TX queue. */\n-struct idpf_tx_queue {\n-\tconst struct rte_memzone *mz;\t\t/* memzone for Tx ring */\n-\tvolatile struct idpf_flex_tx_desc *tx_ring;\t/* Tx ring virtual address */\n-\tvolatile union {\n-\t\tstruct idpf_flex_tx_sched_desc *desc_ring;\n-\t\tstruct idpf_splitq_tx_compl_desc *compl_ring;\n-\t};\n-\tuint64_t tx_ring_phys_addr;\t\t/* Tx ring DMA address */\n-\tstruct idpf_tx_entry *sw_ring;\t\t/* address array of SW ring */\n-\n-\tuint16_t nb_tx_desc;\t\t/* ring length */\n-\tuint16_t tx_tail;\t\t/* current value of tail */\n-\tvolatile uint8_t *qtx_tail;\t/* register address of tail */\n-\t/* number of used desc since RS bit set */\n-\tuint16_t nb_used;\n-\tuint16_t nb_free;\n-\tuint16_t last_desc_cleaned;\t/* last desc have been cleaned*/\n-\tuint16_t free_thresh;\n-\tuint16_t rs_thresh;\n-\n-\tuint16_t port_id;\n-\tuint16_t queue_id;\n-\tuint64_t offloads;\n-\tuint16_t next_dd;\t/* next to set RS, for VPMD */\n-\tuint16_t next_rs;\t/* next to check DD, for VPMD */\n-\n-\tbool q_set;\t\t/* if tx queue has been configured */\n-\tbool q_started;\t\t/* if tx queue has been started */\n-\tbool tx_deferred_start; /* don't start this queue in dev start */\n-\tconst struct idpf_txq_ops *ops;\n-\n-\t/* only valid for split queue mode */\n-\tuint16_t sw_nb_desc;\n-\tuint16_t sw_tail;\n-\tvoid **txqs;\n-\tuint32_t tx_start_qid;\n-\tuint8_t expected_gen_id;\n-\tstruct idpf_tx_queue *complq;\n-};\n-\n /* Offload features */\n union idpf_tx_offload {\n \tuint64_t data;\n@@ -239,9 +147,6 @@ void idpf_stop_queues(struct rte_eth_dev *dev);\n void idpf_set_rx_function(struct rte_eth_dev *dev);\n void idpf_set_tx_function(struct rte_eth_dev *dev);\n \n-int idpf_vc_config_rxq(struct idpf_vport *vport, struct idpf_rx_queue *rxq);\n-int idpf_vc_config_txq(struct idpf_vport *vport, struct idpf_tx_queue *txq);\n-\n #define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000\n /* Helper function to convert a 32b nanoseconds timestamp to 64b. */\n static inline uint64_t\ndiff --git a/drivers/net/idpf/idpf_vchnl.c b/drivers/net/idpf/idpf_vchnl.c\ndeleted file mode 100644\nindex 45d05ed108..0000000000\n--- a/drivers/net/idpf/idpf_vchnl.c\n+++ /dev/null\n@@ -1,184 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2022 Intel Corporation\n- */\n-\n-#include <stdio.h>\n-#include <errno.h>\n-#include <stdint.h>\n-#include <string.h>\n-#include <unistd.h>\n-#include <stdarg.h>\n-#include <inttypes.h>\n-#include <rte_byteorder.h>\n-#include <rte_common.h>\n-\n-#include <rte_debug.h>\n-#include <rte_atomic.h>\n-#include <rte_eal.h>\n-#include <rte_ether.h>\n-#include <ethdev_driver.h>\n-#include <ethdev_pci.h>\n-#include <rte_dev.h>\n-\n-#include \"idpf_ethdev.h\"\n-#include \"idpf_rxtx.h\"\n-\n-#define IDPF_RX_BUF_STRIDE\t\t64\n-int\n-idpf_vc_config_rxq(struct idpf_vport *vport, struct idpf_rx_queue *rxq)\n-{\n-\tstruct idpf_adapter *adapter = vport->adapter;\n-\tstruct virtchnl2_config_rx_queues *vc_rxqs = NULL;\n-\tstruct virtchnl2_rxq_info *rxq_info;\n-\tstruct idpf_cmd_info args;\n-\tuint16_t num_qs;\n-\tint size, err, i;\n-\n-\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE)\n-\t\tnum_qs = IDPF_RXQ_PER_GRP;\n-\telse\n-\t\tnum_qs = IDPF_RXQ_PER_GRP + IDPF_RX_BUFQ_PER_GRP;\n-\n-\tsize = sizeof(*vc_rxqs) + (num_qs - 1) *\n-\t\tsizeof(struct virtchnl2_rxq_info);\n-\tvc_rxqs = rte_zmalloc(\"cfg_rxqs\", size, 0);\n-\tif (vc_rxqs == NULL) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_rx_queues\");\n-\t\terr = -ENOMEM;\n-\t\treturn err;\n-\t}\n-\tvc_rxqs->vport_id = vport->vport_id;\n-\tvc_rxqs->num_qinfo = num_qs;\n-\tif (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n-\t\trxq_info = &vc_rxqs->qinfo[0];\n-\t\trxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;\n-\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n-\t\trxq_info->queue_id = rxq->queue_id;\n-\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n-\t\trxq_info->data_buffer_size = rxq->rx_buf_len;\n-\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n-\n-\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SQ_NIC_M;\n-\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n-\n-\t\trxq_info->ring_len = rxq->nb_rx_desc;\n-\t} else {\n-\t\t/* Rx queue */\n-\t\trxq_info = &vc_rxqs->qinfo[0];\n-\t\trxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;\n-\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX;\n-\t\trxq_info->queue_id = rxq->queue_id;\n-\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n-\t\trxq_info->data_buffer_size = rxq->rx_buf_len;\n-\t\trxq_info->max_pkt_size = vport->max_pkt_len;\n-\n-\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n-\t\trxq_info->qflags |= VIRTCHNL2_RX_DESC_SIZE_32BYTE;\n-\n-\t\trxq_info->ring_len = rxq->nb_rx_desc;\n-\t\trxq_info->rx_bufq1_id = rxq->bufq1->queue_id;\n-\t\trxq_info->rx_bufq2_id = rxq->bufq2->queue_id;\n-\t\trxq_info->rx_buffer_low_watermark = 64;\n-\n-\t\t/* Buffer queue */\n-\t\tfor (i = 1; i <= IDPF_RX_BUFQ_PER_GRP; i++) {\n-\t\t\tstruct idpf_rx_queue *bufq = i == 1 ? rxq->bufq1 : rxq->bufq2;\n-\t\t\trxq_info = &vc_rxqs->qinfo[i];\n-\t\t\trxq_info->dma_ring_addr = bufq->rx_ring_phys_addr;\n-\t\t\trxq_info->type = VIRTCHNL2_QUEUE_TYPE_RX_BUFFER;\n-\t\t\trxq_info->queue_id = bufq->queue_id;\n-\t\t\trxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n-\t\t\trxq_info->data_buffer_size = bufq->rx_buf_len;\n-\t\t\trxq_info->desc_ids = VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M;\n-\t\t\trxq_info->ring_len = bufq->nb_rx_desc;\n-\n-\t\t\trxq_info->buffer_notif_stride = IDPF_RX_BUF_STRIDE;\n-\t\t\trxq_info->rx_buffer_low_watermark = 64;\n-\t\t}\n-\t}\n-\n-\tmemset(&args, 0, sizeof(args));\n-\targs.ops = VIRTCHNL2_OP_CONFIG_RX_QUEUES;\n-\targs.in_args = (uint8_t *)vc_rxqs;\n-\targs.in_args_size = size;\n-\targs.out_buffer = adapter->mbx_resp;\n-\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n-\n-\terr = idpf_execute_vc_cmd(adapter, &args);\n-\trte_free(vc_rxqs);\n-\tif (err != 0)\n-\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_RX_QUEUES\");\n-\n-\treturn err;\n-}\n-\n-int\n-idpf_vc_config_txq(struct idpf_vport *vport, struct idpf_tx_queue *txq)\n-{\n-\tstruct idpf_adapter *adapter = vport->adapter;\n-\tstruct virtchnl2_config_tx_queues *vc_txqs = NULL;\n-\tstruct virtchnl2_txq_info *txq_info;\n-\tstruct idpf_cmd_info args;\n-\tuint16_t num_qs;\n-\tint size, err;\n-\n-\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE)\n-\t\tnum_qs = IDPF_TXQ_PER_GRP;\n-\telse\n-\t\tnum_qs = IDPF_TXQ_PER_GRP + IDPF_TX_COMPLQ_PER_GRP;\n-\n-\tsize = sizeof(*vc_txqs) + (num_qs - 1) *\n-\t\tsizeof(struct virtchnl2_txq_info);\n-\tvc_txqs = rte_zmalloc(\"cfg_txqs\", size, 0);\n-\tif (vc_txqs == NULL) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to allocate virtchnl2_config_tx_queues\");\n-\t\terr = -ENOMEM;\n-\t\treturn err;\n-\t}\n-\tvc_txqs->vport_id = vport->vport_id;\n-\tvc_txqs->num_qinfo = num_qs;\n-\n-\tif (vport->txq_model == VIRTCHNL2_QUEUE_MODEL_SINGLE) {\n-\t\ttxq_info = &vc_txqs->qinfo[0];\n-\t\ttxq_info->dma_ring_addr = txq->tx_ring_phys_addr;\n-\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n-\t\ttxq_info->queue_id = txq->queue_id;\n-\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SINGLE;\n-\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_QUEUE;\n-\t\ttxq_info->ring_len = txq->nb_tx_desc;\n-\t} else {\n-\t\t/* txq info */\n-\t\ttxq_info = &vc_txqs->qinfo[0];\n-\t\ttxq_info->dma_ring_addr = txq->tx_ring_phys_addr;\n-\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX;\n-\t\ttxq_info->queue_id = txq->queue_id;\n-\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n-\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n-\t\ttxq_info->ring_len = txq->nb_tx_desc;\n-\t\ttxq_info->tx_compl_queue_id = txq->complq->queue_id;\n-\t\ttxq_info->relative_queue_id = txq_info->queue_id;\n-\n-\t\t/* tx completion queue info */\n-\t\ttxq_info = &vc_txqs->qinfo[1];\n-\t\ttxq_info->dma_ring_addr = txq->complq->tx_ring_phys_addr;\n-\t\ttxq_info->type = VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION;\n-\t\ttxq_info->queue_id = txq->complq->queue_id;\n-\t\ttxq_info->model = VIRTCHNL2_QUEUE_MODEL_SPLIT;\n-\t\ttxq_info->sched_mode = VIRTCHNL2_TXQ_SCHED_MODE_FLOW;\n-\t\ttxq_info->ring_len = txq->complq->nb_tx_desc;\n-\t}\n-\n-\tmemset(&args, 0, sizeof(args));\n-\targs.ops = VIRTCHNL2_OP_CONFIG_TX_QUEUES;\n-\targs.in_args = (uint8_t *)vc_txqs;\n-\targs.in_args_size = size;\n-\targs.out_buffer = adapter->mbx_resp;\n-\targs.out_size = IDPF_DFLT_MBX_BUF_SIZE;\n-\n-\terr = idpf_execute_vc_cmd(adapter, &args);\n-\trte_free(vc_txqs);\n-\tif (err != 0)\n-\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of VIRTCHNL2_OP_CONFIG_TX_QUEUES\");\n-\n-\treturn err;\n-}\ndiff --git a/drivers/net/idpf/meson.build b/drivers/net/idpf/meson.build\nindex 998afd21fe..6d98b80ad3 100644\n--- a/drivers/net/idpf/meson.build\n+++ b/drivers/net/idpf/meson.build\n@@ -12,7 +12,6 @@ deps += ['common_idpf']\n sources = files(\n 'idpf_ethdev.c',\n 'idpf_rxtx.c',\n- 'idpf_vchnl.c',\n )\n \n if arch_subdir == 'x86'\n", "prefixes": [ "11/15" ] }