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GET /api/patches/120562/?format=api
{ "id": 120562, "url": "https://patches.dpdk.org/api/patches/120562/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221208075309.37852-8-beilei.xing@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221208075309.37852-8-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221208075309.37852-8-beilei.xing@intel.com", "date": "2022-12-08T07:53:01", "name": "[07/15] common/idpf: add irq map/unmap", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "45ad06a2b28e40d0643e9d0fb2d42ee0645e2287", "submitter": { "id": 410, "url": "https://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221208075309.37852-8-beilei.xing@intel.com/mbox/", "series": [ { "id": 26041, "url": "https://patches.dpdk.org/api/series/26041/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=26041", "date": "2022-12-08T07:52:54", "name": "net/idpf: refactor idpf pmd", "version": 1, "mbox": "https://patches.dpdk.org/series/26041/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/120562/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/120562/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 96AE0A00C2;\n\tThu, 8 Dec 2022 08:54:16 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 68EA742D53;\n\tThu, 8 Dec 2022 08:53:38 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id E3DF342D43\n for <dev@dpdk.org>; Thu, 8 Dec 2022 08:53:36 +0100 (CET)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Dec 2022 23:53:36 -0800", "from dpdk-beileix-3.sh.intel.com ([10.67.110.253])\n by fmsmga004.fm.intel.com with ESMTP; 07 Dec 2022 23:53:34 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1670486017; x=1702022017;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=ntmOUX+TqX5KBAdqvXH8BNvdmtK4J0PwtMeaWpJlWbk=;\n b=Q0QlBTn/+Gs8pwmxvEsGiuxSo1ce1nQQe6t0B99/9rnimQBSMyroyIwt\n XRSi/BsdnwlSqdeMRHd9ktrHrenztmoT9HkCWhMUWvZuGLVMJTQEXvnpi\n 5XQB8vw/o/rezIMGqkRi4g9q0pTFriWIohVLTeTX4jWNGpbIhbbqFvLiu\n 9n5bL5jtipE+OvCUBpCQodUMsLPyrurkc9kR341CRZIDrkcWtBDDx7EbV\n iyt+EeYaYNHxSklki7Lh0N2voL3LHJx4wIsvlHFKaBVlUpgYVp2ni3FOR\n NR0+yfF0gaUraPiTqvavG/jgJQr8K4hFL+sfD1rI7A/3tkZd8daA9C2f7 g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10554\"; a=\"318244185\"", "E=Sophos;i=\"5.96,227,1665471600\"; d=\"scan'208\";a=\"318244185\"", "E=McAfee;i=\"6500,9779,10554\"; a=\"715499317\"", "E=Sophos;i=\"5.96,227,1665471600\"; d=\"scan'208\";a=\"715499317\"" ], "X-ExtLoop1": "1", "From": "beilei.xing@intel.com", "To": "jingjing.wu@intel.com,\n\tqi.z.zhang@intel.com", "Cc": "dev@dpdk.org,\n\tBeilei Xing <beilei.xing@intel.com>", "Subject": "[PATCH 07/15] common/idpf: add irq map/unmap", "Date": "Thu, 8 Dec 2022 07:53:01 +0000", "Message-Id": "<20221208075309.37852-8-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20221208075309.37852-1-beilei.xing@intel.com>", "References": "<20221208075309.37852-1-beilei.xing@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nAdd irq map/unmap functions in common module.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/common/idpf/idpf_common_device.c | 110 +++++++++++++++++++++\n drivers/common/idpf/idpf_common_device.h | 6 ++\n drivers/common/idpf/idpf_common_virtchnl.c | 8 --\n drivers/common/idpf/idpf_common_virtchnl.h | 5 +-\n drivers/common/idpf/version.map | 3 +-\n drivers/net/idpf/idpf_ethdev.c | 90 +----------------\n drivers/net/idpf/idpf_ethdev.h | 1 -\n 7 files changed, 124 insertions(+), 99 deletions(-)", "diff": "diff --git a/drivers/common/idpf/idpf_common_device.c b/drivers/common/idpf/idpf_common_device.c\nindex 19d638824d..58a7f4cee3 100644\n--- a/drivers/common/idpf/idpf_common_device.c\n+++ b/drivers/common/idpf/idpf_common_device.c\n@@ -254,8 +254,21 @@ idpf_vport_init(struct idpf_vport *vport,\n \t\tgoto err_rss_lut;\n \t}\n \n+\t/* recv_vectors is used for VIRTCHNL2_OP_ALLOC_VECTORS response,\n+\t * reserve maximum size for it now, may need optimization in future.\n+\t */\n+\tvport->recv_vectors = rte_zmalloc(\"recv_vectors\", IDPF_DFLT_MBX_BUF_SIZE, 0);\n+\tif (vport->recv_vectors == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate ecv_vectors\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_recv_vec;\n+\t}\n+\n \treturn 0;\n \n+err_recv_vec:\n+\trte_free(vport->rss_lut);\n+\tvport->rss_lut = NULL;\n err_rss_lut:\n \tvport->dev_data = NULL;\n \trte_free(vport->rss_key);\n@@ -271,6 +284,8 @@ idpf_vport_init(struct idpf_vport *vport,\n int\n idpf_vport_deinit(struct idpf_vport *vport)\n {\n+\trte_free(vport->recv_vectors);\n+\tvport->recv_vectors = NULL;\n \trte_free(vport->rss_lut);\n \tvport->rss_lut = NULL;\n \n@@ -311,4 +326,99 @@ idpf_config_rss(struct idpf_vport *vport)\n \n \treturn ret;\n }\n+\n+int\n+idpf_config_irq_map(struct idpf_vport *vport, uint16_t nb_rx_queues)\n+{\n+\tstruct idpf_adapter *adapter = vport->adapter;\n+\tstruct virtchnl2_queue_vector *qv_map;\n+\tstruct idpf_hw *hw = &adapter->hw;\n+\tuint32_t dynctl_val, itrn_val;\n+\tuint32_t dynctl_reg_start;\n+\tuint32_t itrn_reg_start;\n+\tuint16_t i;\n+\n+\tqv_map = rte_zmalloc(\"qv_map\",\n+\t\t\t nb_rx_queues *\n+\t\t\t sizeof(struct virtchnl2_queue_vector), 0);\n+\tif (qv_map == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate %d queue-vector map\",\n+\t\t\tnb_rx_queues);\n+\t\tgoto qv_map_alloc_err;\n+\t}\n+\n+\t/* Rx interrupt disabled, Map interrupt only for writeback */\n+\n+\t/* The capability flags adapter->caps.other_caps should be\n+\t * compared with bit VIRTCHNL2_CAP_WB_ON_ITR here. The if\n+\t * condition should be updated when the FW can return the\n+\t * correct flag bits.\n+\t */\n+\tdynctl_reg_start =\n+\t\tvport->recv_vectors->vchunks.vchunks->dynctl_reg_start;\n+\titrn_reg_start =\n+\t\tvport->recv_vectors->vchunks.vchunks->itrn_reg_start;\n+\tdynctl_val = IDPF_READ_REG(hw, dynctl_reg_start);\n+\tDRV_LOG(DEBUG, \"Value of dynctl_reg_start is 0x%x\",\n+\t\tdynctl_val);\n+\titrn_val = IDPF_READ_REG(hw, itrn_reg_start);\n+\tDRV_LOG(DEBUG, \"Value of itrn_reg_start is 0x%x\", itrn_val);\n+\t/* Force write-backs by setting WB_ON_ITR bit in DYN_CTL\n+\t * register. WB_ON_ITR and INTENA are mutually exclusive\n+\t * bits. Setting WB_ON_ITR bits means TX and RX Descs\n+\t * are written back based on ITR expiration irrespective\n+\t * of INTENA setting.\n+\t */\n+\t/* TBD: need to tune INTERVAL value for better performance. */\n+\tif (itrn_val != 0)\n+\t\tIDPF_WRITE_REG(hw,\n+\t\t\t dynctl_reg_start,\n+\t\t\t VIRTCHNL2_ITR_IDX_0 <<\n+\t\t\t PF_GLINT_DYN_CTL_ITR_INDX_S |\n+\t\t\t PF_GLINT_DYN_CTL_WB_ON_ITR_M |\n+\t\t\t itrn_val <<\n+\t\t\t PF_GLINT_DYN_CTL_INTERVAL_S);\n+\telse\n+\t\tIDPF_WRITE_REG(hw,\n+\t\t\t dynctl_reg_start,\n+\t\t\t VIRTCHNL2_ITR_IDX_0 <<\n+\t\t\t PF_GLINT_DYN_CTL_ITR_INDX_S |\n+\t\t\t PF_GLINT_DYN_CTL_WB_ON_ITR_M |\n+\t\t\t IDPF_DFLT_INTERVAL <<\n+\t\t\t PF_GLINT_DYN_CTL_INTERVAL_S);\n+\n+\tfor (i = 0; i < nb_rx_queues; i++) {\n+\t\t/* map all queues to the same vector */\n+\t\tqv_map[i].queue_id = vport->chunks_info.rx_start_qid + i;\n+\t\tqv_map[i].vector_id =\n+\t\t\tvport->recv_vectors->vchunks.vchunks->start_vector_id;\n+\t}\n+\tvport->qv_map = qv_map;\n+\n+\tif (idpf_vc_config_irq_map_unmap(vport, nb_rx_queues, true) != 0) {\n+\t\tDRV_LOG(ERR, \"config interrupt mapping failed\");\n+\t\tgoto config_irq_map_err;\n+\t}\n+\n+\treturn 0;\n+\n+config_irq_map_err:\n+\trte_free(vport->qv_map);\n+\tvport->qv_map = NULL;\n+\n+qv_map_alloc_err:\n+\treturn -1;\n+}\n+\n+int\n+idpf_config_irq_unmap(struct idpf_vport *vport, uint16_t nb_rx_queues)\n+{\n+\tidpf_vc_config_irq_map_unmap(vport, nb_rx_queues, false);\n+\n+\trte_free(vport->qv_map);\n+\tvport->qv_map = NULL;\n+\n+\treturn 0;\n+}\n+\n RTE_LOG_REGISTER_SUFFIX(idpf_common_logtype, common, NOTICE);\ndiff --git a/drivers/common/idpf/idpf_common_device.h b/drivers/common/idpf/idpf_common_device.h\nindex 026d852de4..43d0380395 100644\n--- a/drivers/common/idpf/idpf_common_device.h\n+++ b/drivers/common/idpf/idpf_common_device.h\n@@ -17,6 +17,8 @@\n \n #define IDPF_MAX_PKT_TYPE\t1024\n \n+#define IDPF_DFLT_INTERVAL\t16\n+\n struct idpf_adapter {\n \tstruct idpf_hw hw;\n \tstruct virtchnl2_version_info virtchnl_version;\n@@ -152,5 +154,9 @@ __rte_internal\n int idpf_vport_deinit(struct idpf_vport *vport);\n __rte_internal\n int idpf_config_rss(struct idpf_vport *vport);\n+__rte_internal\n+int idpf_config_irq_map(struct idpf_vport *vport, uint16_t nb_rx_queues);\n+__rte_internal\n+int idpf_config_irq_unmap(struct idpf_vport *vport, uint16_t nb_rx_queues);\n \n #endif /* _IDPF_COMMON_DEVICE_H_ */\ndiff --git a/drivers/common/idpf/idpf_common_virtchnl.c b/drivers/common/idpf/idpf_common_virtchnl.c\nindex e7ba32c532..c5b68e8968 100644\n--- a/drivers/common/idpf/idpf_common_virtchnl.c\n+++ b/drivers/common/idpf/idpf_common_virtchnl.c\n@@ -573,14 +573,6 @@ idpf_vc_alloc_vectors(struct idpf_vport *vport, uint16_t num_vectors)\n \tif (err != 0)\n \t\tDRV_LOG(ERR, \"Failed to execute command VIRTCHNL2_OP_ALLOC_VECTORS\");\n \n-\tif (vport->recv_vectors == NULL) {\n-\t\tvport->recv_vectors = rte_zmalloc(\"recv_vectors\", len, 0);\n-\t\tif (vport->recv_vectors == NULL) {\n-\t\t\trte_free(alloc_vec);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\n \trte_memcpy(vport->recv_vectors, args.out_buffer, len);\n \trte_free(alloc_vec);\n \treturn err;\ndiff --git a/drivers/common/idpf/idpf_common_virtchnl.h b/drivers/common/idpf/idpf_common_virtchnl.h\nindex 182a6a4490..035be095e5 100644\n--- a/drivers/common/idpf/idpf_common_virtchnl.h\n+++ b/drivers/common/idpf/idpf_common_virtchnl.h\n@@ -15,6 +15,8 @@ int idpf_vc_destroy_vport(struct idpf_vport *vport);\n int idpf_vc_set_rss_key(struct idpf_vport *vport);\n int idpf_vc_set_rss_lut(struct idpf_vport *vport);\n int idpf_vc_set_rss_hash(struct idpf_vport *vport);\n+int idpf_vc_config_irq_map_unmap(struct idpf_vport *vport,\n+\t\t\t\t uint16_t nb_rxq, bool map);\n __rte_internal\n int idpf_switch_queue(struct idpf_vport *vport, uint16_t qid,\n \t\t bool rx, bool on);\n@@ -23,9 +25,6 @@ int idpf_vc_ena_dis_queues(struct idpf_vport *vport, bool enable);\n __rte_internal\n int idpf_vc_ena_dis_vport(struct idpf_vport *vport, bool enable);\n __rte_internal\n-int idpf_vc_config_irq_map_unmap(struct idpf_vport *vport,\n-\t\t\t\t uint16_t nb_rxq, bool map);\n-__rte_internal\n int idpf_vc_alloc_vectors(struct idpf_vport *vport, uint16_t num_vectors);\n __rte_internal\n int idpf_vc_dealloc_vectors(struct idpf_vport *vport);\ndiff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map\nindex 62ea6579e3..3b3b8c2d19 100644\n--- a/drivers/common/idpf/version.map\n+++ b/drivers/common/idpf/version.map\n@@ -10,7 +10,6 @@ INTERNAL {\n \tidpf_switch_queue;\n \tidpf_vc_ena_dis_queues;\n \tidpf_vc_ena_dis_vport;\n-\tidpf_vc_config_irq_map_unmap;\n \tidpf_vc_alloc_vectors;\n \tidpf_vc_dealloc_vectors;\n \tidpf_vc_query_ptype_info;\n@@ -21,6 +20,8 @@ INTERNAL {\n \tidpf_vport_init;\n \tidpf_vport_deinit;\n \tidpf_config_rss;\n+\tidpf_config_irq_map;\n+\tidpf_config_irq_unmap;\n \n \tlocal: *;\n };\ndiff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c\nindex ca920bef85..15a71c6efa 100644\n--- a/drivers/net/idpf/idpf_ethdev.c\n+++ b/drivers/net/idpf/idpf_ethdev.c\n@@ -268,84 +268,9 @@ static int\n idpf_config_rx_queues_irqs(struct rte_eth_dev *dev)\n {\n \tstruct idpf_vport *vport = dev->data->dev_private;\n-\tstruct idpf_adapter *adapter = vport->adapter;\n-\tstruct virtchnl2_queue_vector *qv_map;\n-\tstruct idpf_hw *hw = &adapter->hw;\n-\tuint32_t dynctl_reg_start;\n-\tuint32_t itrn_reg_start;\n-\tuint32_t dynctl_val, itrn_val;\n-\tuint16_t i;\n-\n-\tqv_map = rte_zmalloc(\"qv_map\",\n-\t\t\tdev->data->nb_rx_queues *\n-\t\t\tsizeof(struct virtchnl2_queue_vector), 0);\n-\tif (qv_map == NULL) {\n-\t\tPMD_DRV_LOG(ERR, \"Failed to allocate %d queue-vector map\",\n-\t\t\t dev->data->nb_rx_queues);\n-\t\tgoto qv_map_alloc_err;\n-\t}\n-\n-\t/* Rx interrupt disabled, Map interrupt only for writeback */\n-\n-\t/* The capability flags adapter->caps.other_caps should be\n-\t * compared with bit VIRTCHNL2_CAP_WB_ON_ITR here. The if\n-\t * condition should be updated when the FW can return the\n-\t * correct flag bits.\n-\t */\n-\tdynctl_reg_start =\n-\t\tvport->recv_vectors->vchunks.vchunks->dynctl_reg_start;\n-\titrn_reg_start =\n-\t\tvport->recv_vectors->vchunks.vchunks->itrn_reg_start;\n-\tdynctl_val = IDPF_READ_REG(hw, dynctl_reg_start);\n-\tPMD_DRV_LOG(DEBUG, \"Value of dynctl_reg_start is 0x%x\",\n-\t\t dynctl_val);\n-\titrn_val = IDPF_READ_REG(hw, itrn_reg_start);\n-\tPMD_DRV_LOG(DEBUG, \"Value of itrn_reg_start is 0x%x\", itrn_val);\n-\t/* Force write-backs by setting WB_ON_ITR bit in DYN_CTL\n-\t * register. WB_ON_ITR and INTENA are mutually exclusive\n-\t * bits. Setting WB_ON_ITR bits means TX and RX Descs\n-\t * are written back based on ITR expiration irrespective\n-\t * of INTENA setting.\n-\t */\n-\t/* TBD: need to tune INTERVAL value for better performance. */\n-\tif (itrn_val != 0)\n-\t\tIDPF_WRITE_REG(hw,\n-\t\t\t dynctl_reg_start,\n-\t\t\t VIRTCHNL2_ITR_IDX_0 <<\n-\t\t\t PF_GLINT_DYN_CTL_ITR_INDX_S |\n-\t\t\t PF_GLINT_DYN_CTL_WB_ON_ITR_M |\n-\t\t\t itrn_val <<\n-\t\t\t PF_GLINT_DYN_CTL_INTERVAL_S);\n-\telse\n-\t\tIDPF_WRITE_REG(hw,\n-\t\t\t dynctl_reg_start,\n-\t\t\t VIRTCHNL2_ITR_IDX_0 <<\n-\t\t\t PF_GLINT_DYN_CTL_ITR_INDX_S |\n-\t\t\t PF_GLINT_DYN_CTL_WB_ON_ITR_M |\n-\t\t\t IDPF_DFLT_INTERVAL <<\n-\t\t\t PF_GLINT_DYN_CTL_INTERVAL_S);\n-\n-\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\t/* map all queues to the same vector */\n-\t\tqv_map[i].queue_id = vport->chunks_info.rx_start_qid + i;\n-\t\tqv_map[i].vector_id =\n-\t\t\tvport->recv_vectors->vchunks.vchunks->start_vector_id;\n-\t}\n-\tvport->qv_map = qv_map;\n+\tuint16_t nb_rx_queues = dev->data->nb_rx_queues;\n \n-\tif (idpf_vc_config_irq_map_unmap(vport, dev->data->nb_rx_queues, true) != 0) {\n-\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping failed\");\n-\t\tgoto config_irq_map_err;\n-\t}\n-\n-\treturn 0;\n-\n-config_irq_map_err:\n-\trte_free(vport->qv_map);\n-\tvport->qv_map = NULL;\n-\n-qv_map_alloc_err:\n-\treturn -1;\n+\treturn idpf_config_irq_map(vport, nb_rx_queues);\n }\n \n static int\n@@ -457,10 +382,9 @@ idpf_dev_stop(struct rte_eth_dev *dev)\n \n \tidpf_stop_queues(dev);\n \n-\tidpf_vc_config_irq_map_unmap(vport, dev->data->nb_rx_queues, false);\n+\tidpf_config_irq_unmap(vport, dev->data->nb_rx_queues);\n \n-\tif (vport->recv_vectors != NULL)\n-\t\tidpf_vc_dealloc_vectors(vport);\n+\tidpf_vc_dealloc_vectors(vport);\n \n \tvport->stopped = 1;\n \n@@ -477,12 +401,6 @@ idpf_dev_close(struct rte_eth_dev *dev)\n \n \tidpf_vport_deinit(vport);\n \n-\trte_free(vport->recv_vectors);\n-\tvport->recv_vectors = NULL;\n-\n-\trte_free(vport->qv_map);\n-\tvport->qv_map = NULL;\n-\n \tadapter->cur_vports &= ~RTE_BIT32(vport->devarg_id);\n \tadapter->cur_vport_nb--;\n \tdev->data->dev_private = NULL;\ndiff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h\nindex bfede6f4e3..7ee99b5585 100644\n--- a/drivers/net/idpf/idpf_ethdev.h\n+++ b/drivers/net/idpf/idpf_ethdev.h\n@@ -32,7 +32,6 @@\n #define IDPF_RX_BUFQ_PER_GRP\t2\n \n #define IDPF_DFLT_Q_VEC_NUM\t1\n-#define IDPF_DFLT_INTERVAL\t16\n \n #define IDPF_MIN_BUF_SIZE\t1024\n #define IDPF_MAX_FRAME_SIZE\t9728\n", "prefixes": [ "07/15" ] }