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GET /api/patches/119369/?format=api
{ "id": 119369, "url": "https://patches.dpdk.org/api/patches/119369/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20221031160824.330200-4-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221031160824.330200-4-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221031160824.330200-4-michaelba@nvidia.com", "date": "2022-10-31T16:08:22", "name": "[3/5] net/mlx5: fix missing counter elements copies in r2r cases", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d50878d4fe38e16102f5311887543ccdb50e7ea8", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20221031160824.330200-4-michaelba@nvidia.com/mbox/", "series": [ { "id": 25498, "url": "https://patches.dpdk.org/api/series/25498/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=25498", "date": "2022-10-31T16:08:19", "name": "net/mlx5: some counter fixes", "version": 1, "mbox": "https://patches.dpdk.org/series/25498/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/119369/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/119369/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D4313A0540;\n\tMon, 31 Oct 2022 17:09:04 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 12D494161A;\n\tMon, 31 Oct 2022 17:08:51 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2089.outbound.protection.outlook.com [40.107.243.89])\n by mails.dpdk.org (Postfix) with ESMTP id 7E37340E5A\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <jackmin@nvidia.com>", "Subject": "[PATCH 3/5] net/mlx5: fix missing counter elements copies in r2r\n cases", "Date": "Mon, 31 Oct 2022 18:08:22 +0200", "Message-ID": "<20221031160824.330200-4-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221031160824.330200-1-michaelba@nvidia.com>", "References": "<20221031160824.330200-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT081:EE_|DS7PR12MB6094:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a5be50db-9aa6-4a51-6e8f-08dabb5a3038", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n ct5blpE+Aa3pTk7YDngb5e7EkK40rxXomzyXWDWaGEWTk3GA3bnIkoUtAqysg+vr9bqRty4NCFMUCLMoSW+BmyO3mr9hB0ra/PGLuBVAlDrcN2IL3sFg0DH1Fe6vyNvQrIQv5AyyJgO0fhFM+1ZL3sV/Xyzf2bYr49wJ/xWnS2MLqnde8y2rLSgVohoYz7tFO8itli/dWIa7OQsSDZg/OzKep3EzIXBaicgWKrbFFxFK7RZjftQPCrihA71ZF79pvPdpvYzXtz5jmrhTKNXkxGjwsfS8UkSI8gCWVZiEDFlQI+LNYKziAYG4qn7+6qTYQonKcxdaubV/eCfJ/5qQpIZYdSaCkE/8iLvEYXGF5a5H5koviObz5EfA2g80/+NqRopei18S9HT+GY0T2NbYpDSBDBqVjsmCYHL7XXrC/zjbvdRlcyJ92+4r5851BbgdE5Wl014dY3tg2vYtwpCcqsm8Ad97ZLEyY7y5KMkoPHCD4hKRp9nIAGJ4R0+ikLyjxK3zmtlSssxvm+ZAXyCiG2qic0LW9KPLLMWSESNAsWdNvqrIGv+kuW017oOxJ17s7WxcRlrYz4oS313aHFiHiUMq8583qbC3Aq5RyGdOAly+AW/dODX2MVRNbItCOH2LAFpc9wC5wYjDw7OHCGF9cIwQqswAfza9d4+keA0Xrq7BHW0+I8h8+mWLvZZOYDup5VbofK9EQcjXacHQY73GJmMqZL+D4SULntwfQEz9BstneVSIujlHnGCMqycL40z4bDrcdkCehAnsWNVS0mA+0A==", "X-Forefront-Antispam-Report": "CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(39860400002)(396003)(346002)(376002)(451199015)(36840700001)(46966006)(40470700004)(6666004)(426003)(47076005)(7636003)(36860700001)(40460700003)(356005)(82740400003)(86362001)(2906002)(5660300002)(8676002)(70206006)(41300700001)(4326008)(2616005)(6286002)(82310400005)(70586007)(107886003)(7696005)(54906003)(186003)(336012)(1076003)(478600001)(316002)(8936002)(6916009)(26005)(55016003)(40480700001)(83380400001)(36756003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Oct 2022 16:08:45.4927 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a5be50db-9aa6-4a51-6e8f-08dabb5a3038", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT081.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB6094", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The __hws_cnt_r2rcpy() function copies elements from one zero-copy ring\nto another zero-copy ring in place.\nThis routine needs to consider the situation that the address was given\nby source and destination could be both wrapped.\n\nIt uses 4 different \"n\" local variables to manage it:\n - n: Number of elements to copy in total.\n - n1: Number of elements to copy from ptr1, it is the minimal value\n from source/dest n1 field.\n - n2: Number of elements to copy from src->ptr1 to dst->ptr2 or from\n src->ptr2 to dst->ptr1, this variable is 0 when both source and\n dest n1 field are equal.\n - n3: Number of elements to copy from src->ptr2 to dst->ptr2.\n\nThe function copies the first n1 elements. If n2 isn't zero it copies\nmore elements and check whether n3 is zero.\nThis logic is wrong since n3 may be bigger than zero even when n2 is\nzero. This scenario is commonly happening in counters when the internal\nmlx5 service thread copies elements from the reset ring into the reuse\nring.\n\nThis patch changes the function to copy n3 regardless of n2 value.\n\nFixes: 4d368e1da3a4 (\"net/mlx5: support flow counter action for HWS\")\nCc: jackmin@nvidia.com\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Xiaoyu Min <jackmin@nvidia.com>\n---\n drivers/net/mlx5/mlx5_hws_cnt.h | 7 +++----\n 1 file changed, 3 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_hws_cnt.h b/drivers/net/mlx5/mlx5_hws_cnt.h\nindex 196604aded..6e371f1929 100644\n--- a/drivers/net/mlx5/mlx5_hws_cnt.h\n+++ b/drivers/net/mlx5/mlx5_hws_cnt.h\n@@ -281,11 +281,10 @@ __hws_cnt_r2rcpy(struct rte_ring_zc_data *zcdd, struct rte_ring_zc_data *zcds,\n \t\td3 = zcdd->ptr2;\n \t}\n \tmemcpy(d1, s1, n1 * sizeof(cnt_id_t));\n-\tif (n2 != 0) {\n+\tif (n2 != 0)\n \t\tmemcpy(d2, s2, n2 * sizeof(cnt_id_t));\n-\t\tif (n3 != 0)\n-\t\t\tmemcpy(d3, s3, n3 * sizeof(cnt_id_t));\n-\t}\n+\tif (n3 != 0)\n+\t\tmemcpy(d3, s3, n3 * sizeof(cnt_id_t));\n }\n \n static __rte_always_inline int\n", "prefixes": [ "3/5" ] }